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250 Commits

Author SHA1 Message Date
Craig Topper a6e6febe2c [AVX512] Remove masked logic op intrinsics and autoupgrade them to native IR. 
llvm-svn: 275155
 2016-07-12 05:27:53 +00:00
Craig Topper 70610cf7b6 [X86] Remove and autoupgrade 512-bit non-temporal store intrinsics. 
llvm-svn: 274966
 2016-07-09 04:38:27 +00:00
Craig Topper f7bf6de0af [AVX512] Remove and autoupgrade a duplicate set of 512-bit masked shift intrinsics. 
I'm not sure if clang ever used these builtin names or not.

llvm-svn: 274827
 2016-07-08 06:14:47 +00:00
Simon Pilgrim 9769428e08 [X86][AVX512] Remove vector BROADCAST builtins. 
llvm-svn: 274555
 2016-07-05 14:49:58 +00:00
Craig Topper 5d16cd9d63 [AVX512] Remove masked VPERMD/VPERMQ/VPERMILPS/VPERMILPD intrinsics. They were autoupgraded to native IR in r274506 and r274506. 
llvm-svn: 274519
 2016-07-04 19:58:38 +00:00
Simon Pilgrim 77dda7c2e0 [X86][AVX512] Converted the MOVDDUP/MOVSLDUP/MOVSHDUP masked intrinsics to generic IR 
llvm-svn: 274443
 2016-07-02 17:16:41 +00:00
Craig Topper 597aa42fec [AVX512] Remove masked unpack intrinsics and autoupgrade to vectorshuffle and selects. 
llvm-svn: 273543
 2016-06-23 07:37:33 +00:00
Craig Topper 0a0fb0fda1 [AVX512] Remove the masked vpcmpeq/vcmpgt intrinsics and autoupgrade them to native icmps. 
llvm-svn: 273240
 2016-06-21 03:53:24 +00:00
Igor Breger e59165ca63 [AVX512] [AVX512/AVX][Intrinsics] Fix Variable Bit Shift Right Arithmetic intrinsic lowering. 
Differential Revision: http://reviews.llvm.org/D20897

llvm-svn: 273138
 2016-06-20 07:05:43 +00:00
Sanjay Patel 0e9afea3c8 [x86] autoupgrade and remove AVX2 integer min/max intrinsics 
This will (hopefully very temporarily) break clang.
The clang side of this should be the next commit.

llvm-svn: 272932
 2016-06-16 18:44:20 +00:00
Sanjay Patel 51ab757941 [x86] autoupgrade and remove SSE2/SSE41 integer min/max intrinsics 
Follow-up to:
http://reviews.llvm.org/rL272806
http://reviews.llvm.org/rL272807

llvm-svn: 272907
 2016-06-16 15:48:30 +00:00
David Majnemer 248190ba69 [X86] Remove llvm.x86.bit.scan.{forward,reverse}.32 
The need for these intrinsics has been obviated by r272564 which
reimplements their functionality using generic IR.

llvm-svn: 272566
 2016-06-13 17:33:13 +00:00
Craig Topper 13cf7cac07 [AVX512] Remove maksed pshufd, pshuflw, and phufhw intrinsics and autoupgrade them to selects and shufflevector. 
llvm-svn: 272527
 2016-06-13 02:36:48 +00:00
Craig Topper 1067986c5b [X86] Remove sse2 pshufd/pshuflw/pshufhw intrinsics and upgrade them to shufflevector. 
llvm-svn: 272510
 2016-06-12 14:11:32 +00:00
Craig Topper 251030babe [AVX512] Remove the masked palignr intrinsics that I forgot to remove when I added auto-upgrade code to turn them into shufflevectors and selects. 
llvm-svn: 272497
 2016-06-12 04:14:13 +00:00
Simon Pilgrim f718682eb9 [X86][AVX512] Dropped avx512 VPSLLDQ/VPSRLDQ intrinsics 
Auto-upgrade to generic shuffles like sse/avx2 implementations now that we can lower to VPSLLDQ/VPSRLDQ 

llvm-svn: 272308
 2016-06-09 21:09:03 +00:00
Igor Breger f635367e2b [AVX512] Remove masked_move/blendm intrinsic from back-end. 
This is complement patch to D21060.

Differential Revision: http://reviews.llvm.org/D21174

llvm-svn: 272257
 2016-06-09 11:46:55 +00:00
Craig Topper 6ae375c9ba [X86] Use smaller types to shrink the intrinsic lowering tables by about 12K. 
llvm-svn: 271776
 2016-06-04 04:32:17 +00:00
Craig Topper 5250634334 [X86] Use X86ISD::ABS for lowering pabs SSSE3/AVX intrinsics to match AVX512. Should allow those intrinsics to use the EVEX encoded instructions and get the extra registers when available. 
llvm-svn: 271775
 2016-06-04 04:32:15 +00:00
Simon Pilgrim e85506b6e0 [X86][XOP] Support for VPERMIL2PD/VPERMIL2PS 2-input shuffle instructions 
This patch begins adding support for lowering to the XOP VPERMIL2PD/VPERMIL2PS shuffle instructions - adding the X86ISD::VPERMIL2 opcode and cleaning up the usage.

The internal llvm intrinsics were assuming the shuffle mask operand was the same type as the float/double input operands (I guess to simplify the intrinsic definitions in X86InstrXOP.td to a single value type). These needed changing to integer types (matching the clang builtin and the AMD intrinsics definitions), an auto upgrade path is added to convert old calls.

Mask decoding/target shuffle support will be added in future patches.

Differential Revision: http://reviews.llvm.org/D20049

llvm-svn: 271633
 2016-06-03 08:06:03 +00:00
Craig Topper 5bb9cda620 [AVX512] Remove LOADA/LOADU/STOREA/STOREU intrinsic types now that they are unused. 
llvm-svn: 271479
 2016-06-02 04:19:40 +00:00
Craig Topper f10fbfa738 [AVX512] Remove masked load intrinsics. Clang now emits generic masked load intrinsics instead. 
The intrinsics will be autoupgraded to the same generic masked loads.

llvm-svn: 271478
 2016-06-02 04:19:36 +00:00
Michael Zuckerman 6a894956fc Adding back-end support to two bit scanning intrinsics 
Adding LLVM back-end support to two intrinsics dealing with bit scan: _bit_scan_forward and _bit_scan_reverse.
Their functionality is as described in Intel intrinsics guide:
https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_forward&expand=371,370
https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_reverse&expand=371,370

Commit on behalf of Omer Paparo Bivas


Differential Revision: http://reviews.llvm.org/D19915

llvm-svn: 271386
 2016-06-01 12:02:37 +00:00
Craig Topper 4f2d5a68d3 Revert r271362 "[AVX512] Remove masked load intrinsics. Clang now emits generic masked load intrinsics instead." 
Looks like something isn't quite right still. Also forgot to move the test cases to an autoupgrade test.

llvm-svn: 271363
 2016-06-01 05:57:55 +00:00
Craig Topper dacd9d2bac [AVX512] Remove masked load intrinsics. Clang now emits generic masked load intrinsics instead. 
The intrinsics will be autoupgraded to the same generic masked loads.

llvm-svn: 271362
 2016-06-01 05:35:16 +00:00
Igor Breger 52bd1d5fcc Fix intrinsic vbroadcast{i32|f32}x2 lowering. 
Differential Revision: http://reviews.llvm.org/D20780

llvm-svn: 271254
 2016-05-31 07:43:39 +00:00
Craig Topper 50f85c22c5 [AVX512] Remove masked store intrinsics. Clang now emits generic masked store intrinsics instead. 
The intrinsics will be autoupgraded to the same generic masked stores.

llvm-svn: 271245
 2016-05-31 01:50:02 +00:00
Simon Pilgrim 9602d678cb [X86][SSE] (Reapplied) Replace (V)PMOVSX and (V)PMOVZX integer extension intrinsics with generic IR (llvm) 
This patch removes the llvm intrinsics VPMOVSX and (V)PMOVZX sign/zero extension intrinsics and auto-upgrades to SEXT/ZEXT calls instead. We already did this for SSE41 PMOVSX sometime ago so much of that implementation can be reused.

Reapplied now that the the companion patch (D20684) removes/auto-upgrade the clang intrinsics has been committed.

Differential Revision: http://reviews.llvm.org/D20686

llvm-svn: 271131
 2016-05-28 18:03:41 +00:00
Simon Pilgrim 4642a57fbf Revert: r270973 - [X86][SSE] Replace (V)PMOVSX and (V)PMOVZX integer extension intrinsics with generic IR (llvm) 
llvm-svn: 270976
 2016-05-27 09:02:25 +00:00
Simon Pilgrim c013e5737b [X86][SSE] Replace (V)PMOVSX and (V)PMOVZX integer extension intrinsics with generic IR (llvm) 
This patch removes the llvm intrinsics VPMOVSX and (V)PMOVZX sign/zero extension intrinsics and auto-upgrades to SEXT/ZEXT calls instead. We already did this for SSE41 PMOVSX sometime ago so much of that implementation can be reused.

A companion patch (D20684) removes/auto-upgrade the clang intrinsics.

Differential Revision: http://reviews.llvm.org/D20686

llvm-svn: 270973
 2016-05-27 08:49:15 +00:00
Igor Breger 23c2090606 [llvm][AVX512][intrinsics] Fix vperm{b|w|d|q|ps|pd} intrinsics. Index is second argument to buildin function but it is first instruction operand. 
Differential Revision: http://reviews.llvm.org/D20515

llvm-svn: 270548
 2016-05-24 11:06:22 +00:00
Michael Zuckerman a63a129749 [Clang][AVX512][intrinsics] Fix rcp and sqrt intrinsics. 
Differential Revision: http://reviews.llvm.org/D20438

llvm-svn: 270322
 2016-05-21 14:44:18 +00:00
Michael Zuckerman 11b55b29d1 [Clang][AVX512][intrinsics] Fix vscalef intrinsics. 
Differential Revision: http://reviews.llvm.org/D20324

llvm-svn: 270321
 2016-05-21 11:09:53 +00:00
Craig Topper b395105584 [X86] Convert some SSE2/AVX2 intrinsics to ISD opcodes during lowering instead of pattern matching the intrinsics. This unifies handling with AVX512 and allows these intrinsics to select EVEX encoded instructions to increase available registers. 
llvm-svn: 270310
 2016-05-21 03:52:28 +00:00
Craig Topper 258f874bb9 [AVX512] Make the permd intrinsics take a 32-bit immediate to match the software spec. 
llvm-svn: 269579
 2016-05-14 21:13:20 +00:00
Elena Demikhovsky e79b716daf Fixed lowering of _comi_ intrinsics from all sets - SSE/SSE2/AVX/AVX-512 
Differential revision http://reviews.llvm.org/D19261

llvm-svn: 269569
 2016-05-14 15:06:09 +00:00
Craig Topper d8a9c0d120 [AVX512] Fix types for pshufd intrinsics. The immediate is the second argument and the mask is the 4th argument. Also move the 128/256 tests to the right test file. 
Prior to this the immediate was a strange 16-bits and the 512-bit intrinsic couldn't receive the full 16 mask bits it needs.

llvm-svn: 269526
 2016-05-14 00:47:18 +00:00
Simon Pilgrim cd0dfc93eb [X86][SSE] Support for MOVMSK signbit extraction instructions 
Add support for lowering with the MOVMSK instruction to extract vector element signbits to a GPR.

This is an early step towards more optimal handling of vector comparison results.

Differential Revision: http://reviews.llvm.org/D18741

llvm-svn: 265266
 2016-04-03 18:22:03 +00:00
Simon Pilgrim 572ca71573 [X86][XOP] Support for VPPERM byte shuffle instruction 
This patch begins adding support for lowering to the XOP VPPERM instruction - adding the X86ISD::VPPERM opcode.

Differential Revision: http://reviews.llvm.org/D18189

llvm-svn: 264260
 2016-03-24 11:52:43 +00:00
Simon Pilgrim abcee45b7a [X86][AVX] Better support for the variable mask form of VPERMILPD/VPERMILPS 
The variable mask form of VPERMILPD/VPERMILPS were only partially implemented, with much of it still performed as an intrinsic.

This patch properly defines the instructions in terms of X86ISD::VPERMILPV, permitting the opcode to be easily combined as a target shuffle.

Differential Revision: http://reviews.llvm.org/D17681

llvm-svn: 262635
 2016-03-03 18:13:53 +00:00
Michael Zuckerman c4d054fa4a [LLVM][AVX512] PSRLWI Chnage imm8 to int 
Differential Revision: http://reviews.llvm.org/D17753

llvm-svn: 262592
 2016-03-03 08:54:05 +00:00
Michael Zuckerman 927fdaee88 [LLVM][AVX512]PSRAWI Change imm8 to int. 
Differential Revision: http://reviews.llvm.org/D17705

llvm-svn: 262480
 2016-03-02 12:05:07 +00:00
Michael Zuckerman 433b241570 [LLVM][AVX512] PSRL{DI|QI} Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D17713

llvm-svn: 262353
 2016-03-01 17:46:32 +00:00
Michael Zuckerman 7878888690 [AVX512][PSRAQ][PSRAD] Change imm8 to int. 
Differential Revision: http://reviews.llvm.org/D17692

llvm-svn: 262320
 2016-03-01 11:36:23 +00:00
Michael Zuckerman 96836fc81c [AVX512][PSLLW ][PSLLV] Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D17684

llvm-svn: 262176
 2016-02-28 07:32:10 +00:00
Simon Pilgrim 3b42ca0760 Strip trailing whitespace. NFCI. 
llvm-svn: 262131
 2016-02-27 11:49:16 +00:00
Michael Zuckerman a1f2d27da2 [LLVM][AVX512][PSHUFHW ][PSHUFLW ] Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D17538

llvm-svn: 261725
 2016-02-24 08:39:05 +00:00
Michael Zuckerman 724dc3b20c [AVX512][PRORQ][PRORD] Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D17024

llvm-svn: 261198
 2016-02-18 09:52:12 +00:00
Ahmed Bougacha f3cccab1e0 [X86] Remove the now-unused X86ISD::PSIGN. NFC. 
llvm-svn: 261025
 2016-02-16 22:14:12 +00:00
Michael Zuckerman 529c27f408 [AVX512][PROLQ][PROLD] Change imm8 to int 
Differential Revision: http://reviews.llvm.org/D16983

llvm-svn: 260101
 2016-02-08 15:13:32 +00:00
Asaf Badouh ad5c3fc47d [X86][AVX512] add intrinsics of Scalar FP to integer conversion with rounding mode 
Differential Revision: http://reviews.llvm.org/D16629

llvm-svn: 260033
 2016-02-07 14:59:13 +00:00
Igor Breger 0aeda37464 AVX512: VPBROADCASTB/W/D/Q from GPR intrinsics implementation. 
Differential Revision: http://reviews.llvm.org/D16813

llvm-svn: 260024
 2016-02-07 08:30:50 +00:00
Michael Zuckerman 7d73360479 [AVX512] add vfmadd132ss and vfmadd132sd Intrinsic 
Differential Revision: http://reviews.llvm.org/D16589

llvm-svn: 259789
 2016-02-04 14:41:08 +00:00
Asaf Badouh 5a3a0231f4 [X86][AVX512VBMI] add encoding and intrinsics for Multishift 
Differential Revision: http://reviews.llvm.org/D16399

llvm-svn: 259363
 2016-02-01 15:48:21 +00:00
Asaf Badouh 42852d99e7 [X86][AVX512] small fix in ptestm intrinsics 
move ptestm{q|d} intrinsics from patterns form (in td file) to the intrinsics table

Differential Revision: http://reviews.llvm.org/D16633

llvm-svn: 259029
 2016-01-28 08:33:22 +00:00
Benjamin Kramer 391be792f2 One more batch of self-containing headers. 
llvm-svn: 258974
 2016-01-27 19:29:56 +00:00
Reid Kleckner 86ff2689a5 Sort intrinsics by LLVM intrinsic name, rather than tablegen def name 
Step one towards using a simple binary search to lookup intrinsic IDs
instead of our crazy table generated switch+memcmp+startswith code that
makes Function.cpp take about a minute to compile.  See PR24785 and
PR11951 for why we should do this.

The X86 backend contains tables that need to be sorted on intrinsic ID,
so reorder those.

llvm-svn: 258757
 2016-01-26 00:55:00 +00:00
Michael Zuckerman 1bd7f993fc [AVX512] Adding PTESTNMB/D/W/Q instruction 
Differential Revision: http://reviews.llvm.org/D16520

llvm-svn: 258688
 2016-01-25 14:43:23 +00:00
Michael Zuckerman 19670d479a [AVX512] Adding PTESTMB/W/D/Q instruction 
Differential Revision: http://reviews.llvm.org/D16519

llvm-svn: 258686
 2016-01-25 13:27:32 +00:00
Asaf Badouh 655822ab7e [X86][IFMA] adding intrinsics and encoding for multiply and add of unsigned 52bit integer 
VPMADD52LUQ - Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Qword Accumulators
 VPMADD52HUQ - Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to 64-bit Accumulators

Differential Revision: http://reviews.llvm.org/D16407

llvm-svn: 258680
 2016-01-25 11:14:24 +00:00
Igor Breger 1e5bafbc82 AVX512: VMOVDQU8/16/32/64 (load) intrinsic implementation. 
Differential Revision: http://reviews.llvm.org/D16137

llvm-svn: 258657
 2016-01-24 08:04:33 +00:00
Igor Breger 7a000f5bb2 AVX512: Masked move intrinsic implementation. 
Implemented intrinsic for the follow instructions (reg move) : VMOVDQU8/16, VMOVDQA32/64, VMOVAPS/PD.

Differential Revision: http://reviews.llvm.org/D16316

llvm-svn: 258398
 2016-01-21 14:18:11 +00:00
Michael Zuckerman 21a30a42a9 [AVX512] Adding VPERMT2B and VPERMI2B Intrinsics 
Differential Revision: http://reviews.llvm.org/D16398

llvm-svn: 258397
 2016-01-21 13:36:01 +00:00
Michael Zuckerman 65c40afb03 [AVX512] Adding VPERMB Intrinsics 
Differential Revision: http://reviews.llvm.org/D16296

llvm-svn: 258316
 2016-01-20 15:24:56 +00:00
Igor Breger d3341f5021 AVX512: Store (MOVNTPD, MOVNTPS, MOVNTDQ) using non-temporal hint intrinsic implementation. 
Differential Revision: http://reviews.llvm.org/D16350

llvm-svn: 258309
 2016-01-20 13:11:47 +00:00
Asaf Badouh d4a0d9a78c [X86][AVX512]fix dag & add intrinsics for fixupimm 
cover all width and types (pd/ps/sd/ss) of fixupimm instruction and inrtinsics

Differential Revision: http://reviews.llvm.org/D16313

llvm-svn: 258124
 2016-01-19 14:21:39 +00:00
Igor Breger 239fda676c AVX512: Masked store intrinsic implementation. 
Implemented intrinsic for the follow instructions (store) : VMOVDQU8/16/32/64, VMOVDQA32/64, VMOVAPS/PD, VMOVUPS/PD.

Differential Revision: http://reviews.llvm.org/D16271

llvm-svn: 258047
 2016-01-18 13:52:57 +00:00
Michael Zuckerman ac1b238b0a [AVX512] Adding VPERMW/D/Q VPERMPS/D Intrinsics 
Differential Revision: http://reviews.llvm.org/D16189

llvm-svn: 258008
 2016-01-17 11:33:29 +00:00
Michael Zuckerman ede597c753 [AVX512] Adding VPERMQ VPERMPD Intrinsics 
Differential Revision: http://reviews.llvm.org/D16194

llvm-svn: 258006
 2016-01-17 08:32:14 +00:00
Igor Breger fc96331d88 AVX512: VMOVDQA32/64 (load) intrinsic implementation. 
Differential Revision: http://reviews.llvm.org/D16142

llvm-svn: 257749
 2016-01-14 07:56:04 +00:00
Michael Zuckerman 0e31b22487 [AVX512] Adding PMOVSXBD/W/Q , PMOVZSDQ and PMOVZSWD/Q Intrinsics . 
Differential Revision: http://reviews.llvm.org/D16111 

llvm-svn: 257604
 2016-01-13 14:59:19 +00:00
Michael Zuckerman 43cea85db9 [AVX512] Adding PMOVZXBD/W/Q , PMOVZXDQ and PMOVZXWD/Q Intrinsics 
Differential Revision:http://reviews.llvm.org/D16071

llvm-svn: 257601
 2016-01-13 14:25:21 +00:00
Michael Zuckerman 298a680c80 [AVX512] adding PRORQ , PRORD , PRORLVQ and PRORLVD Intrinsics 
Differential Revision: http://reviews.llvm.org/D16052

llvm-svn: 257594
 2016-01-13 12:39:33 +00:00
Michael Zuckerman 2ddcbcf464 [AVX512] adding PROLQ and PROLD Intrinsics 
Differential Revision: http://reviews.llvm.org/D16048

llvm-svn: 257523
 2016-01-12 21:19:17 +00:00
Igor Breger ea8e8e9f97 AVX512: VPMOVAPS/PD and VPMOVUPS/PD (load) intrinsic implementation. 
Differential Revision: http://reviews.llvm.org/D16042

llvm-svn: 257463
 2016-01-12 10:02:32 +00:00
Michael Zuckerman 885f61c534 [AVX512] add PRORVQ and PRORVD Intrinsic 
Differential Revision:http://reviews.llvm.org/D15955

llvm-svn: 257283
 2016-01-10 09:16:41 +00:00
Michael Zuckerman 3aca221b31 [AVX512] add PSLLW and PSLLV Intrinsic 
Differential Revision: http://reviews.llvm.org/D15889

llvm-svn: 257070
 2016-01-07 16:02:51 +00:00
Michael Zuckerman 354152d590 [AVX512] add PSRAV Intrinsic 
Differential Revision: http://reviews.llvm.org/D15856

llvm-svn: 257063
 2016-01-07 14:42:20 +00:00
Michael Zuckerman a6df006b50 [AVX512] add PSHUFHW and PSHUFLW Intrinsic 
Differential Revision: http://reviews.llvm.org/D15925

llvm-svn: 257056
 2016-01-07 12:35:43 +00:00
Michael Zuckerman 4a1566827d [AVX512] add PSHUFD Intrinsic 
Differential Revision: http://reviews.llvm.org/D15934

llvm-svn: 257044
 2016-01-07 09:24:12 +00:00
Michael Zuckerman 5cbae95916 [AVX512] add PSLLD and PSLLQ Intrinsic 
Differential Revision: http://reviews.llvm.org/D15885

llvm-svn: 256840
 2016-01-05 15:17:39 +00:00
Michael Zuckerman cf0b6db9ef [AVX512] add PSRAD and PSRAQ Intrinsic 
Differential Revision: http://reviews.llvm.org/D15851

llvm-svn: 256754
 2016-01-04 13:45:45 +00:00
Michael Zuckerman 000fca44a8 [AVX512] add PSRAW Intrinsic 
Differential Revision: http://reviews.llvm.org/D15850

llvm-svn: 256751
 2016-01-04 12:50:36 +00:00
Michael Zuckerman 068bc2f219 [AVX512] add PSRLV Intrinsic 
Differential Revision: http://reviews.llvm.org/D15838

llvm-svn: 256747
 2016-01-04 11:39:06 +00:00
Michael Zuckerman 0dc468880d [AVX512] add PSRLQ and PSRLD Intrinsic 
Differential Revision: http://reviews.llvm.org/D15770

llvm-svn: 256673
 2015-12-31 15:22:04 +00:00
Michael Zuckerman 80821ee77c [AVX512] add PSRLW Intrinsic 
Differential Revision: http://reviews.llvm.org/D15751

llvm-svn: 256558
 2015-12-29 13:04:35 +00:00
Asaf Badouh fba562004b [X86][AVX512] Lower broadcast sub vector to vector inrtrinsics 
lower broadcast<type>x<vector> to shuffles.
 there are two cases:
1.src is 128 bits and dest is 512 bits: in this case we will lower it to shuffle with imm = 0.
2.src is 256 bit and dest is 512 bits: in this case we will lower it to shuffle with imm = 01000100b (0x44) that way we will broadcast the 256bit source: ymm[0,1,2,3] => zmm[0,1,2,3,0,1,2,3] then it will mask it with the passthru value (in case it's mask op).



Differential Revision: http://reviews.llvm.org/D15790

llvm-svn: 256490
 2015-12-28 08:26:26 +00:00
Asaf Badouh 5546f51011 [X86][AVX512] add fp scalar broadcast intrinsics 
Differential Revision: http://reviews.llvm.org/D15790

llvm-svn: 256489
 2015-12-28 08:09:25 +00:00
Igor Breger 756c289dd8 AVX512: Change VPMOVB2M DAG lowering , use CVT2MASK node instead TRUNCATE. 
Fix TRUNCATE lowering vector to vector i1, use LSB and not MSB.
Implement VPMOVB/W/D/Q2M intrinsic.

Differential Revision: http://reviews.llvm.org/D15675

llvm-svn: 256470
 2015-12-27 13:56:16 +00:00
Igor Breger 268f6f53c5 AVX512: VPMOVM2B/W/D/Q intrinsic implementation. 
Differential Revision: http://reviews.llvm.org//D15747

llvm-svn: 256364
 2015-12-24 07:11:53 +00:00
Asaf Badouh 13ffa4bf7c [X86][AVX512] Add rcp14 and rsqrt14 intrinsics 
Differential Revision: http://reviews.llvm.org/D15414

llvm-svn: 256237
 2015-12-22 11:40:04 +00:00
Igor Breger 3ab6f17530 AVX-512: implement kunpck intrinsics. 
Differential Revision: http://reviews.llvm.org/D14821

llvm-svn: 254908
 2015-12-07 13:25:18 +00:00
Asaf Badouh 41ecf460fa [X86][AVX512] add vmovss/sd missing encoding 
Differential Revision: http://reviews.llvm.org/D14701

llvm-svn: 254875
 2015-12-06 13:26:56 +00:00
Asaf Badouh 2489f350c0 [X86][AVX512] add comi with Sae 
add builtin_ia32_vcomisd and builtin_ia32_vcomisd

Differential Revision: http://reviews.llvm.org/D14331

llvm-svn: 254493
 2015-12-02 08:17:51 +00:00
Craig Topper fbde7aa13a [X86] Remove duplicate entries from intrinsics tables and add asserts to verify there are no others. 
llvm-svn: 254274
 2015-11-29 23:18:32 +00:00
Craig Topper 0009656335 [X86] Split ISD node for Vfpclass and Vfpclasss so that we can write strong type constraints for each that don't cause ambiguous isel. 
llvm-svn: 254172
 2015-11-26 19:41:34 +00:00
Cong Hou db6220f84d [X86] Fix several issues related to X86's psadbw instruction. 
This patch fixes the following issues:

1. Fix the return type of X86psadbw: it should not be the same type of inputs.
   For vNi8 inputs the output should be vMi64, where M = N/8.
2. Fix the return type of int_x86_avx512_psad_bw_512 accordingly.
3. Fix the definiton of PSADBW, VPSADBW, and VPSADBWY accordingly.
4. Adjust the return type when building a DAG node of X86ISD::PSADBW type.
5. Update related tests.


Differential revision: http://reviews.llvm.org/D14897

llvm-svn: 254010
 2015-11-24 19:51:26 +00:00
Cong Hou bed60d35ed [X86][SSE] Detect AVG pattern during instruction combine for SSE2/AVX2/AVX512BW. 
This patch detects the AVG pattern in vectorized code, which is simply
c = (a + b + 1) / 2, where a, b, and c have the same type which are vectors of
either unsigned i8 or unsigned i16. In the IR, i8/i16 will be promoted to
i32 before any arithmetic operations. The following IR shows such an example:

%1 = zext <N x i8> %a to <N x i32>
%2 = zext <N x i8> %b to <N x i32>
%3 = add nuw nsw <N x i32> %1, <i32 1 x N>
%4 = add nuw nsw <N x i32> %3, %2
%5 = lshr <N x i32> %N, <i32 1 x N>
%6 = trunc <N x i32> %5 to <N x i8>

and with this patch it will be converted to a X86ISD::AVG instruction.

The pattern recognition is done when combining instructions just before type
legalization during instruction selection. We do it here because after type
legalization, it is much more difficult to do pattern recognition based
on many instructions that are doing type conversions. Therefore, for
target-specific instructions (like X86ISD::AVG), we need to take care of type
legalization by ourselves. However, as X86ISD::AVG behaves similarly to
ISD::ADD, I am wondering if there is a way to legalize operands and result
types of X86ISD::AVG together with ISD::ADD. It seems that the current design
doesn't support this idea.

Tests are added for SSE2, AVX2, and AVX512BW and both i8 and i16 types of
variant vector sizes.


Differential revision: http://reviews.llvm.org/D14761

llvm-svn: 253952
 2015-11-24 05:44:19 +00:00
Igor Breger 1f78296869 AVX512: Implemented encoding, intrinsics and DAG lowering for VMOVDDUP instructions. 
Differential Revision: http://reviews.llvm.org/D14702

llvm-svn: 253548
 2015-11-19 08:26:56 +00:00
Asaf Badouh 0d957b8b09 [X86][AVX512CD] add mask broadcast intrinsics 
Differential Revision: http://reviews.llvm.org/D14573

llvm-svn: 253450
 2015-11-18 09:42:45 +00:00