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Author SHA1 Message Date
Sanjay Patel 8716b3cbe0 remove FIXME comment (fixed with r284424); NFC 
llvm-svn: 284427
 2016-10-17 21:08:39 +00:00
Sanjay Patel 523cd8290a [DAG] use isConstOrConstSplat in ComputeNumSignBits to optimize SRA 
The scalar version of this pattern was noted in:
https://reviews.llvm.org/D25485

and fixed with:
https://reviews.llvm.org/rL284395

More refactoring of the constant/splat helpers is needed and will happen in follow-up patches.

Differential Revision: https://reviews.llvm.org/D25685

llvm-svn: 284424
 2016-10-17 20:41:39 +00:00
Sanjay Patel 2cf6bfaf73 [DAG] optimize away an arithmetic-right-shift of a 0 or -1 value 
This came up as part of:
https://reviews.llvm.org/D25485

Note that the vector case is missed because ComputeNumSignBits() is deficient for vectors.

llvm-svn: 284395
 2016-10-17 15:58:28 +00:00
Sanjay Patel 95db75791e [x86] add tests to show missing DAG folds for arithmetic-shift-right 
llvm-svn: 284394
 2016-10-17 15:44:59 +00:00
Sanjay Patel 832962110a [x86] auto-generate checks 
llvm-svn: 284393
 2016-10-17 15:38:41 +00:00
Michael Kuperstein e75e6e2a23 [X86] Improve shift combining 
This folds (ashr (shl a, [56,48,32,24,16]), SarConst)
into       (shl, (sext (a), [56,48,32,24,16] - SarConst))
or into    (lshr, (sext (a), SarConst - [56,48,32,24,16]))
depending on sign of (SarConst - [56,48,32,24,16])

sexts in X86 are MOVs.
The MOVs have the same code size as above SHIFTs (only SHIFT by 1 has lower code size).
However the MOVs have 2 advantages to SHIFTs on x86:
1. MOVs can write to a register that differs from source.
2. MOVs accept memory operands.

This fixes PR24373.

Patch by: evgeny.v.stupachenko@intel.com
Differential Revision: http://reviews.llvm.org/D13161

llvm-svn: 255761
 2015-12-16 11:22:37 +00:00