11 Commits

Author	SHA1	Message	Date
Fangrui Song	7e5508e6a8	[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests	2020-12-30 15:28:11 -08:00
Michael Munday	e28b6a60bc	[RISCV][NFC] Regenerate RISCV CodeGen tests ... Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841	2020-12-09 19:42:49 +00:00
Luis Marques	3d0fbafd0b	[RISCV] Switch to the Machine Scheduler ... Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106	2019-09-17 11:15:35 +00:00
Luis Marques	2d550d19b3	Revert Patch from Phabricator ... This reverts r372092 (git commit e38695a025) llvm-svn: 372104	2019-09-17 10:52:09 +00:00
Luis Marques	e38695a025	Patch from Phabricator ... llvm-svn: 372092	2019-09-17 09:43:08 +00:00
Alex Bradbury	8a70468a27	[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer ... This follows similar logic in the ARM and Mips backends, and allows the free use of s0 in functions without a dedicated frame pointer. The changes in callee-saved-gprs.ll most clearly show the effect of this patch. llvm-svn: 356063	2019-03-13 16:33:45 +00:00
Alex Bradbury	d834d8301d	[RISCV] Add RV64F codegen support ... This requires a little extra work due tothe fact i32 is not a legal type. When call lowering happens post-legalisation (e.g. when an intrinsic was inserted during legalisation). A bitcast from f32 to i32 can't be introduced. This is similar to the challenges with RV32D. To handle this, we introduce target-specific DAG nodes that perform bitcast+anyext for f32->i64 and trunc+bitcast for i64->f32. Differential Revision: https://reviews.llvm.org/D53235 llvm-svn: 352807	2019-01-31 22:48:38 +00:00
Sameer AbuAsal	1dc0a8fb18	[RISCV] Separate base from offset in lowerGlobalAddress ... Summary: When lowering global address, lower the base as a TargetGlobal first then create an SDNode for the offset separately and chain it to the address calculation This optimization will create a DAG where the base address of a global access will be reused between different access. The offset can later be folded into the immediate part of the memory access instruction. With this optimization we generate: lui a0, %hi(s) addi a0, a0, %lo(s) ; shared base address. addi a1, zero, 20 ; 2 instructions per access. sw a1, 44(a0) addi a1, zero, 10 sw a1, 8(a0) addi a1, zero, 30 sw a1, 80(a0) Instead of: lui a0, %hi(s+44) ; 3 instructions per access. addi a1, zero, 20 sw a1, %lo(s+44)(a0) lui a0, %hi(s+8) addi a1, zero, 10 sw a1, %lo(s+8)(a0) lui a0, %hi(s+80) addi a1, zero, 30 sw a1, %lo(s+80)(a0) Which will save one instruction per access. Reviewers: asb, apazos Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, apazos, asb, llvm-commits Differential Revision: https://reviews.llvm.org/D46989 llvm-svn: 332641	2018-05-17 18:14:53 +00:00
Shiva Chen	d58bd8dc4a	[RISCV] Expand function call to "call" pseudoinstruction ... To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827	2018-04-25 14:19:12 +00:00
Alex Bradbury	77d5927a1c	[RISCV] Add tests missed from r327979 ... llvm-svn: 328102	2018-03-21 14:50:27 +00:00
Alex Bradbury	80c8eb7696	[RISCV] Add codegen for RV32F floating point load/store ... As part of this, add support for load/store from the constant pool. This is used to materialise f32 constants. llvm-svn: 327979	2018-03-20 13:26:12 +00:00