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5 Commits

Author SHA1 Message Date
Michael Munday e28b6a60bc [RISCV][NFC] Regenerate RISCV CodeGen tests 
Regenerated using:

./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll

This has added comments to spill-related instructions and added @plt to
some symbols.

Differential Revision: https://reviews.llvm.org/D92841
 2020-12-09 19:42:49 +00:00
Shiva Chen ff55e2e047 [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore 
We would like to split the SP adjustment to reduce the instructions in
prologue and epilogue as the following case. In this way, the offset of
the callee saved register could fit in a single store.

    add     sp,sp,-2032
    sw      ra,2028(sp)
    sw      s0,2024(sp)
    sw      s1,2020(sp)
    sw      s3,2012(sp)
    sw      s4,2008(sp)
    add     sp,sp,-64

Differential Revision: https://reviews.llvm.org/D68011

llvm-svn: 373688
 2019-10-04 02:00:57 +00:00
Shiva Chen a49a16ddd0 [RISCV] Support stack offset exceed 32-bit for RV64 
Differential Revision: https://reviews.llvm.org/D61884

llvm-svn: 371810
 2019-09-13 04:03:32 +00:00
Shiva Chen ea530ba3ed Revert "[RISCV] Support stack offset exceed 32-bit for RV64" 
This reverts commit 1c340c62058d4115d21e5fa1ce3a0d094d28c792.

llvm-svn: 371809
 2019-09-13 04:03:24 +00:00
Shiva Chen eaa230fe3c [RISCV] Support stack offset exceed 32-bit for RV64 
Differential Revision: https://reviews.llvm.org/D61884

llvm-svn: 371806
 2019-09-13 02:50:13 +00:00