23bcf06a15
[Hexagon] Add/fix patterns for 32/64-bit vector compares and logical ops
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llvm-svn: 330330
2018-04-19 14:24:31 +00:00
9915291ab8
[Hexagon] Fix zero-extending non-HVX bool vectors
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llvm-svn: 327712
2018-03-16 15:03:37 +00:00
2c3edf0567
[Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned ones
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This is a follow-up to r325169, this time for all types, not just HVX
vector types.
Disable this by default, since it's not always safe.
llvm-svn: 326915
2018-03-07 17:27:18 +00:00
d70f5a0eb4
[Hexagon] Add patterns for compares of i1 values
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llvm-svn: 326220
2018-02-27 18:31:46 +00:00
893a6b89ff
[DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in a canonical manner.
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Summary:
There are transformation that change setcc into other constructs, and transform that try to reconstruct a setcc from the brcond condition. Depending on what order these transform are done, the end result differs.
Most of the time, it is preferable to get a setcc as a brcond argument (and this is why brcond try to recreate the setcc in the first place) so we ensure this is done every time by also doing it at the setcc level when the only user is a brcond.
Reviewers: spatel, hfinkel, niravd, craig.topper
Subscribers: nhaehnle, llvm-commits
Differential Revision: https://reviews.llvm.org/D41235
llvm-svn: 325892
2018-02-23 11:50:42 +00:00
ad83ce4cb4
[Hexagon] Split HVX vector pair loads/stores, expand unaligned loads
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llvm-svn: 325169
2018-02-14 20:46:06 +00:00
8abaf8954a
[Hexagon] Extract HVX lowering and selection into HVX-specific files, NFC
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llvm-svn: 324392
2018-02-06 20:22:20 +00:00
88f11003a0
[Hexagon] Split HVX operations on vector pairs
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Vector pairs are legal types, but not every operation can work on pairs.
For those operations that are legal for single vectors, generate a concat
of their results on pair halves.
llvm-svn: 324350
2018-02-06 14:24:57 +00:00
69f1d7e370
[Hexagon] Handle lowering of SETCC via setCondCodeAction
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It was expanded directly into instructions earlier. That was to avoid
loads from a constant pool for a vector negation: "xor x, splat(i1 -1)".
Implement ISD opcodes QTRUE and QFALSE to denote logical vectors of
all true and all false values, and handle setcc with negations through
selection patterns.
llvm-svn: 324348
2018-02-06 14:16:52 +00:00
1108ee2496
[Hexagon] Implement HVX codegen for vector shifts
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llvm-svn: 323914
2018-01-31 20:49:24 +00:00
90ca4e8b0c
[Hexagon] Generate constant splats instead of loads from constant pool
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llvm-svn: 323568
2018-01-26 21:54:56 +00:00
5aef4b5997
[Hexagon] Remove unused HexagonISD opcodes, NFC
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llvm-svn: 323324
2018-01-24 14:07:37 +00:00
d5e8a260bb
[Hexagon] Add patterns for sext_inreg of HVX vector types
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llvm-svn: 323250
2018-01-23 19:56:16 +00:00
3780a0e1fa
[Hexagon] Implement basic vector operations on vectors vNi1
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In addition to that, make sure that there are no boolean vector types that
are associated with multiple register classes. Specifically, remove v32i1
and v64i1 from integer register classes. These types will correspond to
results of vector comparisons, and as such should belong to the vector
predicate class. Having them in scalar registers as well makes legalization
ambiguous.
llvm-svn: 323229
2018-01-23 17:53:59 +00:00
7fb738ab71
[Hexagon] Implement signed and unsigned multiply-high for vectors
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llvm-svn: 322499
2018-01-15 18:43:55 +00:00
b0b52618c0
[Hexagon] Even simpler patterns for sign- and zero-extending HVX vectors
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Recommit r321897 with updated testcases.
llvm-svn: 321908
2018-01-05 22:31:11 +00:00
4ed8ef6f8e
Revert r321894: it requires a part of another commit that is not ready yet
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Commit message:
[Hexagon] Add patterns for sext_inreg of HVX vector types
llvm-svn: 321904
2018-01-05 21:57:43 +00:00
9920dab75e
Revert r321897: affected testcases were not updated
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Commit message:
[Hexagon] Even simpler patterns for sign- and zero-extending HVX vectors
llvm-svn: 321902
2018-01-05 21:50:15 +00:00
577d2f2fbd
[Hexagon] Even simpler patterns for sign- and zero-extending HVX vectors
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llvm-svn: 321897
2018-01-05 20:49:26 +00:00
f9d01a12d1
[Hexagon] Add patterns for truncating HVX vector types
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Only non-bool vectors.
llvm-svn: 321895
2018-01-05 20:48:03 +00:00
9d0c6355a0
[Hexagon] Add patterns for sext_inreg of HVX vector types
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llvm-svn: 321894
2018-01-05 20:46:41 +00:00
66ee123d61
[Hexagon] Add pattern for vsplat to v8i8
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llvm-svn: 321892
2018-01-05 20:43:56 +00:00
b1b2960336
[Hexagon] Replace INSERTRP/EXTRACTRP with INSERT/EXTRACT in HexagonISD
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llvm-svn: 321798
2018-01-04 13:56:04 +00:00
cfe4a3616f
[Hexagon] Fix generation of vector sign extensions
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llvm-svn: 321650
2018-01-02 15:28:49 +00:00
e4ce92cabf
[Hexagon] Allow construction of HVX vector predicates
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Handle BUILD_VECTOR of boolean values.
llvm-svn: 321220
2017-12-20 20:49:43 +00:00
6b589e593d
[Hexagon] Generate HVX code for vector sign-, zero- and any-extends
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Implement any-extend as zero-extend.
llvm-svn: 321004
2017-12-18 18:32:27 +00:00
266d6f03a1
[Hexagon] Handle concat_vectors of all allowed HVX types
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llvm-svn: 320865
2017-12-15 21:23:12 +00:00
29832a6c8b
[Hexagon] Fix operand-swapping PatFrag for atomic stores
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PatFrag now has the atomicity information stored as bit fields. They
need to be copied to the new PatFrag.
llvm-svn: 320855
2017-12-15 20:13:57 +00:00
470760533a
[Hexagon] Generate HVX code for comparisons and selects
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llvm-svn: 320744
2017-12-14 21:28:48 +00:00
708c9f5947
[Hexagon] Remove vectors of i64 from valid HVX types
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HVX does not support operations on 64-bit integers.
llvm-svn: 320722
2017-12-14 18:35:24 +00:00
039d4d9286
[Hexagon] Generate HVX code for basic arithmetic operations
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Handle and, or, xor, add, sub, mul for vectors of i8, i16, and i32.
llvm-svn: 320063
2017-12-07 17:37:28 +00:00
7d37dd8902
[Hexagon] Generate HVX code for vector construction and access
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Support for:
- build vector,
- extract vector element, subvector,
- insert vector element, subvector,
- shuffle.
llvm-svn: 319901
2017-12-06 16:40:37 +00:00
f4dcc42e7b
[Hexagon] Remove HexagonISD::PACKHL
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llvm-svn: 319352
2017-11-29 19:59:29 +00:00
b9f33b32ee
[Hexagon] Add patterns to select A2_combine_ll and its variants
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llvm-svn: 318876
2017-11-22 20:55:41 +00:00
058014fca5
[Hexagon] Prefer L2_loadrub_io over L4_loadrub_rr
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If the offset is an immediate, avoid putting it in a register
to get Rs+Rt<<#0.
llvm-svn: 317275
2017-11-02 21:56:59 +00:00
4dc04e6a70
[Hexagon] Adjust patterns to reflect instruction selection preferences
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llvm-svn: 316804
2017-10-27 22:24:49 +00:00
273678823b
[Hexagon] Add extra pattern for S4_addaddi
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One combination was missing: add(add(x,y),c).
llvm-svn: 316363
2017-10-23 19:07:50 +00:00
64e5d7d3ae
[Hexagon] Reorganize and update instruction patterns
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llvm-svn: 316228
2017-10-20 19:33:12 +00:00
a0f2f7c413
[Hexagon] Add patterns for cmpb/cmph with immediate arguments
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Patch by Sumanth Gundapaneni.
llvm-svn: 315692
2017-10-13 15:43:12 +00:00
557729761c
[Hexagon] Switch to parameterized register classes for HVX
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This removes the duplicate HVX instruction set for the 128-byte mode.
Single instruction set now works for both modes (64- and 128-byte).
llvm-svn: 313362
2017-09-15 15:46:05 +00:00
5eef92eb7f
[Hexagon] Remove custom lowering of loads of v4i16
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The target-independent lowering works fine, except concatenating 32-bit
words. Add a pattern to generate A2_combinew instead of 64-bit asl/or.
llvm-svn: 308186
2017-07-17 15:45:45 +00:00
302a9d41c6
[Hexagon] Replace ISD opcode VPACK with VPACKE/VPACKO, NFC
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This breaks up pack-even and pack-odd into two separate operations.
llvm-svn: 308049
2017-07-14 19:02:32 +00:00
89b2d7c938
[Hexagon] Use VSPLAT instead of COMBINE for vectors of type v2i32, NFC
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This cleans up the vector shift patterns.
llvm-svn: 307935
2017-07-13 18:17:58 +00:00
c86e2ef3f5
[Hexagon] Add support for nontemporal loads and stores on HVX
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Patch by Michael Wu.
Differential Revision: https://reviews.llvm.org/D35104
llvm-svn: 307671
2017-07-11 16:39:33 +00:00
f85dd9f4e5
[Hexagon] Convert typed ISD opcodes to generic ones, NFC
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llvm-svn: 307582
2017-07-10 20:16:44 +00:00
40df124eda
[Hexagon] Remove unused ISD opcodes, NFC
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llvm-svn: 307580
2017-07-10 20:13:44 +00:00
b3a8d20e27
[Hexagon] Generate store-immediate instructions for stack objects
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Store-immediate instructions have a non-extendable offset. Since the
actual offset for a stack object is not known until much later, only
generate these stores when the stack size (at the time of instruction
selection) is small.
llvm-svn: 305305
2017-06-13 17:10:16 +00:00
c83c267b84
[Hexagon] Generate multiply-high instruction in isel
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llvm-svn: 305302
2017-06-13 16:21:57 +00:00
7aca2fd830
[Hexagon] Fixes and updates to the selection patterns
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- Add some missing patterns.
- Use C4_cmplte in branch patterns.
- Fix signedness of immediate operand in M2_accii.
llvm-svn: 305085
2017-06-09 15:26:21 +00:00
7881415510
[Hexagon] Add LLVM header to HexagonPatterns.td
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llvm-svn: 305074
2017-06-09 13:30:58 +00:00
Krzysztof Parzyszek