Commit Graph

10 Commits

Author SHA1 Message Date
Andrea Di Biagio db66efcb6a [llvm-mca] Remove method Instruction::isZeroLatency(). NFCI
llvm-svn: 330807
2018-04-25 09:38:58 +00:00
Andrea Di Biagio 6fd62feff8 [llvm-mca] Do not assume that implicit reads cannot be associated with ReadAdvance entries.
Before, the instruction builder incorrectly assumed that only explicit reads
could have been associated with ReadAdvance entries.
This patch fixes the issue and adds a test to verify it.

llvm-svn: 328972
2018-04-02 13:46:49 +00:00
Andrea Di Biagio 0a837ef6b1 [llvm-mca] Correctly set the ReadAdvance information for register use operands.
The tool was passing the wrong operand index to method
MCSubtargetInfo::getReadAdvanceCycles(). That method requires a "UseIdx", and
not the operand index. This was found when testing X86 code where instructions
had a memory folded operand.

This patch fixes the issue and adds test read-advance-1.s to ensure that
the ReadAfterLd (a ReadAdvance of 3cy) information is correctly used.

llvm-svn: 328790
2018-03-29 14:26:56 +00:00
Andrea Di Biagio 94fafdfded [llvm-mca] run clang-format on all files.
This also addresses Simon's review comment in D44839.

llvm-svn: 328428
2018-03-24 16:05:36 +00:00
Andrea Di Biagio 2dee62bd0a [llvm-mca] Minor refactoring. NFCI
Also, removed a couple of unused methods from class Instruction.

llvm-svn: 328198
2018-03-22 14:14:49 +00:00
Andrea Di Biagio 09ea09e478 [llvm-mca] Simplify (and better standardize) the Instruction interface.
llvm-svn: 328190
2018-03-22 11:39:34 +00:00
Andrea Di Biagio 3562248825 [llvm-mca] Simplify code. NFC
llvm-svn: 328187
2018-03-22 10:19:20 +00:00
Andrea Di Biagio 7b3d162fba [llvm-mca] Use llvm::make_unique in a few places. NFC
Also, clang-format a couple of DEBUG functions.

llvm-svn: 327978
2018-03-20 12:58:34 +00:00
Andrea Di Biagio 4732d43cae [llvm-mca] Move the logic that updates the register files from InstrBuilder to DispatchUnit. NFCI
Before this patch, the register file was always updated at instruction creation
time. That means, new read-after-write dependencies, and new temporary registers
were allocated at instruction creation time.

This patch refactors the code in InstrBuilder, and move all the logic that
updates the register file into the dispatch unit. We only want to update the
register file when instructions are effectively dispatched (not before).

This refactoring also helps removing a bad dependency between the InstrBuilder
and the DispatchUnit.

No functional change intended.

llvm-svn: 327514
2018-03-14 14:57:23 +00:00
Andrea Di Biagio 3a6b092017 [llvm-mca] LLVM Machine Code Analyzer.
llvm-mca is an LLVM based performance analysis tool that can be used to
statically measure the performance of code, and to help triage potential
problems with target scheduling models.

llvm-mca uses information which is already available in LLVM (e.g. scheduling
models) to statically measure the performance of machine code in a specific cpu.
Performance is measured in terms of throughput as well as processor resource
consumption. The tool currently works for processors with an out-of-order
backend, for which there is a scheduling model available in LLVM.

The main goal of this tool is not just to predict the performance of the code
when run on the target, but also help with diagnosing potential performance
issues.

Given an assembly code sequence, llvm-mca estimates the IPC (instructions per
cycle), as well as hardware resources pressure. The analysis and reporting style
were mostly inspired by the IACA tool from Intel.

This patch is related to the RFC on llvm-dev visible at this link:
http://lists.llvm.org/pipermail/llvm-dev/2018-March/121490.html

Differential Revision: https://reviews.llvm.org/D43951

llvm-svn: 326998
2018-03-08 13:05:02 +00:00