Commit Graph

174426 Commits

Author SHA1 Message Date
Craig Topper 11133d2531 [X86] Remove unnecessary code from the top of handleCompareFP in X86FloatingPoint.cpp.
There were checks to ensure some tables were sorted, but those tables aren't used by this function. The same tables are checked in the function that does use them. Maybe this was copy/pasted?

llvm-svn: 352609
2019-01-30 08:04:06 +00:00
Craig Topper 594f76aea2 [X86] Remove a couple places where we unnecessarily pass 0 to the EmitPriority of some FP instruction aliases. NFC
As far as I can tell we already won't emit these aliases due to an operand count check in the tablegen code. Removing these because I couldn't make sense of the inconsistency between fadd and fmul from reading the code.

I checked the AsmMatcher and AsmWriter files before and after this change and there were no differences.

llvm-svn: 352608
2019-01-30 07:33:24 +00:00
Craig Topper 9dfe9b086e [X86] Add FPSW as a Def on some FP instructions that were missing it.
llvm-svn: 352607
2019-01-30 07:08:44 +00:00
Hiroshi Inoue c437f310a5 [NFC] fix trivial typos in comments
llvm-svn: 352602
2019-01-30 05:26:31 +00:00
Matt Arsenault dc6c78596b GlobalISel: Implement fewerElementsVector for select
llvm-svn: 352601
2019-01-30 04:19:31 +00:00
Craig Topper a8710a6e7e [IR] Use CallBase to simplify some code
Summary:
This patch does the following to simplify the asm-goto patch

-Move isInlineAsm from CallInst to CallBase to share with CallBrInst in the asm-goto patch.
-Forward CallSite's data_operands_begin()/data_operands_end() to CallBase's implementation.
-Forward CallSite's getOperandBundlesAsDefs to CallBase.

Reviewers: chandlerc

Reviewed By: chandlerc

Subscribers: nickdesaulniers, llvm-commits

Differential Revision: https://reviews.llvm.org/D57415

llvm-svn: 352600
2019-01-30 03:43:41 +00:00
Matt Arsenault f6cab16258 AMDGPU/GlobalISel: Fix clamping shifts with 16-bit insts
llvm-svn: 352599
2019-01-30 03:36:25 +00:00
Heejin Ahn d6f487863d [WebAssembly] Exception handling: Switch to the new proposal
Summary:
This switches the EH implementation to the new proposal:
https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md
(The previous proposal was
 https://github.com/WebAssembly/exception-handling/blob/master/proposals/old/Exceptions.md)

- Instruction changes
  - Now we have one single `catch` instruction that returns a except_ref
    value
  - `throw` now can take variable number of operations
  - `rethrow` does not have 'depth' argument anymore
  - `br_on_exn` queries an except_ref to see if it matches the tag and
    branches to the given label if true.
  - `extract_exception` is a pseudo instruction that simulates popping
    values from wasm stack. This is to make `br_on_exn`, a very special
    instruction, work: `br_on_exn` puts values onto the stack only if it
    is taken, and the # of values can vay depending on the tag.

- Now there's only one `catch` per `try`, this patch removes all special
  handling for terminate pad with a call to `__clang_call_terminate`.
  Before it was the only case there are two catch clauses (a normal
  `catch` and `catch_all` per `try`).

- Make `rethrow` act as a terminator like `throw`. This splits BB after
  `rethrow` in WasmEHPrepare, and deletes an unnecessary `unreachable`
  after `rethrow` in LateEHPrepare.

- Now we stop at all catchpads (because we add wasm `catch` instruction
  that catches all exceptions), this creates new
  `findWasmUnwindDestinations` function in SelectionDAGBuilder.

- Now we use `br_on_exn` instrution to figure out if an except_ref
  matches the current tag or not, LateEHPrepare generates this sequence
  for catch pads:
```
  catch
  block i32
  br_on_exn $__cpp_exception
  end_block
  extract_exception
```

- Branch analysis for `br_on_exn` in WebAssemblyInstrInfo

- Other various misc. changes to switch to the new proposal.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D57134

llvm-svn: 352598
2019-01-30 03:21:57 +00:00
Matt Arsenault 6d8e1b456a GlobalISel: Use appropriate extension for legalizing select conditions
llvm-svn: 352597
2019-01-30 02:57:43 +00:00
Zi Xuan Wu fec749ff5d [PowerPC] [NFC] Create a helper function to copy register to particular register class at PPCFastISel
Make copy register code as common function as following.

unsigned copyRegToRegClass(const TargetRegisterClass *ToRC, unsigned SrcReg, unsigned Flag = 0, unsigned SubReg = 0);

Differential Revision: https://reviews.llvm.org/D57368

llvm-svn: 352596
2019-01-30 02:56:22 +00:00
Matt Arsenault 045bc9a4a6 GlobalISel: Support narrowScalar for uneven loads
llvm-svn: 352594
2019-01-30 02:35:38 +00:00
Thomas Lively 079816efb7 [WebAssembly] Optimize BUILD_VECTOR lowering for size
Summary:
Implements custom lowering logic that finds the optimal value for the
initial splat of the vector and either uses it or uses v128.const if
it is available and if it would produce smaller code. This logic
replaces large TableGen ISEL patterns that would lower all non-splat
BUILD_VECTORs into a splat followed by a fixed number of replace_lane
instructions. This CL fixes PR39685.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D56633

llvm-svn: 352592
2019-01-30 02:23:29 +00:00
Matt Arsenault ccefbbd0f0 GlobalISel: Handle some odd splits in fewerElementsVector
Also add some quick hacks to AMDGPU legality for the tests.

llvm-svn: 352591
2019-01-30 02:22:13 +00:00
Sam Clegg fc37198df1 Add enum values to CodeGenOpt::Level
The absolute values of this enum are important at least in that
they get printed by SelectionDAGISel. e.g:
  `Before: -O2 ; After: -O0`

Differential Revision: https://reviews.llvm.org/D57430

llvm-svn: 352587
2019-01-30 02:08:34 +00:00
Matt Arsenault 92c5001136 GlobalISel: Handle more cases for widenScalar for G_STORE
llvm-svn: 352585
2019-01-30 02:04:31 +00:00
Chen Zheng ca26039cc7 [PowerPC] more opportunity for converting reg+reg to reg+imm
Differential Revision: https://reviews.llvm.org/D57314

llvm-svn: 352583
2019-01-30 01:57:01 +00:00
Matt Arsenault 4a4d7a7be8 Add 8.0 release bug to merge request script
llvm-svn: 352579
2019-01-30 01:10:47 +00:00
Matt Arsenault ccb810fb54 GlobalISel: Verify memory size for load/store
llvm-svn: 352578
2019-01-30 01:10:42 +00:00
George Burgess IV 179f6baa45 Remove a redundant space from an error message; NFC
llvm-svn: 352576
2019-01-30 00:28:56 +00:00
Sam Clegg c7d2e5f154 [WebAssembly] Add missing SymbolRef update from rL352551
This change broke some MC tests which are now fixed.

Differential Revision: https://reviews.llvm.org/D57424

llvm-svn: 352573
2019-01-30 00:15:48 +00:00
Thomas Lively 74c12ceacb [WebAssembly] Lower SCALAR_TO_VECTOR to splats
Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish

Differential Revision: https://reviews.llvm.org/D57269

llvm-svn: 352568
2019-01-29 23:44:48 +00:00
Matt Arsenault 3de9a96174 GlobalISel: Fix unused variable warning in release builds
llvm-svn: 352565
2019-01-29 23:38:42 +00:00
Craig Topper 0b5e6b11c3 [IR] Use CallBase to reduce code duplication. NFC
Noticed in the asm-goto patch. Callbr needs to go here too. One cast and call is better than 3.

Differential Revision: https://reviews.llvm.org/D57295

llvm-svn: 352563
2019-01-29 23:31:54 +00:00
Matt Arsenault d45b03bb81 GlobalISel: Verify pointer casts
Not sure if the old AArch64 tests should be just
deleted or not.

llvm-svn: 352562
2019-01-29 23:29:00 +00:00
Matt Arsenault d8d193d5e2 GlobalISel: Partially implement widenScalar for MERGE_VALUES
llvm-svn: 352560
2019-01-29 23:17:35 +00:00
Alina Sbirlea f9027e554a Check bool attribute value in getOptionalBoolLoopAttribute.
Summary:
Check the bool value of the attribute in getOptionalBoolLoopAttribute
not just its existance.
Eliminates the warning noise generated when vectorization is explicitly disabled.

Reviewers: Meinersbur, hfinkel, dmgreen

Subscribers: jlebar, sanjoy, llvm-commits

Differential Revision: https://reviews.llvm.org/D57260

llvm-svn: 352555
2019-01-29 22:33:20 +00:00
Sam Clegg 2a193e0d12 [WebAssembly] Ensure BasicSymbolRef.getRawDataRefImpl().p is non-null
Store a non-zero value to ref.d.a and use ref.d.b to store the symbol
index.  This means that ref.p is never null, which was confusing
llvm-nm.

Fixes PR40497

Differential Revision: https://reviews.llvm.org/D57373

llvm-svn: 352551
2019-01-29 22:22:32 +00:00
Shoaib Meenai ed2ebf82e7 [docs] Prevent O0 optnone for opt input
If we just compile with -O0, clang will add optnone attributes
everywhere, so opt won't actually be able to perform any passes.
Instruct clang to not emit the optnone so opt can do its thing.

Differential Revision: https://reviews.llvm.org/D56950

llvm-svn: 352550
2019-01-29 22:17:51 +00:00
Amara Emerson 102c9ed768 [AArch64][GlobalISel] Unmerge into scalars from a vector should use FPR bank.
This currently shows up as a selection fallback since the dest regs were given
GPR banks but the source was a vector FPR reg.

Differential Revision: https://reviews.llvm.org/D57408

llvm-svn: 352545
2019-01-29 21:19:33 +00:00
Paul Robinson 4ca29477d9 [DWARF] Emit reasonable debug info for empty .s files.
llvm-svn: 352541
2019-01-29 20:53:51 +00:00
Sanjay Patel 18db56209c [InstCombine] canonicalize cmp/select form of uadd saturate with constant
I'm circling back around to a loose end from D51929.

The backend (either CGP or DAG) doesn't recognize this pattern, so we end up with different asm for these IR variants.

Regardless of any future changes to canonicalize to saturation/overflow intrinsics, we want to get raw IR variations 
into the minimal number of raw IR forms. If/when we can canonicalize to intrinsics, that will make that step easier.

  Pre: C2 == ~C1
  %a = add i32 %x, C1
  %c = icmp ugt i32 %x, C2
  %r = select i1 %c, i32 -1, i32 %a
  =>
  %a = add i32 %x, C1
  %c2 = icmp ult i32 %x, C2
  %r = select i1 %c2, i32 %a, i32 -1

  https://rise4fun.com/Alive/pkH

Differential Revision: https://reviews.llvm.org/D57352

llvm-svn: 352536
2019-01-29 20:02:45 +00:00
Sanjay Patel a61d586f74 [DAGCombiner] fold extract_subvector of extract_subvector
This is the sibling fold for insert-of-insert that was added with D56604.

Now that we have x86 shuffle narrowing (D57156), this change shows improvements for 
lots of AVX512 reduction code (not sure that we would ever expect extract-of-extract otherwise).

There's a small regression in some of the partial-permute tests (extracting followed by splat).
That is tracked by PR40500:
https://bugs.llvm.org/show_bug.cgi?id=40500

Differential Revision: https://reviews.llvm.org/D57336

llvm-svn: 352528
2019-01-29 19:13:39 +00:00
Michael J. Spencer 2a5a0ad1e4 [VFS] Fix warning and use better check.
llvm-svn: 352527
2019-01-29 19:07:15 +00:00
Matt Arsenault 18619afe1d GlobalISel: Fix narrowScalar for load/store with different mem size
This was ignoring the memory size, and producing multiple loads/stores
if the operand size was different from the memory size.

I assume this is the intent of not having an explicit G_ANYEXTLOAD
(although I think that would probably be better).

llvm-svn: 352523
2019-01-29 18:13:02 +00:00
Sanjay Patel cd6b240303 [x86] add tests for vector bool math; NFC
llvm-svn: 352520
2019-01-29 17:00:47 +00:00
Sanjay Patel 22dd34b0ec [AArch64] add tests for vector bool math; NFC
llvm-svn: 352519
2019-01-29 17:00:07 +00:00
Andrea Di Biagio 815cdbff29 [X86][Btver2] Improved latency/throughput model for scalar int-to-float conversions.
Account for bypass delays when computing the latency of scalar int-to-float
conversions.
On Jaguar we need to account for an extra 6cy latency (see AMD fam16h SOG).
This patch also fixes the number of micropcodes for the register-memory variants
of scalar int-to-float conversions.

Differential Revision: https://reviews.llvm.org/D57148

llvm-svn: 352518
2019-01-29 16:47:27 +00:00
Sanjay Patel 2e87df9112 [InstCombine] regenerate test checks; NFC
llvm-svn: 352517
2019-01-29 16:44:05 +00:00
Sanjay Patel f044d1884d [InstCombine] add tests for ext-of-bool + add/sub; NFC
We should choose one of these as canonical:

  %z = zext i1 %cmp to i32
  %r = sub i32 %x, %z
  =>
  %s = sext i1 %cmp to i32
  %r = add i32 %x, %s

The test comments assume that the zext form is better,
but we can adjust that if we decide to go the other way.

llvm-svn: 352515
2019-01-29 16:39:23 +00:00
James Y Knight 5d71fc5d7b Adjust documentation for git migration.
This fixes most references to the paths:
 llvm.org/svn/
 llvm.org/git/
 llvm.org/viewvc/
 github.com/llvm-mirror/
 github.com/llvm-project/
 reviews.llvm.org/diffusion/

to instead point to https://github.com/llvm/llvm-project.

This is *not* a trivial substitution, because additionally, all the
checkout instructions had to be migrated to instruct users on how to
use the monorepo layout, setting LLVM_ENABLE_PROJECTS instead of
checking out various projects into various subdirectories.

I've attempted to not change any scripts here, only documentation. The
scripts will have to be addressed separately.

Additionally, I've deleted one document which appeared to be outdated
and unneeded:
  lldb/docs/building-with-debug-llvm.txt

Differential Revision: https://reviews.llvm.org/D57330

llvm-svn: 352514
2019-01-29 16:37:27 +00:00
Nirav Dave 1527c0e727 [SelectionDAGBuilder] Remove redundant variable. NFCI.
llvm-svn: 352506
2019-01-29 15:14:07 +00:00
Jordan Rupprecht c892741e74 [llvm-objcopy] Implement --set-section-flags.
Summary:
--set-section-flags is used to change the section flags (e.g. SHF_ALLOC) for given sections. The flags allowed are the same from the existing --rename-section=.old=.new[,flags] feature.

Additionally, make sure that --set-section-flag cannot be used with --rename-section (either the source or destination), since --rename-section accepts flags. This avoids ambiguity for something like "--rename-section=.foo=.bar,alloc --set-section-flag=.bar,code".

Reviewers: jhenderson, jakehehrlich, alexshap, espindola

Reviewed By: jhenderson, jakehehrlich

Subscribers: llvm-commits, emaste, arichardson

Differential Revision: https://reviews.llvm.org/D57198

llvm-svn: 352505
2019-01-29 15:05:38 +00:00
Ayonam Ray a1f6973ade Reversing the checkin for version 352484 as tests are failing.
llvm-svn: 352504
2019-01-29 15:00:50 +00:00
Nico Weber a963821052 gn build: Merge r352444, r352431, r352430
llvm-svn: 352502
2019-01-29 14:39:54 +00:00
Neil Henning 0799352026 [AMDGPU] Fix a weird WWM intrinsic issue.
I found a really strange WWM issue through a very convoluted shader that
essentially boils down to a bug in SIInstrInfo where canReadVGPR did not
correctly identify that WWM is like a copy and can have a VGPR as its
source.

Differential Revision: https://reviews.llvm.org/D56002

llvm-svn: 352500
2019-01-29 14:28:17 +00:00
Hans Wennborg 81675c8f3b Revert r351833 and r352250.
They were breaking the Windows build when using MSBuild, see the
discussion on D56781.

r351833: "Use response file when generating LLVM-C.dll"

> Use response file when generating LLVM-C.dll
>
> As discovered in D56774 the command line gets to long, so use a response file to give the script the libs. This change has been tested and is confirmed working for me.
>
> Commited on behalf of Jakob Bornecrantz
>
> Differential Revision: https://reviews.llvm.org/D56781

r352250: "Build LLVM-C.dll by default on windows and enable in release package"

>  Build LLVM-C.dll by default on windows and enable in release package
>
>  With the fixes to the building of LLVM-C.dll in D56781 this should now
>  be safe to land. This will greatly simplify dealing with LLVM for people
>  that just want to use the C API on windows. This is a follow up from
>  D35077.
>
>  Patch by Jakob Bornecrantz!
>
>  Differential revision: https://reviews.llvm.org/D56774

llvm-svn: 352492
2019-01-29 13:43:22 +00:00
Ayonam Ray 4272af9b3e [CodeGen] Omit range checks from jump tables when lowering switches with unreachable default
During the lowering of a switch that would result in the generation of a 
jump table, a range check is performed before indexing into the jump 
table, for the switch value being outside the jump table range and a 
conditional branch is inserted to jump to the default block. In case the 
default block is unreachable, this conditional jump can be omitted. This 
patch implements omitting this conditional branch for unreachable 
defaults.

Review ID: D52002
Reviewers: Hans Wennborg, Eli Freidman, Roman Lebedev

llvm-svn: 352484
2019-01-29 12:01:32 +00:00
Simon Pilgrim 4293ad8ab2 [X86] Add PR40483 test case
llvm-svn: 352480
2019-01-29 10:58:42 +00:00
Dan Gohman 4684f824d4 [WebAssembly] Re-enable main-function signature rewriting
Re-enable the code to rewrite main-function signatures into
"int main(int argc, char *argv[])", but limited to only handling
the case of "int main(void)", so that it doesn't silently strip
an argument in the "int main(int argc, char *argv[], char *envp[])"
case.

This allows main to be called by C startup code, since WebAssembly
requires caller and callee signatures to match, so it can't rely
on passing main a different number of arguments than it expects.

Differential Revision: https://reviews.llvm.org/D57323

llvm-svn: 352479
2019-01-29 10:53:42 +00:00
James Henderson 6f39f6ace7 [llvm-symbolizer][doc] Tweak wording of --adjust-vma switch description
The address isn't dynamically relocated. The object is.

llvm-svn: 352477
2019-01-29 10:43:48 +00:00