eaf2da14bf
[X86][AVX512] add masked version for RSQRT14 & RCP14 Scalar FP
...
Differential Revision: http://reviews.llvm.org/D12524
llvm-svn: 248147
2015-09-21 10:23:53 +00:00
b7e1f9d680
AVX512: Implemented encoding and intrinsics for vcmpss/sd.
...
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D12593
llvm-svn: 248121
2015-09-20 15:15:10 +00:00
2744d21fb8
[X86][AVX512] extend support in Scalar conversion
...
add scalar FP to Int conversion with truncation intrinsics
add scalar conversion FP32 from/to FP64 intrinsics
add rounding mode and SAE mode encoding for these intrinsics
Differential Revision: http://reviews.llvm.org/D12665
llvm-svn: 248117
2015-09-20 14:31:19 +00:00
4c4cd789c9
AVX512: vsqrtss/sd encoding and intrinsics implementation.
...
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D12102
llvm-svn: 248116
2015-09-20 09:13:41 +00:00
572bbceecc
[X86][AVX512DQ] Add fpclass instruction
...
Differential Revision: http://reviews.llvm.org/D12931
llvm-svn: 248115
2015-09-20 08:46:07 +00:00
1d55f20bee
AVX512: Implemented intrinsics for vshuff32x4, vshuff64x2, vshufi64x2, vshufi32x4
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Added tests for intrinsics.
Differential Revision: http://reviews.llvm.org/D12525
llvm-svn: 248113
2015-09-20 07:18:53 +00:00
0ede3cbb5c
AVX512: Implement instructions encoding, lowering and intrinsics
...
vinserti64x4, vinserti64x2, vinserti32x8, vinserti32x4, vinsertf64x4, vinsertf64x2, vinsertf32x8, vinsertf32x4
Added tests for encoding, lowering and intrinsics.
Differential Revision: http://reviews.llvm.org/D11893
llvm-svn: 248111
2015-09-20 06:52:42 +00:00
0dcd8bcf24
AVX512: Implemented encoding and intrinsics for vplzcntq, vplzcntd, vpconflictq, vpconflictd
...
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11931
llvm-svn: 246750
2015-09-03 09:05:31 +00:00
d2c3599c5f
[X86][AVX512VLBW] add support in byte shift and SAD
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add byte shift left/right
add SAD - compute sum of absolute differences
Differential Revision: http://reviews.llvm.org/D12479
llvm-svn: 246654
2015-09-02 14:21:54 +00:00
1e58e8adf6
AVX512: Implemented encoding and intrinsics for VGETMANTPD/S , VGETMANTSD/S instructions
...
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11593
llvm-svn: 246642
2015-09-02 11:18:55 +00:00
a6297c701e
AVX512: Implemented encoding and intrinsics for vshufps/d.
...
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11709
llvm-svn: 246640
2015-09-02 10:50:58 +00:00
f6f1bb6ddc
AVX512: Implemented intrinsics for valign.
...
Differential Revision: http://reviews.llvm.org/D12526
llvm-svn: 246551
2015-09-01 15:27:18 +00:00
f3ded811b2
AVX512: Implemented encoding and intrinsics for vdbpsadbw
...
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D12491
llvm-svn: 246436
2015-08-31 13:09:30 +00:00
2ae0fe3ac3
AVX512: Implemented encoding and intrinsics for vpalignr
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Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D12270
llvm-svn: 246428
2015-08-31 11:14:02 +00:00
8352a0ddf2
AVX512: Implemented encoding and intrinsics for VGETEXPSS/D instructions
...
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11528
llvm-svn: 243390
2015-07-28 06:53:28 +00:00
f2460112ad
Implemented encoding and intrinsics of the following instructions
...
vunpckhps/pd, vunpcklps/pd,
vpunpcklbw, vpunpckhbw, vpunpcklwd, vpunpckhwd, vpunpckldq, vpunpckhdq, vpunpcklqdq, vpunpckhqdq
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11509
llvm-svn: 243246
2015-07-26 14:41:44 +00:00
074a64e72c
AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer Truncate with/without saturation
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Added tests for DAG lowering ,encoding and intrinsic
Differential Revision: http://reviews.llvm.org/D11218
llvm-svn: 243122
2015-07-24 17:24:15 +00:00
fe414353db
Revert r242990: "AVX-512: Implemented encoding , DAG lowering and ..."
...
This commit broke the build. Numerous build bots broken, and it was
blocking my progress so reverting.
It should be trivial to reproduce -- enable the BPF backend and it
should fail when running llvm-tblgen.
llvm-svn: 242992
2015-07-23 08:03:44 +00:00
da1b2ea955
AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer Truncate with/without saturation
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Added tests for DAG lowering ,encoding and intrinsic
Differential Revision: http://reviews.llvm.org/D11218
llvm-svn: 242990
2015-07-23 07:39:21 +00:00
a5b2e5e2a7
[X86][AVX512] add reduce/range/scalef/rndScale
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include encoding and intrinsics
Differential Revision: http://reviews.llvm.org/D11222
llvm-svn: 242896
2015-07-22 12:00:43 +00:00
a26f10ce18
AVX-512: Added intrinsics for VCVT* instructions.
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All SKX forms. All VCVT instructions for float/double/int/long types.
Differential Revision: http://reviews.llvm.org/D11343
llvm-svn: 242877
2015-07-22 08:56:00 +00:00
f7fd547e27
AVX512 : Implemented VPMADDUBSW and VPMADDWD instruction ,
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Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11351
llvm-svn: 242761
2015-07-21 07:11:28 +00:00
d85cae3d52
[X86][SSE4A] Shuffle lowering using SSE4A EXTRQ/INSERTQ instructions
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This patch adds support for v8i16 and v16i8 shuffle lowering using the immediate versions of the SSE4A EXTRQ and INSERTQ instructions. Although rather limited (they can only act on the lower 64-bits of the source vectors, leave the upper 64-bits of the result vector undefined and don't have VEX encoded variants), the instructions are still useful for the zero extension of any lane (EXTRQ) or inserting a lane into another vector (INSERTQ). Testing demonstrated that it wasn't typically worth it to use these instructions for v2i64 or v4i32 vector shuffles although they are capable of it.
As well as adding specific pattern matching for the shuffles, the patch uses EXTRQ for zero extension cases where SSE41 isn't available and its more efficient than the SSE2 'unpack' default approach. It also adds shuffle decode support for the EXTRQ / INSERTQ cases when the instructions are handling full byte-sized extractions / insertions.
From this foundation, future patches will be able to make use of the instructions for situations that use their ability to extract/insert at the bit level.
Differential Revision: http://reviews.llvm.org/D10146
llvm-svn: 241508
2015-07-06 20:46:41 +00:00
8b756596fc
[X86][SSE] Use the general SMAX/SMIN/UMAX/UMIN opcodes and remove the X86 implementation
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With the completion of D9746 there is now a common implementation of integer signed/unsigned min/max nodes, removing the need for the equivalent X86 specific implementations.
This patch removes the old X86ISD nodes, legalizes the relevant SSE2/SSE41/AVX2/AVX512 instructions for the ISD versions and converts the small amount of existing X86 code.
Differential Revision: http://reviews.llvm.org/D10947
llvm-svn: 241506
2015-07-06 20:30:47 +00:00
c6f3c82ffc
[X86][AVX512] Multiply Packed Unsigned Integers with Round and Scale
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pmulhrsw
review:
http://reviews.llvm.org/D10948
llvm-svn: 241443
2015-07-06 14:03:40 +00:00
73f26f8ffc
[x86][AVX512] add Multiply High Op
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include encoding and intrinsics tests.
review
http://reviews.llvm.org/D10896
llvm-svn: 241406
2015-07-05 12:23:20 +00:00
30bc4ca313
AVX-512: all forms of SCATTER instruction on SKX,
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encoding, intrinsics and tests.
llvm-svn: 240936
2015-06-29 12:14:24 +00:00
a7a8e9a018
AVX-512: Implemented missing encoding and intrinsics for FMA instructions
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Added tests for DAG lowering ,encoding and intrinsics
Differential Revision: http://reviews.llvm.org/D10796
llvm-svn: 240926
2015-06-29 09:10:00 +00:00
7bffb6954d
Whitespace.
...
llvm-svn: 240924
2015-06-29 04:50:09 +00:00
7ec4b7a8bb
[x86][AVX512]
...
Add vscalef support
include encoding and intrinsics
review:
http://reviews.llvm.org/D10730
llvm-svn: 240906
2015-06-28 14:30:39 +00:00
6a1a357f1f
AVX-512: Added all SKX forms of GATHER instructions.
...
Added intrinsics.
Added encoding and tests.
llvm-svn: 240905
2015-06-28 10:53:29 +00:00
5e2f8c4231
AVX-512: Added all forms of VPABS instruction
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Added all intrinsics, tests for encoding, tests for intrinsics.
llvm-svn: 240386
2015-06-23 08:19:46 +00:00
55a997437c
AVX-512: added VPSHUFB instruction - all SKX forms
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Added intrinsics and encoding tests.
llvm-svn: 240277
2015-06-22 13:00:42 +00:00
e77566112c
AVX-512: Added intrinsics for VPERMT2W/D/Q/PS/PD and
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VPERMI2W/D/Q/PS/PD instructions.
Added tests.
llvm-svn: 240256
2015-06-22 06:45:48 +00:00
81f03c30a5
[AVX512]
...
add instructions: VPAVGB and VPAVGW
review
http://reviews.llvm.org/D10504
llvm-svn: 240012
2015-06-18 12:30:53 +00:00
dfcc3d31a7
AVX-512: cvtusi2ss/d intrinsics.
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Change builtin function name and signature ( add third parameter - rounding mode ).
Added tests for intrinsics.
Differential Revision: http://reviews.llvm.org/D10473
llvm-svn: 239888
2015-06-17 07:23:57 +00:00
02d126cb9d
[AVX512] add integer min/max intrinsics support.
...
review:
http://reviews.llvm.org/D10439
llvm-svn: 239806
2015-06-16 08:39:27 +00:00
abe4a79b75
AVX-512: Implemented cvtsi2ss/d cvtusi2ss/d instructions with round control for KNL.
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Added intrinsics for cvtsi2ss/d instructions.
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D10430
llvm-svn: 239694
2015-06-14 12:44:55 +00:00
00d9f8457b
AVX-512: Implemented 256/128bit VALIGND/Q instructions for SKX and KNL
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Implemented DAG lowering for all these forms.
Added tests for DAG lowering and encoding.
Differential Revision: http://reviews.llvm.org/D10310
llvm-svn: 239300
2015-06-08 14:03:17 +00:00
402ebb34af
re-apply 238809
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AVX-512: Implemented GETEXP instruction for KNL and SKX
Added rounding mode modifier for SQRTPS/PD
Added tests for encoding and intrinsics.
CR:
http://reviews.llvm.org/D9991
llvm-svn: 238923
2015-06-03 13:41:48 +00:00
8d897dd05f
revert 238809
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llvm-svn: 238810
2015-06-02 07:45:19 +00:00
17de10f37e
AVX-512: Implemented GETEXP instruction for KNL and SKX
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Added rounding mode modifier for SQRTPS/PD
Added tests for encoding and intrinsics.
llvm-svn: 238809
2015-06-02 07:18:14 +00:00
b8573cba02
AVX-512: Added intrinsics for ADDSS/D, MULSS/D, SUBSS/D, DIVSS/D
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instructions. These intrinsics are comming with rounding mode.
Added intrinsics for MAXSS/D, MINSS/D - with and without sae.
By Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 237560
2015-05-18 07:24:19 +00:00
0d7e9364d1
AVX-512: Added SKX instructions and intrinsics:
...
{add/sub/mul/div/} x {ps/pd} x {128/256} 2. max/min with sae
By Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 236971
2015-05-11 06:05:05 +00:00
29792e9a80
AVX-512: Added all forms of FP compare instructions for KNL and SKX.
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Added intrinsics for the instructions. CC parameter of the intrinsics was changed from i8 to i32 according to the spec.
By Igor Breger (igor.breger@intel.com )
llvm-svn: 236714
2015-05-07 11:24:42 +00:00
52266388f8
AVX-512: added integer "add" and "sub" instructions with saturation for SKX
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with intrinsics and tests
by Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 236418
2015-05-04 12:35:55 +00:00
2557a22be7
AVX-512: Added VPACK* instructions forms for KNL and SKX
...
and their intrinsics
by Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 236414
2015-05-04 09:14:02 +00:00
f75ee4dc07
[x86] remove RCPPS and RSQRTPS intrinsic instruction definitions
...
We don't need codegen-only intrinsic instructions for the vector forms of these instructions.
This makes the reciprocal estimate instruction lowering identical to how we handle normal
square roots: (V)SQRTPS / (V)SQRTPD.
No existing regression tests fail with this patch.
Differential Revision: http://reviews.llvm.org/D9301
llvm-svn: 236013
2015-04-28 18:48:45 +00:00
ae51853924
AVX-512: Added "pandn" intrinsics set
...
by Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 235971
2015-04-28 08:12:42 +00:00
8fd573e87f
fix 80-cols; NFC
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llvm-svn: 235902
2015-04-27 17:45:44 +00:00
912315811e
fix typos; NFC
...
llvm-svn: 235896
2015-04-27 17:03:31 +00:00
50b88ddb87
AVX-512: Added logical and arithmetic instructions for SKX
...
by Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 235375
2015-04-21 10:27:40 +00:00
1eeece1285
AVX-512: intrinsics for VPADD, VPMULDQ and VPSUB
...
by Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 233906
2015-04-02 10:51:40 +00:00
98de9d6360
AVX-512: added intrinsics for VPAND, VPOR and VPXOR
...
by Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 233525
2015-03-30 08:30:34 +00:00
f59b2d034c
[X86] Fix a regression introduced by r223641.
...
The permps and permd instructions have their operands swapped compared to the
intrinsic definition. Therefore, they do not fall into the INTR_TYPE_2OP
category.
I did not create a new category for those two, as they are the only one AFAICT
in that case.
<rdar://problem/20108262>
llvm-svn: 232085
2015-03-12 19:34:12 +00:00
52e81bc499
AVX-512: recommitted 229837 + bugfix + test
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llvm-svn: 230223
2015-02-23 15:12:31 +00:00
0d94fa98e5
Revert "AVX-512: Full implementation for VRNDSCALESS/SD instructions and intrinsics."
...
The instructions were being generated on architectures that don't support avx512.
This reverts commit r229837.
llvm-svn: 229942
2015-02-20 00:45:28 +00:00
69e8b45b13
AVX-512: Full implementation for VRNDSCALESS/SD instructions and intrinsics.
...
llvm-svn: 229837
2015-02-19 10:48:04 +00:00
714f23bcdb
AVX-512: Added support for FP instructions with embedded rounding mode.
...
By Asaf Badouh <asaf.badouh@intel.com>
llvm-svn: 229645
2015-02-18 07:59:20 +00:00
7b0dd39db6
AVX-512: Added FMA intrinsics with rounding mode
...
By Asaf Badouh and Elena Demikhovsky
Added special nodes for rounding: FMADD_RND, FMSUB_RND..
It will prevent merge between nodes with rounding and other standard nodes.
llvm-svn: 227303
2015-01-28 10:21:27 +00:00
fcea06acb5
AVX-512: Added FMA instructions, intrinsics an tests for KNL and SKX targets
...
by Asaf Badouh
http://reviews.llvm.org/D6456
llvm-svn: 224764
2014-12-23 10:30:39 +00:00
949b0d46bf
AVX-512: Added all forms of BLENDM instructions,
...
intrinsics, encoding tests for AVX-512F and skx instructions.
llvm-svn: 224707
2014-12-22 13:52:48 +00:00
72860c341e
AVX-512: Added EXPAND instructions and intrinsics.
...
llvm-svn: 224241
2014-12-15 10:03:52 +00:00
5fb084e798
[AVX512] Add support for 512b variable bit shift intrinsics.
...
llvm-svn: 224028
2014-12-11 17:13:05 +00:00
908dbf48c8
AVX-512: Added all forms of COMPRESS instruction
...
+ intrinsics + tests
llvm-svn: 224019
2014-12-11 15:02:24 +00:00
68e04b8613
X86 intrinsics moved form X86ISelLowering.cpp to X86IntrinsicsInfo.h
...
X86ISelLowering.cpp has a long switch for intrinsics. I moved a part of
this long switch to the new intrinsics table in X86IntrinsicsInfo.h.
No functional changes, just code and compile time optimization.
llvm-svn: 223641
2014-12-08 09:03:08 +00:00
8b54286d1c
[X86] Refactor PMOV[SZ]Xrm to add missing AVX2 patterns.
...
Most patterns will go away once the extload legalization changes land.
Differential Revision: http://reviews.llvm.org/D6125
llvm-svn: 223567
2014-12-06 01:31:07 +00:00
5bf9578ce4
[X86] Clean up whitespace as well as minor coding style
...
llvm-svn: 223339
2014-12-04 05:20:33 +00:00
905a5a606f
AVX-512: Scalar ERI intrinsics
...
including SAE mode and memory operand.
Added AVX512_maskable_scalar template, that should cover all scalar instructions in the future.
The main difference between AVX512_maskable_scalar<> and AVX512_maskable<> is using X86select instead of vselect.
I need it, because I can't create vselect node for MVT::i1 mask for scalar instruction.
http://reviews.llvm.org/D6378
llvm-svn: 222820
2014-11-26 10:46:49 +00:00
9b7c15a364
[AVX512] Add 512b integer shift by variable intrinsics and patterns.
...
llvm-svn: 222786
2014-11-25 20:41:51 +00:00
73a6bca32b
[AVX512] Add integer shift by immediate intrinsics.
...
llvm-svn: 221811
2014-11-12 19:58:54 +00:00
be8808dc3f
AVX-512: Intrinsics for ERI
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3 instructions: vrcp28, vrsqrt28, vexp2, only vector forms.
Intrinsics include SAE (Suppres All Exceptions) parameter.
http://reviews.llvm.org/D6214
llvm-svn: 221774
2014-11-12 07:31:03 +00:00
b51bb22611
[AVX512] Added intrinsics for 128-, 256- and 512-bit versions of VPCMP/VPCMPU{BWDQ}
...
Added CMP_MASK_CC intrinsic type.
Added tests for intrinsics.
Patch by Sergey Lisitsyn <sergey.lisitsyn@intel.com>
llvm-svn: 219316
2014-10-08 15:49:26 +00:00
28a7df0b5f
[AVX512] Added intrinsics for 128-, 256- and 512-bit versions of VCMPGT{BWDQ}.
...
Patch by Sergey Lisitsyn <sergey.lisitsyn@intel.com>
llvm-svn: 218670
2014-09-30 12:15:52 +00:00
5aa4445bde
[AVX512] Added intrinsics for 128- and 256-bit versions of VCMPEQ{BWDQ}
...
Fixed lowering of this intrinsics in case when mask is v2i1 and v4i1.
Now cmp intrinsics lower in the following way:
(i8 (int_x86_avx512_mask_pcmpeq_q_128
(v2i64 %a), (v2i64 %b), (i8 %mask))) ->
(i8 (bitcast
(v8i1 (insert_subvector undef,
(v2i1 (and (PCMPEQM %a, %b),
(extract_subvector
(v8i1 (bitcast %mask)), 0))), 0))))
llvm-svn: 218669
2014-09-30 11:41:54 +00:00
b25e562d14
[AVX512] Added intrinsics for VPCMPEQB and VPCMPEQW.
...
Added new operand type for intrinsics (IIT_V64)
llvm-svn: 218668
2014-09-30 11:32:22 +00:00
a27c8e0fd9
[AVX512] Enabled intrinsics for VPCMPEQD and VPCMPEQQ.
...
Added CMP_MASK intrinsic type
llvm-svn: 218667
2014-09-30 11:19:50 +00:00
0f54a0b02a
Fixed compilation problem on Windows (initialization of non-aggregate type).
...
After commit 217131.
llvm-svn: 217134
2014-09-04 07:20:39 +00:00
228ab3d7b3
X86 Intrinsics table - changed to a static table sorted by intrinsic id.
...
Used binary search over the tables.
llvm-svn: 217131
2014-09-04 06:34:34 +00:00
22e735d725
X86 intrinsics table - simplifies intrinsics lowering.
...
The tables are initialized when X86TargetLowering object is created.
llvm-svn: 216345
2014-08-24 09:19:56 +00:00
c0b420fdf5
Reverted last commit
...
llvm-svn: 215827
2014-08-17 09:36:07 +00:00
2bb991a0c5
Added a table for intrinsics on X86.
...
It should remove dosens of lines in handling instrinsics (in a huge switch) and give an easy way to add new intrinsics.
I did not completed to move al intrnsics to the table, I'll do this in the upcomming commits.
llvm-svn: 215826
2014-08-17 09:00:20 +00:00
Asaf Badouh