3a9cbeed73
ARM assembly parsing and encoding for SSAT instruction.
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Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').
Add tests for diagnostics and proper encoding.
llvm-svn: 135990
2011-07-25 22:20:28 +00:00
801e0a3fde
ARM SSAT instruction 5-bit immediate handling.
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The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.
llvm-svn: 135823
2011-07-22 23:16:18 +00:00
39f9388a9d
Thumb assembly support for SETEND instruction.
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llvm-svn: 135778
2011-07-22 17:52:23 +00:00
0491270f99
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
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llvm-svn: 135722
2011-07-21 23:38:37 +00:00
a20cde31e7
Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
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llvm-svn: 135636
2011-07-20 23:34:39 +00:00
a288b1c10a
ARM PKH shift ammount operand printing tweaks.
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Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.
llvm-svn: 135626
2011-07-20 21:40:26 +00:00
a98f80095b
ARM: Tidy up representation of PKH instruction.
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The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't
be also encoded as part of the shift value immediate. Otherwise we're able to
represent invalid instructions, plus it needlessly complicates the
representation. Preparatory work for asm parsing of these instructions.
llvm-svn: 135616
2011-07-20 20:32:09 +00:00
83c6c4f30e
Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler.
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llvm-svn: 135442
2011-07-18 23:25:34 +00:00
64d53620aa
Re-apply r135319 with a fix for the constant island pass.
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Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change.
llvm-svn: 135414
2011-07-18 18:50:52 +00:00
2ebff84b90
Revert r135319 in an attempt to get to unbreak testers.
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llvm-svn: 135343
2011-07-16 09:17:43 +00:00
d57a049e5c
Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change.
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llvm-svn: 135319
2011-07-15 22:49:31 +00:00
454e1c7abb
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
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llvm-svn: 135290
2011-07-15 18:46:47 +00:00
cb1a888fde
Eliminate "const" from extern const to fix breakeage since r135184 on msvc.
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MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions.
llvm-svn: 135269
2011-07-15 12:50:21 +00:00
bc153d49b7
Next round of MC refactoring. This patch factor MC table instantiations, MC
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registeration and creation code into XXXMCDesc libraries.
llvm-svn: 135184
2011-07-14 20:59:42 +00:00
b218202586
ARM ISB instruction assembly parsing.
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The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.
llvm-svn: 135156
2011-07-14 18:00:31 +00:00
1e210d08d8
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
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llvm-svn: 134024
2011-06-28 20:07:07 +00:00
6cc775f905
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
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sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
llvm-svn: 134021
2011-06-28 19:10:37 +00:00
a51604e511
Restore an accidentally removed comment.
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llvm-svn: 132044
2011-05-25 04:48:17 +00:00
310b3472ec
Change the order of tBX's operands so that the predicate operands come after the
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target register, matching BX. I filed this bug because I was confused at first:
PR10007 - ARM branch instructions have inconsistent predicate operand placement
<http://llvm.org/bugs/show_bug.cgi?id=10007 >
llvm-svn: 132041
2011-05-25 04:45:23 +00:00
012247e60c
Rename tBX_Rm to tBX.
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llvm-svn: 132040
2011-05-25 04:45:20 +00:00
a0c9c75df2
Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx
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Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and
modified ARMDisassemblerCore.cpp a little bit.
llvm-svn: 131859
2011-05-22 17:51:04 +00:00
071634612d
Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand.
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llvm-svn: 131565
2011-05-18 20:32:41 +00:00
886894cb70
Fix a bug in the case that there is no add or subtract symbol and the offset
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value is zero so it does not add a NULL expr operand.
llvm-svn: 130330
2011-04-27 21:02:27 +00:00
dc62e59776
Fix typo in the comment.
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llvm-svn: 129837
2011-04-19 23:58:52 +00:00
48592ee5af
Thumb2 BFC was insufficiently encoded.
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rdar://problem/9292717
llvm-svn: 129619
2011-04-15 22:52:15 +00:00
761e1e3512
A8.6.315 VLD3 (single 3-element structure to all lanes)
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The a bit must be encoded as 0.
rdar://problem/9292625
llvm-svn: 129618
2011-04-15 22:49:08 +00:00
421316178e
The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions
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(single element or n-element structure to all lanes).
llvm-svn: 129550
2011-04-15 00:10:45 +00:00
4251b151b1
Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.
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llvm-svn: 129531
2011-04-14 19:13:28 +00:00
d0fb04f437
Thumb disassembler did not handle tBRIND (indirect branch) properly.
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rdar://problem/9280370
llvm-svn: 129480
2011-04-13 21:59:01 +00:00
b6a37bff21
Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc).
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rdar://problem/9280470
llvm-svn: 129471
2011-04-13 21:35:49 +00:00
ffa6378fd6
The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.
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rdar://problem/9279440
llvm-svn: 129469
2011-04-13 21:04:32 +00:00
70591cbc60
Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such.
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rdar://problem/9276651
llvm-svn: 129462
2011-04-13 19:46:05 +00:00
0d306a7840
Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled.
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rdar://problem/9276427
llvm-svn: 129456
2011-04-13 17:51:02 +00:00
3c2f74c9f3
Add sanity check for Ld/St Dual forms of Thumb2 instructions.
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rdar://problem/9273947
llvm-svn: 129411
2011-04-12 23:31:00 +00:00
960eef3db3
The Thumb2 RFE instructions need to have their second halfword fully specified.
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In addition, the base register is not rGPR, but GPR with th exception that:
if n == 15 then UNPREDICTABLE
rdar://problem/9273836
llvm-svn: 129391
2011-04-12 21:41:51 +00:00
01637b9acb
Add bad register checks for Thumb2 Ld/St instructions.
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rdar://problem/9269047
llvm-svn: 129387
2011-04-12 21:17:51 +00:00
ab86a519f8
The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23}
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be specified as '1' (add = TRUE).
Also add a utility function for Thumb2.
llvm-svn: 129377
2011-04-12 18:48:00 +00:00
d0e2be39ea
Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple.
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llvm-svn: 129365
2011-04-12 17:09:04 +00:00
672ef14a62
A8.6.16 B
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Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;
rdar://problem/9268681
llvm-svn: 129325
2011-04-12 00:14:49 +00:00
dc8bf9ec08
Thumb disassembler was erroneously rejecting "blx sp" instruction.
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rdar://problem/9267838
llvm-svn: 129320
2011-04-11 23:33:30 +00:00
f79d5365de
Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled.
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rdar://problem/9266265
llvm-svn: 129298
2011-04-11 21:14:35 +00:00
74adbddade
Trivial comment fix.
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llvm-svn: 129288
2011-04-11 18:51:50 +00:00
66fab75920
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as
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invalid instructions.
llvm-svn: 129286
2011-04-11 18:34:12 +00:00
9377a52c12
Adding support for printing operands symbolically to llvm's public 'C'
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disassembler API. Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets for example this:
blx _puts
instead of this:
blx #-36
And even print the expression encoded in the Mach-O relocation entried for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
llvm-svn: 129284
2011-04-11 18:08:50 +00:00
4e1796e8d1
Fix an apparent typo that made GCC complain
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llvm-svn: 129160
2011-04-08 21:59:49 +00:00
f2faf4e53a
Check opcoe (dmb, dsb) instead of bitfields matching.
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llvm-svn: 129148
2011-04-08 20:03:46 +00:00
a9570f77d5
Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.
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PR9650
rdar://problem/9257565
llvm-svn: 129147
2011-04-08 19:41:22 +00:00
875e0e4626
Sanity check the option operand for DMB/DSB.
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PR9648
rdar://problem/9257634
llvm-svn: 129146
2011-04-08 19:18:07 +00:00
7e51b4640f
Add sanity checking for bad register specifier(s) for the DPFrm instructions.
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Add more test cases to exercise the logical branches related to the above change.
llvm-svn: 129117
2011-04-08 00:29:09 +00:00
04efb8f6ce
Add sanity checking for invalid register encodings for signed/unsigned extend instructions.
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Add some test cases.
llvm-svn: 129098
2011-04-07 19:28:58 +00:00
Jim Grosbach