3b0f5e4d61
- Add target lowering hooks that specify which setcc conditions are illegal,
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i.e. conditions that cannot be checked with a single instruction. For example,
SETONE and SETUEQ on x86.
- Teach legalizer to implement *illegal* setcc as a and / or of a number of
legal setcc nodes. For now, only implement FP conditions. e.g. SETONE is
implemented as SETO & SETNE, SETUEQ is SETUO | SETEQ.
- Move x86 target over.
llvm-svn: 57542
2008-10-15 02:05:31 +00:00
56b6885104
When doing the very-late shift-and address-mode optimization,
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create a new DAG node to represent the new shift to keep the
DAG consistent, even though it'll almost always be folded into
the address.
If a user of the resulting address has multiple uses, the
nodes may get revisited by a later MatchAddress call, in which
case DAG inconsistencies do matter.
This fixes PR2849.
llvm-svn: 57465
2008-10-13 20:52:04 +00:00
da9b752883
FIX PR2794. Make sure SIGN_EXTEND_INREG nodes introduced by LegalizeSetCCOperands are leglized. Patch by Richard Pennington.
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llvm-svn: 57460
2008-10-13 18:46:18 +00:00
4c499c4fa6
Also update sub-register intervals after a trivial computation is rematt'ed for a copy instruction. PR2775.
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llvm-svn: 57458
2008-10-13 18:35:52 +00:00
762f0f53ec
Add a test case for _Complex passed as a FCA.
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llvm-svn: 57456
2008-10-13 18:13:07 +00:00
2753955fc0
Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
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parameters instead of raw Constants. This prevents the constants from
being selected by the isel pass, fixing PR2735.
llvm-svn: 57385
2008-10-11 22:08:30 +00:00
a0cce200c5
Add testcase for 'r' inline asm operand
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llvm-svn: 57361
2008-10-10 20:28:59 +00:00
b36d3b2bb7
This does not fail anymore
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llvm-svn: 57360
2008-10-10 20:28:32 +00:00
e6b3093b18
Add sparc test for memory operand used in inline asm
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llvm-svn: 57348
2008-10-10 10:15:33 +00:00
b3692f7d38
This is not failing anymore
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llvm-svn: 57347
2008-10-10 10:15:18 +00:00
1a84f86271
get CodeGen/Alpha/mul128.ll to work.
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llvm-svn: 57318
2008-10-09 04:50:56 +00:00
60ad173dfe
Remove -disable-fast-isel. Use cl::boolOrDefault with -fast-isel
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instead.
So now: -fast-isel or -fast-isel=true enable fast-isel, and
-fast-isel=false disables it. Fast-isel is also on by default
with -fast, and off by default otherwise.
llvm-svn: 57270
2008-10-07 23:00:56 +00:00
b8118fd432
Add a testcase for i256 add. i256 isn't fully supported in
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codegen right now, but add and subtract work.
llvm-svn: 57260
2008-10-07 20:39:12 +00:00
83f5f40b6a
128 mul test, xfailed
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llvm-svn: 57250
2008-10-07 17:13:32 +00:00
1699ad9030
Certain patterns involving the "movss" instruction were marked as requiring SSE2, when in reality movss is an SSE1 instruction.
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llvm-svn: 57246
2008-10-07 16:14:11 +00:00
3a9be150be
Expand arith on machines without carry flags
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llvm-svn: 57243
2008-10-07 14:15:42 +00:00
315e3c0e64
no need to write the output to the disk
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llvm-svn: 57232
2008-10-07 04:06:55 +00:00
3b893a905e
Add test case for ADDC ADDE expansion
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llvm-svn: 57228
2008-10-07 02:30:13 +00:00
6c6729f3a8
Be more precise about which conversions of NaNs
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are Inexact. (These are not Inexact as defined
by IEEE754, but that seems like a reasonable way
to abstract what happens: information is lost.)
llvm-svn: 57218
2008-10-06 22:59:10 +00:00
94d14f2d45
Fix PR2850 and PR2863. Only generate movddup for 128-bit SSE vector shuffles.
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llvm-svn: 57210
2008-10-06 21:13:08 +00:00
b52ef06c8c
Revert r56675 - it breaks unwinding runtime everywhere.
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llvm-svn: 57048
2008-10-04 11:09:36 +00:00
78bb44fcd4
Fix a bug in the local allocator's liveness computation where it
...
was setting kill flags on tied uses in two-address instructions.
The kill flags were causing the allocator to think it could
allocate the use and its tied def in different registers.
llvm-svn: 57039
2008-10-04 00:31:14 +00:00
867d549fce
Handle some 64-bit atomics on x86-32, some of the time.
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llvm-svn: 56963
2008-10-02 18:53:47 +00:00
88536398ff
Fix a think-o in isSafeToMove. This fixes it from thinking that
...
volatile memory references are safe to move.
llvm-svn: 56948
2008-10-02 15:04:30 +00:00
dfc507d2b5
Disable fast-isel for this test, as it doesn't emit the same
...
number of instructions.
llvm-svn: 56940
2008-10-01 23:48:35 +00:00
1b76f2c40b
Remove OptimizeForSize global. Use function attribute optsize.
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llvm-svn: 56937
2008-10-01 23:18:38 +00:00
5c8c00af1f
Split this test and move it into target-specific directories.
...
This fixes failures on configurations that don't have one or the
other targets enabled.
llvm-svn: 56926
2008-10-01 19:46:30 +00:00
7354227de0
nounwind-ify this test.
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llvm-svn: 56918
2008-10-01 15:07:14 +00:00
920f6d588e
Moved this option to the front-end.
...
llvm-svn: 56901
2008-10-01 01:02:18 +00:00
1df16dff64
Use explicit target-triples to unbreak this test on non-darwin systems.
...
llvm-svn: 56896
2008-10-01 00:25:38 +00:00
1782584f56
Just don't transform this memset into "bzero" if no-builtin is specified.
...
llvm-svn: 56888
2008-09-30 22:05:33 +00:00
e818bc159f
- Initialize "--no-builtin" to "false".
...
- Testcase for r56885.
llvm-svn: 56886
2008-09-30 21:40:30 +00:00
9156bd2f48
Re-apply 56835 along with header file changes.
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llvm-svn: 56848
2008-09-30 15:44:16 +00:00
2b9adce1d0
Revert commit 56835 since it breaks the build.
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"If a re-materializable instruction has a register
operand, the spiller will change the register operand's
spill weight to HUGE_VAL to avoid it being spilled.
However, if the operand is already in the queue ready
to be spilled, avoid re-materializing it".
llvm-svn: 56837
2008-09-30 10:00:30 +00:00
9469049f7d
If a re-materializable instruction has a register operand, the spiller will change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it.
...
llvm-svn: 56835
2008-09-30 06:36:58 +00:00
82237f2f42
Fix PR2835. Do not change the width of a volatile load.
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llvm-svn: 56792
2008-09-29 17:26:18 +00:00
3774b2f292
Re-apply 56683 with fixes.
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llvm-svn: 56748
2008-09-27 01:56:22 +00:00
9eb525d4f9
Implement function notes as function attributes.
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llvm-svn: 56716
2008-09-26 23:51:19 +00:00
7d6fa97567
Implement "punpckldq %xmm0, $xmm0" as "pshufd $0x50, %xmm0, %xmm" unless optimizing for code size.
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llvm-svn: 56711
2008-09-26 23:41:32 +00:00
c966a737c5
Temporarily reverting r56683. This is causing a failure during the build of llvm-gcc:
...
/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311.
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter > for instructions.
{standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
{standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression
{standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
...
llvm-svn: 56703
2008-09-26 22:10:44 +00:00
d77cbe8947
Fix @llvm.frameaddress codegen. FP elimination optimization should be disabled when frame address is desired. Also add support for depth > 0.
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llvm-svn: 56683
2008-09-26 19:48:35 +00:00
994dd0bbec
Avoid spilling EBP / RBP twice in the prologue.
...
llvm-svn: 56675
2008-09-26 19:14:21 +00:00
9dbe45c000
Prefer movlhps over punpcklqdq, etc. in more cases.
...
llvm-svn: 56627
2008-09-25 23:35:16 +00:00
74c9ed91b0
With sse3 and when the source is a load or has multiple uses, favors movddup over shuffp*, pshufd, etc. Without sse3 or when the source is from a register, make use of movlhps
...
llvm-svn: 56620
2008-09-25 20:50:48 +00:00
c50ada2f56
Accept 'inreg' attribute on x86 functions as
...
meaning sse_regparm (i.e. float/double values go
in XMM0 instead of ST0). Update documentation
to reflect reality.
llvm-svn: 56619
2008-09-25 20:47:45 +00:00
f8ead16b50
Fix patterns for SSE4.1 move and sign extend instructions. Also add instructions which fold VZEXT_MOVL and VZEXT_LOAD.
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llvm-svn: 56594
2008-09-24 23:27:55 +00:00
86d421df23
Remove SelectionDag early allocation of registers
...
for earlyclobbers. Teach Local RA about earlyclobber,
and add some tests for it.
llvm-svn: 56592
2008-09-24 23:13:09 +00:00
e0add20c1b
Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
...
llvm-svn: 56526
2008-09-24 00:05:32 +00:00
9e9426cb82
Support x86 specific inline asm modifier 'J'.
...
llvm-svn: 56483
2008-09-22 23:57:37 +00:00
796a271c5f
Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC.
...
llvm-svn: 56436
2008-09-22 14:50:07 +00:00
Evan Cheng