fa8f9f937a
Undo r50574. We are already ensuring the folded load address is 16-byte aligned.
...
llvm-svn: 50578
2008-05-02 17:01:01 +00:00
50f82f2c8e
Not safe folding a load + FsXORPSrr into FsXORPSrm. It's loading a FR64 value but the load folding variant expects a 16-byte aligned address.
...
llvm-svn: 50574
2008-05-02 07:50:58 +00:00
984e7199cc
Don't forget to update the current operand when getting the size of an instruction.
...
llvm-svn: 50007
2008-04-20 23:36:47 +00:00
147cb764b5
Don't forget about sub-register indices when rematting instructions.
...
llvm-svn: 49830
2008-04-16 23:44:44 +00:00
ae84bbdbed
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
...
llvm-svn: 49809
2008-04-16 20:10:13 +00:00
3bc3ddd638
Rename MemOperand to MachineMemOperand. This was suggested by
...
review feedback from Chris quite a while ago. No functionality
change.
llvm-svn: 49348
2008-04-07 19:35:22 +00:00
b86595fb0a
ReMat of load from stub in pic mode extends the life of pic base. Currently spiller doesn't do a good job of estimating the impact. Disable for now.
...
llvm-svn: 49059
2008-04-01 23:26:12 +00:00
19a6dd9f2a
Remove unnecessary and non-deterministic checking code. Re-enable remat of load from gv stub.
...
llvm-svn: 49054
2008-04-01 21:38:20 +00:00
306e3dcff4
Disabling remat of load from gv stub (temporarily) again to fix llvmgcc bootstrap miscompare.
...
llvm-svn: 49037
2008-04-01 07:33:13 +00:00
e4f77c69ac
It's not safe to fold a load from GV stub or constantpool into a two-address use.
...
llvm-svn: 49002
2008-03-31 23:19:51 +00:00
ed6e34fe41
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
...
llvm-svn: 48995
2008-03-31 20:40:39 +00:00
1973a46cd3
Re-apply 48911.
...
llvm-svn: 48977
2008-03-31 07:54:19 +00:00
b8654202dd
Backing out 48911 for now. It's breaking stuff.
...
llvm-svn: 48922
2008-03-28 17:49:06 +00:00
9ae4d7b719
Load from stub is already re-materializable.
...
llvm-svn: 48911
2008-03-28 06:49:25 +00:00
308e564693
Code clean up.
...
llvm-svn: 48856
2008-03-27 01:45:11 +00:00
29e62a59f3
Allow certain lea instructions to be rematerialized.
...
llvm-svn: 48855
2008-03-27 01:41:09 +00:00
4fb07c6500
Remove an unused command line option.
...
llvm-svn: 48854
2008-03-27 01:30:24 +00:00
883cbfd0ba
Add CMP32mr and friends to the load-unfolding table. Among
...
other things, this allows the scheduler to unfold a load operand
in the 2008-01-08-SchedulerCrash.ll testcase, so it now successfully
clones the comparison to avoid a pushf+popf.
llvm-svn: 48777
2008-03-25 16:53:19 +00:00
5abbe6cef5
Add support for calls that return two FP values in
...
ST(0)/ST(1).
llvm-svn: 48634
2008-03-21 06:38:26 +00:00
d3d0ad3f58
Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
...
llvm-svn: 48412
2008-03-16 03:12:01 +00:00
dd55d3f1b2
Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.
...
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329
2008-03-13 05:47:01 +00:00
7b27ccfd5e
coalesce away 80-bit floating point copies.
...
llvm-svn: 48241
2008-03-11 19:30:09 +00:00
7930d8e775
convert a massive if statement to a switch.
...
llvm-svn: 48240
2008-03-11 19:28:17 +00:00
342e4104d3
Missed part of recommit.
...
llvm-svn: 48224
2008-03-11 10:27:36 +00:00
a4fa0ad30d
abort with an assert instead of a cerr to get line#
...
llvm-svn: 48199
2008-03-10 23:56:08 +00:00
d4e1d9eeb2
Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
...
llvm-svn: 48167
2008-03-10 19:31:26 +00:00
4ba3f0430b
Allow insert_subreg into implicit, target-specific values.
...
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.
llvm-svn: 48130
2008-03-10 06:12:08 +00:00
86829f0ff7
teach X86InstrInfo::copyRegToReg how to copy into ST(0) from
...
an RFP register class.
Teach ScheduleDAG how to handle CopyToReg with different src/dst
reg classes.
This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.
llvm-svn: 48107
2008-03-09 09:15:31 +00:00
b79bafcec8
add some code to support cross-register class copying from
...
RST -> RFP{32/64/80}. We only handle ST(0) for now.
llvm-svn: 48104
2008-03-09 08:46:19 +00:00
c4c9dde04c
rearrange some code, no functionality change.
...
llvm-svn: 48101
2008-03-09 07:58:04 +00:00
42cb72e52c
Turning on remat of pic loads.
...
llvm-svn: 47524
2008-02-23 02:07:42 +00:00
4d17671997
No need recognize load from a fixed argument slot as re-materializable. LiveIntervalAnalysis already handles it as a special case.
...
llvm-svn: 47522
2008-02-23 01:47:44 +00:00
94ba37f8e3
Allow re-materialization of pic load (controlled by -remat-pic-load for now).
...
llvm-svn: 47476
2008-02-22 09:25:47 +00:00
244183ef0d
commuteInstr() can now commute non-ssa machine instrs.
...
llvm-svn: 47043
2008-02-13 02:46:49 +00:00
3b3286d4bc
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
...
llvm-svn: 46893
2008-02-08 21:20:40 +00:00
8d59dd119b
Added missing entries in X86 load / store folding tables.
...
llvm-svn: 46866
2008-02-08 00:12:56 +00:00
1bc1cae318
In some cases, e.g. ADD32ri, no transformation is made. Guide against it.
...
llvm-svn: 46849
2008-02-07 08:29:53 +00:00
18df33d0c8
fix a wordo that gordon noticed :)
...
llvm-svn: 45896
2008-01-12 00:53:16 +00:00
6da61c2515
Any x86 instruction that reads from an invariant location is invariant.
...
This allows us to sink things like:
cvtsi2sd 32(%esp), %xmm1
when reading from the argument area, for example.
llvm-svn: 45895
2008-01-12 00:35:08 +00:00
596875118c
rename MachineInstr::setInstrDescriptor -> setDesc
...
llvm-svn: 45871
2008-01-11 18:10:50 +00:00
806dd0e2ac
remove xchg and shift-reg-by-1 instructions, which are dead.
...
llvm-svn: 45870
2008-01-11 18:00:50 +00:00
c8226f32e9
Simplify the side effect stuff a bit more and make licm/sinking
...
both work right according to the new flags.
This removes the TII::isReallySideEffectFree predicate, and adds
TII::isInvariantLoad.
It removes NeverHasSideEffects+MayHaveSideEffects and adds
UnmodeledSideEffects as machine instr flags. Now the clients
can decide everything they need.
I think isRematerializable can be implemented in terms of the
flags we have now, though I will let others tackle that.
llvm-svn: 45843
2008-01-10 23:08:24 +00:00
f171482a66
verify that the frame index is immutable before remat'ing (still disabled)
...
or being side-effect free.
llvm-svn: 45816
2008-01-10 04:16:31 +00:00
9129f51f9b
add a testcase
...
llvm-svn: 45768
2008-01-09 00:37:18 +00:00
a3bdad153f
Operand 1 should be a register. We don't care if it's a preg, vreg, or 0.
...
llvm-svn: 45699
2008-01-07 08:05:29 +00:00
03ad885039
rename TargetInstrDescriptor -> TargetInstrDesc.
...
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
llvm-svn: 45695
2008-01-07 07:27:27 +00:00
b0d06b4381
Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
...
llvm-svn: 45680
2008-01-07 03:13:06 +00:00
f0f438a517
remove MachineOpCode typedef.
...
llvm-svn: 45679
2008-01-07 02:48:55 +00:00
e55e115616
Add predicates methods to TargetOperandInfo, and switch all clients
...
over to using them, instead of diddling Flags directly. Change the
various flags from const variables to enums.
llvm-svn: 45677
2008-01-07 02:39:19 +00:00
a98c679de0
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
...
that it is cheap and efficient to get.
Move a variety of predicates from TargetInstrInfo into
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around. Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.
Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.
llvm-svn: 45674
2008-01-07 01:56:04 +00:00
2a3be7bb6c
Move even more functionality from MRegisterInfo into TargetInstrInfo.
...
Some day I'll get it all moved over...
llvm-svn: 45672
2008-01-07 01:35:02 +00:00
5fa2c64b78
Fix comment.
...
llvm-svn: 45638
2008-01-05 23:30:51 +00:00
be984cf10b
Chris and Evan noticed that this check was compleatly fubared. I was
...
checking that there was a from a global instead of a load from the stub
for a global, which is the one that's safe to hoist.
Consider this program:
volatile char G[100];
int B(char *F, int N) {
for (; N > 0; --N)
F[N] = G[N];
}
In static mode, we shouldn't be hoisting the load from G:
$ llc -relocation-model=static -o - a.bc -march=x86 -machine-licm
LBB1_1: # bb.preheader
leal -1(%eax), %edx
testl %edx, %edx
movl $1, %edx
cmovns %eax, %edx
xorl %esi, %esi
LBB1_2: # bb
movb _G(%eax), %bl
movb %bl, (%ecx,%eax)
llvm-svn: 45626
2008-01-05 09:18:04 +00:00
e0f0c4aa02
enable sinking and licm of loads from the argument area. I'd like to enable this
...
for remat, but can't due to an RA bug.
llvm-svn: 45623
2008-01-05 06:10:42 +00:00
d4738ee8e1
simplify some code by using shorter accessors.
...
llvm-svn: 45622
2008-01-05 05:28:30 +00:00
86f4a2e4f2
revert my previous patch.
...
llvm-svn: 45621
2008-01-05 05:26:26 +00:00
69d7902cf1
factor some code better to avoid redundancy between
...
isReallySideEffectFree and isReallyTriviallyReMaterializable. Why is a load from
a global considered side-effect-free but not rematable?
llvm-svn: 45620
2008-01-05 05:19:56 +00:00
6bb0c52628
Move some more functionality from MRegisterInfo to TargetInstrInfo.
...
llvm-svn: 45603
2008-01-04 23:57:37 +00:00
e1f28e7871
Machine LICM will check that operands are defined outside of the loop. Also
...
check that register isn't 0 before going further.
llvm-svn: 45498
2008-01-02 21:10:40 +00:00
eee14601b1
Move some more instruction creation methods from RegisterInfo into InstrInfo.
...
llvm-svn: 45484
2008-01-01 21:11:32 +00:00
b0fb17fd34
Fix a bug in my previous patch: refer to the impl not the pure virtual version. It's unclear why gcc would ever compile this...
...
llvm-svn: 45476
2008-01-01 01:05:34 +00:00
25568e4cef
Fix a problem where lib/Target/TargetInstrInfo.h would include and use
...
a header file from libcodegen. This violates a layering order: codegen
depends on target, not the other way around. The fix to this is to
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen. It is defined in libcodegen, where
the base is not.
llvm-svn: 45475
2008-01-01 01:03:04 +00:00
7a73ae9a86
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
...
Machine-level API cleanup instigated by Chris.
llvm-svn: 45470
2007-12-31 06:32:00 +00:00
a10fff51d9
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
...
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
llvm-svn: 45467
2007-12-31 04:13:23 +00:00
a5bb370aa4
Add new shorter predicates for testing machine operands for various types:
...
e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should just start using the
shorter names.
Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(),
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.
llvm-svn: 45464
2007-12-30 23:10:15 +00:00
5c4637816e
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
...
llvm-svn: 45453
2007-12-30 20:49:49 +00:00
7749a9014b
If we have a load of a global address that's not modified during the
...
function, then go ahead and hoist it out of the loop. This is the result:
$ cat a.c
volatile int G;
int A(int N) {
for (; N > 0; --N)
G++;
}
$ llc -o - -relocation-model=pic
_A:
...
LBB1_2: # bb
movl L_G$non_lazy_ptr-"L1$pb"(%eax), %esi
incl (%esi)
incl %edx
cmpl %ecx, %edx
jne LBB1_2 # bb
...
$ llc -o - -relocation-model=pic -machine-licm
_A:
...
movl L_G$non_lazy_ptr-"L1$pb"(%eax), %eax
LBB1_2: # bb
incl (%eax)
incl %edx
cmpl %ecx, %edx
jne LBB1_2 # bb
...
I'm limiting this to the MOV32rm x86 instruction for now.
llvm-svn: 45444
2007-12-30 03:18:58 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
...
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
b3d85a5d4b
Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I
...
based what flag to set on whether it was already marked as
"isRematerializable". If there was a further check to determine if it's "really"
rematerializable, then I marked it as "mayHaveSideEffects" and created a check
in the X86 back-end similar to the remat one.
llvm-svn: 45132
2007-12-17 23:07:56 +00:00
3f19dfe794
Reverting 44702. It wasn't correct to rename them.
...
llvm-svn: 44727
2007-12-08 23:58:46 +00:00
2b07d8c5a0
Renaming:
...
isTriviallyReMaterializable -> hasNoSideEffects
isReallyTriviallyReMaterializable -> isTriviallyReMaterializable
llvm-svn: 44702
2007-12-08 07:17:56 +00:00
9ccea99165
Added tail call optimization to the x86 back end. It can be
...
enabled by passing -tailcallopt to llc. The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
elf/pic enabled + callee is in module + callee has
visibility protected or hidden
llvm-svn: 42870
2007-10-11 19:40:01 +00:00
82bc90ac60
Under 64-bit mode use LEA64_32r instead of LEA64r to save a byte.
...
llvm-svn: 42783
2007-10-09 07:14:53 +00:00
18109c88c3
Allow x86 compare to be commutable by default.
...
llvm-svn: 42761
2007-10-08 18:27:46 +00:00
1151ffde70
Commute x86 cmove instructions by swapping the operands and change the condition
...
to its inverse.
Testing this as llcbeta
llvm-svn: 42661
2007-10-05 23:13:21 +00:00
484cab7a2f
Enable convertToThreeAddress for X86 by default.
...
llvm-svn: 42655
2007-10-05 22:31:10 +00:00
d3ccf00870
INC64_32r -> LEA64_32r is better than INC64_32r -> LEA32r, but it still can
...
cause performance degradation.
llvm-svn: 42653
2007-10-05 21:55:32 +00:00
fa2c828687
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g.
...
leal 1(%ecx), %edi, which requires 67H prefix.
llvm-svn: 42647
2007-10-05 20:34:26 +00:00
aac0f8e351
Add support to convert more 64-bit instructions to 3-address instructions.
...
llvm-svn: 42642
2007-10-05 18:20:36 +00:00
a8a9c15e30
Testing convertToThreeeAddress as X86 llcbeta.
...
llvm-svn: 42630
2007-10-05 08:04:01 +00:00
5fb5a1f389
Enabling new condition code modeling scheme.
...
llvm-svn: 42459
2007-09-29 00:00:36 +00:00
e95f391ef1
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after
...
all the kinks are worked out.
llvm-svn: 42285
2007-09-25 01:57:46 +00:00
3243e10ef0
Add 64-bit jmp instructions to the list of instructions that
...
can terminate a block with no fall-through.
llvm-svn: 42029
2007-09-17 15:19:08 +00:00
48ea03d169
Add patterns for SHLD64* and SHRD64*.
...
llvm-svn: 41975
2007-09-14 23:17:45 +00:00
483e1ce16e
Add implicit def of EFLAGS on those instructions that may modify flags.
...
llvm-svn: 41962
2007-09-14 21:48:26 +00:00
e2f23a3abf
Add lengthof and endof templates that hide a lot of sizeof computations.
...
Patch by Sterling Stein!
llvm-svn: 41758
2007-09-07 04:06:50 +00:00
189df733ed
Fix a bug in X86InstrInfo::convertToThreeAddress that caused it to codegen:
...
leal (,%rcx,8), %rcx
It should be
leal (,%rcx,8), %ecx
llvm-svn: 41735
2007-09-06 00:14:41 +00:00
d36d30b53c
Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled.
...
llvm-svn: 41007
2007-08-10 21:18:25 +00:00
936d17aa1b
Don't pollute the meaning of isUnpredicatedTerminator.
...
llvm-svn: 40537
2007-07-26 17:32:14 +00:00
d771e05121
isUnpredicatedTerminator should treat conditional branches as unpredicated terminator.
...
llvm-svn: 37960
2007-07-06 23:22:03 +00:00
3d7008cd49
Refactor X87 instructions. As a side effect, all
...
their names are changed.
llvm-svn: 37876
2007-07-04 21:07:47 +00:00
a2b3c175db
Fix for PR 1505 (and 1489). Rewrite X87 register
...
model to include f32 variants. Some factoring
improvments forthcoming.
llvm-svn: 37847
2007-07-03 00:53:03 +00:00
e8c1e428f2
Revert the earlier change that removed the M_REMATERIALIZABLE machine
...
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
9e82064924
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
...
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
616627b002
Do not treat FP_REG_KILL as terminator in branch analysis (X86).
...
llvm-svn: 37578
2007-06-14 22:03:45 +00:00
4a4a8eb00e
Add a target hook to allow loads from constant pools to be rematerialized, and an
...
implementation for x86.
llvm-svn: 37576
2007-06-14 20:50:44 +00:00
c68554683d
Handle blocks with 2 unconditional branches in AnalyzeBranch.
...
llvm-svn: 37571
2007-06-13 17:59:52 +00:00
5514bbef46
Add a utility routine to check for unpredicated terminator instruction.
...
llvm-svn: 37528
2007-06-08 21:59:56 +00:00
fc94eb66d2
BlockHasNoFallThrough() now returns true if block ends with a return instruction.
...
llvm-svn: 37266
2007-05-21 18:44:17 +00:00
e20dd92792
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
...
llvm-svn: 37193
2007-05-18 00:18:17 +00:00
Evan Cheng