59f75bba24
Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
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These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.
llvm-svn: 99309
2010-03-23 18:54:46 +00:00
cc0a2a75a0
Change VST1 instructions for loading Q register values to operate on pairs
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of D registers. Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.
llvm-svn: 99265
2010-03-23 06:20:33 +00:00
340861d29e
Change VLD1 instructions for loading Q register values to operate on pairs
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of D registers. Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.
llvm-svn: 99261
2010-03-23 05:25:43 +00:00
c53a1125ff
Rename some VLD1/VST1 instructions to match the implementation, i.e., the
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corresponding NEON instructions, instead of operation they are currently
used for.
llvm-svn: 99189
2010-03-22 18:13:18 +00:00
ae08a736d6
Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")
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with changes to add a separate optional register update argument. Change all
the NEON instructions with address register writeback to use it.
llvm-svn: 99095
2010-03-20 22:13:40 +00:00
c0795f8b87
Rename some instructions for consistency and sanity: use "_UPD" suffix for
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load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.
llvm-svn: 99066
2010-03-20 18:35:24 +00:00
c7ba918b84
Revert 98683. It is breaking something in the disassembler.
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llvm-svn: 98692
2010-03-16 23:01:13 +00:00
c953bca10b
Remove redundant writeback flag from ARM address mode 6. Also remove the
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optional register update argument, which is currently unused -- when we add
support for that, it can just be a separate operand.
llvm-svn: 98683
2010-03-16 21:44:40 +00:00
f98f124a73
Sink InstructionSelect() out of each target into SDISel, and rename it
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DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.
Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.
17 files changed, 114 insertions(+), 430 deletions(-)
llvm-svn: 97555
2010-03-02 06:34:30 +00:00
5e73ff2e3a
Split SelectionDAGISel::IsLegalAndProfitableToFold to
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IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.
This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.
llvm-svn: 96255
2010-02-15 19:41:07 +00:00
b06015aa69
move target-independent opcodes out of TargetInstrInfo
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into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
llvm-svn: 95687
2010-02-09 19:54:29 +00:00
6c0fb92c03
Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2.
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llvm-svn: 93829
2010-01-19 00:44:15 +00:00
8546ec9c14
Patch by David Conrad:
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"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
sequence it is now."
llvm-svn: 93758
2010-01-18 19:58:49 +00:00
55d2ebda31
Fix an off-by-one error that caused the chain operand to be dropped from Neon
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vector load-lane and store-lane instructions.
llvm-svn: 93673
2010-01-17 05:58:23 +00:00
ea6f91ff64
Change SelectCode's argument from SDValue to SDNode *, to make it more
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clear what information these functions are actually using.
This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.
llvm-svn: 92564
2010-01-05 01:24:18 +00:00
2522908653
Materialize global addresses via movt/movw pair, this is always better
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than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
llvm-svn: 89720
2009-11-24 00:44:37 +00:00
a33fc86be3
Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.
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llvm-svn: 89542
2009-11-21 06:21:52 +00:00
81a2851bcb
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all.
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llvm-svn: 89423
2009-11-20 00:54:03 +00:00
b6c7704a8d
Refactor cmov selection code out to a separate function. No functionality change.
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llvm-svn: 89396
2009-11-19 21:45:22 +00:00
82adca8373
80 col violation.
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llvm-svn: 89337
2009-11-19 08:16:50 +00:00
d7cf55cd0e
Use Unified Assembly Syntax for the ARM backend.
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llvm-svn: 86494
2009-11-09 00:11:35 +00:00
d1d002a6fe
Support alignment specifier for NEON vld/vst instructions
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llvm-svn: 86404
2009-11-07 21:25:39 +00:00
b15f4a1cbd
Remove uninteresting and confusing debug output.
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llvm-svn: 86149
2009-11-05 18:47:09 +00:00
e90a4aa703
Prune unnecessary include.
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llvm-svn: 85805
2009-11-02 16:58:31 +00:00
b678a56fef
Test commit. Added '.' to the comment line.
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llvm-svn: 85255
2009-10-27 17:25:15 +00:00
0f55e9ce2e
Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad.
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llvm-svn: 84813
2009-10-22 00:40:00 +00:00
786b15fe12
Match more patterns to movt.
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llvm-svn: 84751
2009-10-21 08:15:52 +00:00
ad03cf02f6
Remove unused variables to fix build warning.
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llvm-svn: 84144
2009-10-14 21:40:45 +00:00
c350cdf3b3
Refactor code to select NEON VST intrinsics.
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llvm-svn: 84122
2009-10-14 18:32:29 +00:00
12b4799787
Refactor code to select NEON VLD intrinsics.
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llvm-svn: 84117
2009-10-14 17:28:52 +00:00
93117bc499
More refactoring. NEON vst lane intrinsics can share almost all the code for
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vld lane intrinsics.
llvm-svn: 84110
2009-10-14 16:46:45 +00:00
4145e3ac8d
Refactor code for selecting NEON load lane intrinsics.
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llvm-svn: 84109
2009-10-14 16:19:03 +00:00
b62d160b3c
More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics
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by creating TargetConstants during instruction selection instead of during
legalization.
llvm-svn: 84042
2009-10-13 22:29:24 +00:00
3b51560ae4
Revise ARM inline assembly memory operands to require the memory address to
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be in a register. The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb. Radar 7137468.
llvm-svn: 84022
2009-10-13 20:50:28 +00:00
7460e0822f
Fix method name in comment, per Bob Wilson.
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llvm-svn: 84017
2009-10-13 20:25:58 +00:00
423e42b371
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
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llvm-svn: 84009
2009-10-13 18:59:48 +00:00
84e7967fae
Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.
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llvm-svn: 83600
2009-10-09 00:01:36 +00:00
c409030838
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.
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llvm-svn: 83598
2009-10-08 23:51:31 +00:00
b851eb356a
Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.
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llvm-svn: 83596
2009-10-08 23:38:24 +00:00
38ba47225a
Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.
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Also fix some copy-and-paste errors in previous changes.
llvm-svn: 83590
2009-10-08 22:53:57 +00:00
cf54e934f8
Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
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llvm-svn: 83585
2009-10-08 22:27:33 +00:00
c2728f44a9
Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.
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llvm-svn: 83568
2009-10-08 18:56:10 +00:00
fac9476589
Clean up some unnecessary initializations.
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llvm-svn: 83566
2009-10-08 18:52:56 +00:00
4facd965bd
Clean up a comment (indentation was wrong).
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llvm-svn: 83565
2009-10-08 18:51:31 +00:00
b6b0ab6117
Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.
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llvm-svn: 83526
2009-10-08 05:18:18 +00:00
71387b4b2f
Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.
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llvm-svn: 83518
2009-10-08 00:28:28 +00:00
d4f5670096
Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.
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llvm-svn: 83513
2009-10-08 00:21:01 +00:00
32cc4ec304
Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
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llvm-svn: 83508
2009-10-07 23:54:04 +00:00
5ef3c6d9f4
Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.
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llvm-svn: 83506
2009-10-07 23:39:57 +00:00
763be1a248
Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
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llvm-svn: 83502
2009-10-07 22:57:01 +00:00
Bob Wilson