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295 Commits

Author SHA1 Message Date
Dan Gohman f19609abe8 Convert the last remaining users of the non-APInt form of 
ComputeMaskedBits to use the APInt form, and remove the
non-APInt form.

llvm-svn: 47654
 2008-02-27 01:23:58 +00:00
Anton Korobeynikov 40d67c59d5 Remove bunch of gcc 4.3-related warnings from Target 
llvm-svn: 47369
 2008-02-20 11:22:39 +00:00
Dan Gohman 3a4be0fdef Rename MRegisterInfo to TargetRegisterInfo. 
llvm-svn: 46930
 2008-02-10 18:45:23 +00:00
Evan Cheng 2cb9068c78 Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead. 
llvm-svn: 46724
 2008-02-04 23:06:48 +00:00
Evan Cheng efd142a920 SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. 
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.

llvm-svn: 46659
 2008-02-02 04:07:54 +00:00
Dan Gohman 47a7d6fafe Factor the addressing mode and the load/store VT out of LoadSDNode 
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.

llvm-svn: 46538
 2008-01-30 00:15:11 +00:00
Chris Lattner 89f36e6b21 Finally implement correct ordered comparisons for PPC, even though 
the code generated is not wonderful.  This turns a miscompilation into
a code quality bug (noted in the ppc readme).  This fixes PR642, which
is over 2 years old (!).  Nate, please review this.

llvm-svn: 45742
 2008-01-08 06:46:30 +00:00
Chris Lattner 03ad885039 rename TargetInstrDescriptor -> TargetInstrDesc. 
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695
 2008-01-07 07:27:27 +00:00
Chris Lattner b0d06b4381 Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor 
llvm-svn: 45680
 2008-01-07 03:13:06 +00:00
Chris Lattner a98c679de0 Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects 
that it is cheap and efficient to get.

Move a variety of predicates from TargetInstrInfo into 
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around.  Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.

Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.

llvm-svn: 45674
 2008-01-07 01:56:04 +00:00
Chris Lattner a10fff51d9 Rename SSARegMap -> MachineRegisterInfo in keeping with the idea 
that "machine" classes are used to represent the current state of
the code being compiled.  Given this expanded name, we can start 
moving other stuff into it.  For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.

llvm-svn: 45467
 2007-12-31 04:13:23 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Evan Cheng ec271b104c Temporary solution: added a different set of BCTRL_Macho / BCTRL_ELF with right callee-saved defs set for ppc64. 
llvm-svn: 43248
 2007-10-23 06:42:42 +00:00
Evan Cheng 58d1eacd80 Prevent PPC::BCC first operand, the PRED number, from being isel'd into a LI instruction. 
llvm-svn: 37790
 2007-06-29 01:25:06 +00:00
Dan Gohman 309d3d51b3 Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from 
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704
 2007-06-22 14:59:07 +00:00
Chris Lattner 3e21eb7fd7 Fix a bug which caused us to never be able to use signed comparisons for 
equality comparisons of a constant.  This allows us to codegen the 'sintzero'
loop in PR1288 as:

LBB1_1: ;cond_next
        li r4, 0
        addi r2, r2, 1
        stw r4, 0(r3)
        addi r3, r3, 4
        cmpwi cr0, r2, -1
        bne cr0, LBB1_1 ;cond_next

instead of:

LBB1_1: ;cond_next
        addi r2, r2, 1
        li r4, 0
        xoris r5, r2, 65535
        stw r4, 0(r3)
        addi r3, r3, 4
        cmplwi cr0, r5, 65535
        bne cr0, LBB1_1 ;cond_next

This implements CodeGen/PowerPC/compare-simm.ll, and also cuts 74
instructions out of kc++.

llvm-svn: 35590
 2007-04-02 05:59:42 +00:00
Chris Lattner 1ef9cd400d eliminate static ctors for Statistic objects. 
llvm-svn: 32703
 2006-12-19 22:59:26 +00:00
Jim Laskey 095e6f3044 Reduce number of instructions to load 64-bit constants. 
llvm-svn: 32481
 2006-12-12 13:23:43 +00:00
Bill Wendling 9bfb1e1f29 What should be the last unnecessary <iostream>s in the library. 
llvm-svn: 32333
 2006-12-07 22:21:48 +00:00
Chris Lattner 700b873130 Detemplatize the Statistic class. The only type it is instantiated with 
is 'unsigned'.

llvm-svn: 32279
 2006-12-06 17:46:33 +00:00
Evan Cheng 20350c4025 Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 
of opcode and number of operands.

llvm-svn: 31947
 2006-11-27 23:37:22 +00:00
Chris Lattner be9377a1e3 convert PPC::BCC to use the 'pred' operand instead of separate predicate 
value and CR reg #.  This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(

llvm-svn: 31835
 2006-11-17 22:37:34 +00:00
Chris Lattner e0263794f4 rename PPC::COND_BRANCH to PPC::BCC 
llvm-svn: 31834
 2006-11-17 22:14:47 +00:00
Chris Lattner 8c6a41ea12 start using PPC predicates more consistently. 
llvm-svn: 31833
 2006-11-17 22:10:59 +00:00
Chris Lattner 6f5840c409 add patterns for ppc32 preinc stores. ppc64 next. 
llvm-svn: 31775
 2006-11-16 00:41:37 +00:00
Chris Lattner 474b5b7c95 fix ldu/stu jit encoding. Swith 64-bit preinc load instrs to use memri 
addrmodes.

llvm-svn: 31757
 2006-11-15 19:55:13 +00:00
Chris Lattner b542925b22 remove a ton of custom selection logic no longer needed 
llvm-svn: 31733
 2006-11-14 18:43:11 +00:00
Chris Lattner c5102bfc7c allow the offset of a preinc'd load to be the low-part of a global. This 
produces this clever code:

_millisecs:
        lis r2, ha16(_Time.1182)
        lwzu r3, lo16(_Time.1182)(r2)
        lwz r2, 4(r2)
        addic r4, r2, 1
        addze r3, r3
        blr

instead of this:

_millisecs:
        lis r2, ha16(_Time.1182)
        la r3, lo16(_Time.1182)(r2)
        lwz r2, lo16(_Time.1182)(r2)
        lwz r3, 4(r3)
        addic r4, r3, 1
        addze r3, r2
        blr

for:

long %millisecs() {
        %tmp = load long* %Time.1182            ; <long> [#uses=1]
        %tmp1 = add long %tmp, 1                ; <long> [#uses=1]
        ret long %tmp1
}

llvm-svn: 31673
 2006-11-11 04:53:30 +00:00
Chris Lattner c9fa36d706 implement preinc support for r+i loads on ppc64 
llvm-svn: 31654
 2006-11-10 23:58:45 +00:00
Chris Lattner ce6455489a add an initial cut at preinc loads for ppc32. This is broken for ppc64 
(because the 64-bit reg target versions aren't implemented yet), doesn't
support r+r addr modes, and doesn't handle stores, but it works otherwise. :)

This is disabled unless -enable-ppc-preinc is passed to llc for now.

llvm-svn: 31621
 2006-11-10 02:08:47 +00:00
Evan Cheng 6cd0909da7 Match tblegen changes. 
llvm-svn: 31571
 2006-11-08 20:34:28 +00:00
Chris Lattner a801fcedd3 Refactor all the addressing mode selection stuff into the isel lowering 
class, where it can be used for preinc formation.

llvm-svn: 31536
 2006-11-08 02:15:41 +00:00
Reid Spencer de46e48420 For PR786: 
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.

llvm-svn: 31380
 2006-11-02 20:25:50 +00:00
Chris Lattner 3e36e07db2 fix miscompilation of llvm.isunordered, where we branched on the opposite 
condition.  This fixes miscompilation of Olden/bh and many others.

llvm-svn: 31301
 2006-10-30 23:02:25 +00:00
Nate Begeman d31efd190f Fold AND and ROTL more often 
llvm-svn: 30577
 2006-09-22 05:01:56 +00:00
Chris Lattner da9b1a9322 Improve PPC64 equality comparisons like PPC32 comparisons. 
llvm-svn: 30510
 2006-09-20 04:33:27 +00:00
Chris Lattner aa3926b7ea Two improvements: 
1. Codegen this comparison:
     if (X == 0x8000)

as:

        cmplwi cr0, r3, 32768
        bne cr0, LBB1_2 ;cond_next

instead of:

        lis r2, 0
        ori r2, r2, 32768
        cmpw cr0, r3, r2
        bne cr0, LBB1_2 ;cond_next


2. Codegen this comparison:
      if (X == 0x12345678)

as:

        xoris r2, r3, 4660
        cmplwi cr0, r2, 22136
        bne cr0, LBB1_2 ;cond_next

instead of:

        lis r2, 4660
        ori r2, r2, 22136
        cmpw cr0, r3, r2
        bne cr0, LBB1_2 ;cond_next

llvm-svn: 30509
 2006-09-20 04:25:47 +00:00
Chris Lattner 3d27be1333 s|llvm/Support/Visibility.h|llvm/Support/Compiler.h| 
llvm-svn: 29911
 2006-08-27 12:54:02 +00:00
Evan Cheng c3acfc0b10 Do not use getTargetNode() and SelectNodeTo() which takes more than 3 
SDOperand arguments. Use the variants which take an array and number instead.

llvm-svn: 29907
 2006-08-27 08:14:06 +00:00
Evan Cheng 34b70eea5c SelectNodeTo now returns a SDNode*. 
llvm-svn: 29901
 2006-08-26 08:00:10 +00:00
Evan Cheng 61413a3d72 Select() no longer require Result operand by reference. 
llvm-svn: 29898
 2006-08-26 05:34:46 +00:00
Evan Cheng ab8297f92d Match tblgen changes. 
llvm-svn: 29895
 2006-08-26 01:07:58 +00:00
Chris Lattner bc485fdc4c Fix PowerPC/2006-08-15-SelectionCrash.ll and simplify selection code. 
llvm-svn: 29715
 2006-08-15 23:48:22 +00:00
Evan Cheng bd1c5a8fb8 Match tablegen changes. 
llvm-svn: 29604
 2006-08-11 09:08:15 +00:00
Chris Lattner c24a1d3093 Start eliminating temporary vectors used to create DAG nodes. Instead, pass 
in the start of an array and a count of operands where applicable.  In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap.  In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.

I updated a lot of code calling getNode that takes a vector, but ran out of
time.  The rest of the code should be updated, and these methods should be
removed.

We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.

It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.

llvm-svn: 29566
 2006-08-08 02:23:42 +00:00
Evan Cheng b9d34bd098 Match tablegen isel changes. 
llvm-svn: 29549
 2006-08-07 22:28:20 +00:00
Evan Cheng b572401bea Remove InFlightSet hack. No longer needed. 
llvm-svn: 29373
 2006-07-28 00:47:19 +00:00
Evan Cheng f300896420 Remove NodeDepth 
llvm-svn: 29338
 2006-07-27 06:40:15 +00:00
Chris Lattner 2f8c2d8ef2 shrink libllvmgcc.dylib another 25K 
llvm-svn: 28971
 2006-06-28 22:00:36 +00:00
Chris Lattner ca9c488528 Don't match 64-bit bitfield inserts into rlwimi's. todo add rldimi. :) 
llvm-svn: 28944
 2006-06-27 21:08:52 +00:00
Chris Lattner f882c54505 Fix ppc64 jump tables 
llvm-svn: 28941
 2006-06-27 20:46:17 +00:00
Chris Lattner 9a40cca40f Fix variable shadowing issue 
llvm-svn: 28922
 2006-06-27 00:10:13 +00:00
Chris Lattner 97b3da1519 Implement a bunch of 64-bit cleanliness work. With this, treeadd builds (but 
doesn't work right).

llvm-svn: 28921
 2006-06-27 00:04:13 +00:00
Chris Lattner b055c8737f Work around a nasty tblgen bug where it doesn't add operands for varargs 
nodes correctly.

llvm-svn: 28745
 2006-06-10 01:15:02 +00:00
Chris Lattner 1fbb0d38c7 Fix build failure of povray 
llvm-svn: 28473
 2006-05-25 18:06:16 +00:00
Chris Lattner 630bbcef8d Fix Benchmarks/MallocBench/cfrac 
llvm-svn: 28471
 2006-05-25 16:54:16 +00:00
Evan Cheng 4af59dac0b Assert if InflightSet is not cleared after instruction selecting a BB. 
llvm-svn: 28459
 2006-05-25 00:24:28 +00:00
Evan Cheng 1a8e74d113 Clear HandleMap and ReplaceMap after instruction selection. Or it may cause 
non-deterministic behavior.

llvm-svn: 28454
 2006-05-24 20:46:25 +00:00
Chris Lattner eb755fc1b3 Make PPC call lowering more aggressive, making the isel matching code simple 
enough to be autogenerated.

llvm-svn: 28354
 2006-05-17 19:00:46 +00:00
Chris Lattner b1e9e37c58 Switch PPC over to a call-selection model where the lowering code creates 
the copyto/fromregs instead of making the PPCISD::CALL selection code create
them.  This vastly simplifies the selection code, and moves the ABI handling
parts into one place.

llvm-svn: 28346
 2006-05-17 06:01:33 +00:00
Chris Lattner f058f5aef1 implement passing/returning vector regs to calls, at least non-varargs calls. 
llvm-svn: 28341
 2006-05-16 23:54:25 +00:00
Chris Lattner a296339c87 Fix PowerPC/2006-05-12-rlwimi-crash.ll 
Nate, please verify that if InsertMask is 0, rlwimi shouldn't be used.
This fixes the crash and causes no PPC testsuite regressions.

llvm-svn: 28243
 2006-05-12 16:29:37 +00:00
Nate Begeman 9b6d4c2968 Fold more shifts into inserts, and update the README 
llvm-svn: 28168
 2006-05-08 17:38:32 +00:00
Nate Begeman dc996b3f6c Update some stuff now that the new rlwimi code has gone in 
llvm-svn: 28162
 2006-05-08 02:52:38 +00:00
Nate Begeman 1333cead5b New rlwimi implementation, which is superior to the old one. There are 
still a couple missed optimizations, but we now generate all the possible
rlwimis for multiple inserts into the same bitfield.  More regression tests
to come.

llvm-svn: 28156
 2006-05-07 00:23:38 +00:00
Nate Begeman 4ca2ea5b43 JumpTable support! What this represents is working asm and jit support for 
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947
 2006-04-22 18:53:45 +00:00
Chris Lattner 0a3d1bbca4 Add VRRC select support 
llvm-svn: 27543
 2006-04-08 22:45:08 +00:00
Chris Lattner 6961fc76bb Codegen vector predicate compares. 
llvm-svn: 27151
 2006-03-26 10:06:40 +00:00
Chris Lattner 5d70a7c4a5 #include Intrinsics.h into all dag isels 
llvm-svn: 27109
 2006-03-25 06:47:10 +00:00
Chris Lattner f2286d5917 Like the comment says, prefer to use the implicit add done by [r+r] addressing 
modes than emitting an explicit add and using a base of r0.  This implements
Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll

llvm-svn: 27068
 2006-03-24 17:58:06 +00:00
Chris Lattner 77373d1bea Add support for "ri" addressing modes where the immediate is a 14-bit field 
which is shifted left two bits before use.  Instructions like STD use this
addressing mode.

llvm-svn: 26942
 2006-03-22 05:26:03 +00:00
Chris Lattner bda7310ef7 With Evan's latest tblgen patch, this code is obsolete, thanks Evan! 
llvm-svn: 26917
 2006-03-21 06:37:40 +00:00
Chris Lattner c8b16d00b9 Handle constant addresses more efficiently, folding the low bits into the 
disp field of the load/store if possible.  This compiles
CodeGen/PowerPC/load-constant-addr.ll to:

_test:
        lis r2, 2838
        lfs f1, 26848(r2)
        blr

instead of:

_test:
        lis r2, 2838
        ori r2, r2, 26848
        lfs f1, 0(r2)
        blr

llvm-svn: 26908
 2006-03-20 22:38:22 +00:00
Chris Lattner eda030da04 reenable this hack, the tblgen version isn't quite ready 
llvm-svn: 26902
 2006-03-20 17:54:43 +00:00
Evan Cheng 89f3cff0f5 Use tblgen'd VECTOR_SHUFFLE selection code. 
llvm-svn: 26900
 2006-03-20 08:14:16 +00:00
Chris Lattner a9a1313386 Add support for generating vspltw, instead of a vperm instruction with a 
constant pool load.  This generates significantly nicer code for splats.

When tblgen gets bugfixed, we can remove the custom selection code.

llvm-svn: 26898
 2006-03-20 06:51:10 +00:00
Nate Begeman bb01d4f272 Remove BRTWOWAY* 
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.

llvm-svn: 26814
 2006-03-17 01:40:33 +00:00
Chris Lattner 1678a6c477 Save/restore VRSAVE once per function, not once per block. 
llvm-svn: 26793
 2006-03-16 18:25:23 +00:00
Chris Lattner ab1ed2aa96 Fix an off by one error that caused PPC LLC failures last night. 
llvm-svn: 26758
 2006-03-14 17:56:49 +00:00
Evan Cheng 2dd2c652b2 Added getTargetLowering() to TargetMachine. Refactored targets to support this. 
llvm-svn: 26742
 2006-03-13 23:20:37 +00:00
Chris Lattner 02e2c18c9c For functions that use vector registers, save VRSAVE, mark used 
registers, and update it on entry to each function, then restore it on exit.

This compiles:

void func(vfloat *a, vfloat *b, vfloat *c) {
        *a = *b * *c + *c;
}

to this:

_func:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r5
        lvx v1, 0, r4
        vmaddfp v0, v1, v0, v0
        stvx v0, 0, r3
        mtspr 256, r2
        blr

GCC produces this (which has additional stack accesses):

_func:
        mfspr r0,256
        stw r0,-4(r1)
        oris r0,r0,0xc000
        mtspr 256,r0
        lvx v0,0,r5
        lvx v1,0,r4
        lwz r12,-4(r1)
        vmaddfp v0,v0,v1,v0
        stvx v0,0,r3
        mtspr 256,r12
        blr

llvm-svn: 26733
 2006-03-13 21:52:10 +00:00
Chris Lattner 51348c5f27 Several big changes: 
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
   type instead of a table in the .cpp file.  Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
   algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
   accurately.

llvm-svn: 26719
 2006-03-12 09:13:49 +00:00
Chris Lattner 543832d39d Change the interface for getting a target HazardRecognizer to be more clean. 
llvm-svn: 26608
 2006-03-08 04:25:59 +00:00
Chris Lattner 2cab13573c Implement a very very simple hazard recognizer for LSU rejects and ctr set/read 
flushes

llvm-svn: 26587
 2006-03-07 06:32:48 +00:00
Chris Lattner 60a60f4b1e Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668. 
llvm-svn: 26450
 2006-03-01 07:14:48 +00:00
Chris Lattner a1ec1ddd59 Implement selection of inline asm memory operands 
llvm-svn: 26348
 2006-02-24 02:13:12 +00:00
Nate Begeman 5965bd19f8 kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC 
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

llvm-svn: 26255
 2006-02-17 05:43:56 +00:00
Evan Cheng 42c01c8d39 If the false case is the current basic block, then this is a self loop. 
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop.  Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.

Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.

llvm-svn: 26231
 2006-02-16 08:27:56 +00:00
Evan Cheng d1b82d8db0 Match getTargetNode() changes (now return SDNode* instead of SDOperand). 
llvm-svn: 26085
 2006-02-09 07:17:49 +00:00
Evan Cheng 6dc90ca172 Change Select() from 
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);

llvm-svn: 26067
 2006-02-09 00:37:58 +00:00
Evan Cheng bfa4b7cc75 Complex pattern isel code shouldn't select nodes. 
llvm-svn: 26010
 2006-02-05 08:45:01 +00:00
Evan Cheng 54cb1833a4 Use SelectRoot() as entry of any tblgen based isel. 
llvm-svn: 25997
 2006-02-05 06:46:41 +00:00
Chris Lattner f424a66524 Use PPCISD::CALL instead of ISD::CALL 
llvm-svn: 25717
 2006-01-27 23:34:02 +00:00
Chris Lattner de02d7727f Add explicit #includes of <iostream> 
llvm-svn: 25515
 2006-01-22 23:41:00 +00:00
Chris Lattner 5bd514d7b0 Use the default impl of DYNAMIC_STACKALLOC, allowing us to delete some code. 
llvm-svn: 25334
 2006-01-15 09:02:48 +00:00
Chris Lattner 1014b38404 these cases are autogenerated 
llvm-svn: 25238
 2006-01-12 02:01:45 +00:00
Chris Lattner 44416f92f1 remove dead code 
llvm-svn: 25237
 2006-01-12 01:54:15 +00:00
Chris Lattner 20c88dfd1b Fix a compile crash building MultiSource/Applications/d with the new front-end. 
The PPC backend was generating random shift counts in this case, due to an
uninitialized variable.

llvm-svn: 25114
 2006-01-05 18:32:49 +00:00
Nate Begeman 9aea6e4691 Fix one of the things in the todo file, and get a bit closer to folding 
constant offsets from statics into the address arithmetic.

llvm-svn: 24999
 2005-12-24 01:00:15 +00:00
Nate Begeman b11b8e44fa Pattern-match return. Includes gross hack! 
llvm-svn: 24874
 2005-12-20 00:26:01 +00:00