e056d1077e
Allow the aggressive anti-dep breaker to process the same region multiple times. This is necessary because new anti-dependencies are exposed when "current" ones are broken.
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llvm-svn: 85166
2009-10-26 22:31:16 +00:00
661ea989e9
Define virtual destructor in *.cpp file.
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llvm-svn: 85146
2009-10-26 19:41:00 +00:00
de11f36ab7
Add aggressive anti-dependence breaker. Currently it is not the default for any target. Enable with -break-anti-dependencies=all.
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llvm-svn: 85145
2009-10-26 19:32:42 +00:00
8370485db9
Break anti-dependence breaking out into its own class.
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llvm-svn: 85127
2009-10-26 16:59:04 +00:00
974e12b2d3
Remove includes of Support/Compiler.h that are no longer needed after the
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VISIBILITY_HIDDEN removal.
llvm-svn: 85043
2009-10-25 06:57:41 +00:00
02d5f77d26
Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
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Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
llvm-svn: 85042
2009-10-25 06:33:48 +00:00
02ad4cb32e
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
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llvm-svn: 84911
2009-10-22 23:19:17 +00:00
682a2d154a
Revert r84658 and r84691. They were causing llvm-gcc bootstrap to fail.
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llvm-svn: 84727
2009-10-21 01:44:44 +00:00
4388beb884
Respect src register allocation requirements when breaking anti-dependencies. Remove some dead code.
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llvm-svn: 84691
2009-10-20 22:50:43 +00:00
baf6dd26ea
Checkpoint more aggressive anti-dependency breaking for post-ra scheduler.
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llvm-svn: 84658
2009-10-20 19:54:44 +00:00
007ceb4603
Change createPostRAScheduler so it can be turned off at llc -O1.
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llvm-svn: 84273
2009-10-16 21:06:15 +00:00
8b614768f8
If post-alloc scheduler is not enabled, it should return false, not true.
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llvm-svn: 84248
2009-10-16 06:10:34 +00:00
4c98efb917
Add debugging output.
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llvm-svn: 84011
2009-10-13 19:16:03 +00:00
26e9b89b7c
Fix a missing initialization of PostRAScheduler's AA member.
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llvm-svn: 83695
2009-10-10 00:15:38 +00:00
87b02d5bbc
Factor out LiveIntervalAnalysis' code to determine whether an instruction
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is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.
This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.
llvm-svn: 83687
2009-10-09 23:27:56 +00:00
3b008a3a65
Fix a use-after-free in post-ra-scheduling.
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MI->addOperand invalidates references to it's operands, avoid touching
the operand after a new one was added.
llvm-svn: 83249
2009-10-02 15:59:52 +00:00
d725159d9d
All callee-saved registers are live-out of a return block.
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llvm-svn: 83223
2009-10-01 23:28:47 +00:00
1cc6dd97da
Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
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llvm-svn: 83218
2009-10-01 22:19:57 +00:00
9a051a5922
Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.
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llvm-svn: 83215
2009-10-01 21:46:35 +00:00
be3039e776
Use MachineFrameInfo.getPristineRegs() to determine which callee-saved registers are available for anti-dependency breaking. Some cleanup.
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llvm-svn: 83208
2009-10-01 19:45:32 +00:00
4fb2891396
Observe hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. Do not change
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operands of instructions with these properties while breaking anti-dep.
llvm-svn: 83198
2009-10-01 08:26:23 +00:00
8ff5c19ebd
Fix integer overflow in instruction scheduling. This can happen if we have
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basic blocks that are so long that their size overflows a short.
Also assert that overflow does not happen in the future, as requested by Evan.
This fixes PR4401.
llvm-svn: 83159
2009-09-30 20:15:38 +00:00
17199b56b0
Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
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llvm-svn: 83122
2009-09-30 00:10:16 +00:00
0bb5af345a
Use KILL instead of IMPLICIT_DEF in LowerSubregs pass.
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llvm-svn: 83007
2009-09-28 20:32:46 +00:00
a4c98a3e34
Fix bug in kill flag updating for post-register-allocation scheduling. When the kill flag of a superreg needs to be cleared because there are one or more subregs live, we instead add implicit-defs of those subregs and leave the kill flag on the superreg. This allows us to end the live-range of the superreg without ending the live-ranges of the subregs.
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llvm-svn: 82629
2009-09-23 16:35:25 +00:00
270d0f986f
Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
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Not functionality change yet.
llvm-svn: 82273
2009-09-18 21:02:19 +00:00
e3c9d23bea
It's a bool, so treat it like one. Fixes a MSVC warning.
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llvm-svn: 81112
2009-09-06 12:10:17 +00:00
6c08cfcfa0
Create our own block initializer for kill fixups as the scheduling one wasn't doing the right thing.
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llvm-svn: 80958
2009-09-03 22:15:25 +00:00
7f6516949b
Add hidden flags to allow binary search of post-RA scheduling errors.
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llvm-svn: 80702
2009-09-01 18:34:03 +00:00
c8985204d9
Don't mark a register live at an undef use.
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llvm-svn: 80621
2009-08-31 20:47:02 +00:00
7cb103dc8b
Another stab at fixing up register kill flags after post-RA scheduling.
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llvm-svn: 80410
2009-08-29 00:11:13 +00:00
ae6bc8214a
Fixup register kills after scheduling.
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llvm-svn: 80002
2009-08-25 17:03:05 +00:00
4883d90396
convert LoopInfo.h and GraphWriter.h to use raw_ostream
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llvm-svn: 79836
2009-08-23 07:19:13 +00:00
1f8c7a76f7
Fix counting of Post-RA scheduling stalls. Improve debug output.
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llvm-svn: 78843
2009-08-12 21:47:46 +00:00
2a767c0d26
This logic was accidentally inverted in r78767.
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llvm-svn: 78773
2009-08-12 01:44:20 +00:00
f7912edba5
Factor out the code for finding an available register for use
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in breaking an anti-dependence into a separate function.
llvm-svn: 78767
2009-08-12 01:33:27 +00:00
92492f2f8e
Use DEBUG macro for debug output.
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llvm-svn: 78694
2009-08-11 17:56:42 +00:00
ebd694bb0a
Add some debug output.
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llvm-svn: 78687
2009-08-11 17:35:23 +00:00
f20236ac83
Replace DOUT.
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llvm-svn: 78634
2009-08-11 01:44:26 +00:00
6021b4dccc
Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets.
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llvm-svn: 78563
2009-08-10 15:55:25 +00:00
0402315d41
Use setPreservesAll and setPreservesCFG in CodeGen passes.
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llvm-svn: 77754
2009-07-31 23:37:33 +00:00
7667332899
inline the global 'getInstrOperandRegClass' function into its callers
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now that TargetOperandInfo does the heavy lifting.
llvm-svn: 77508
2009-07-29 21:36:49 +00:00
fbcc663cbf
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
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This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
llvm-svn: 75640
2009-07-14 16:55:14 +00:00
56d0659726
assert(0) -> LLVM_UNREACHABLE.
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Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
llvm-svn: 75379
2009-07-11 20:10:48 +00:00
1ff2727c95
Move getInstrOperandRegClass from the scheduler to TargetInstrInfo.
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llvm-svn: 70950
2009-05-05 00:30:09 +00:00
51856173c8
Fix pr3954. The register scavenger asserts for inline assembly with
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register destinations that are tied to source operands. The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).
llvm-svn: 68714
2009-04-09 17:16:43 +00:00
be69d60d54
Add parentheses to pacify gcc-4.3.
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llvm-svn: 66653
2009-03-11 09:04:34 +00:00
64613aceed
Fix a post-RA scheduling liveness bug. When a basic block is being
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scheduled in multiple regions, liveness data used by the
anti-dependence breaker is carried from one region to the next, however
the information reflects the state of the instructions before scheduling.
After scheduling, there may be new live range overlaps. Handle this by
pessimizing the liveness data carried between regions to the point where
it will be conservatively correct now matter how the earlier region is
scheduled. This fixes a miscompilation in 176.gcc with the post-RA
scheduler enabled.
llvm-svn: 66558
2009-03-10 18:10:43 +00:00
dfaf646c34
When scheduling a block in parts, keep track of the overall
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instruction index across each part. Instruction indices are used
to make live range queries, and live ranges can extend beyond
scheduling region boundaries.
Refactor the ScheduleDAGSDNodes class some more so that it
doesn't have to worry about this additional information.
llvm-svn: 64288
2009-02-11 04:27:20 +00:00
b3dbb21df1
Consider any instruction that modifies the stack pointer to be
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a scheduling region boundary. This isn't necessary for
correctness; it helps with compile time, as it avoids the need
for data- and anti-dependencies from all spills and reloads on
the stack-pointer modification.
llvm-svn: 64255
2009-02-10 23:29:38 +00:00
David Goodwin