ec6d7c945d
Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names.
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llvm-svn: 85381
2009-10-28 06:55:03 +00:00
4a609f3cef
Use fconsts and fconstd to materialize small fp constants.
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llvm-svn: 85362
2009-10-28 01:44:26 +00:00
854530a7dd
Most of the NEON shuffle instructions do not support 64-bit element types.
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llvm-svn: 84785
2009-10-21 21:36:27 +00:00
786b15fe12
Match more patterns to movt.
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llvm-svn: 84751
2009-10-21 08:15:52 +00:00
3301207a15
Random #include pruning.
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llvm-svn: 84632
2009-10-20 11:44:38 +00:00
419160bd79
Revert svn r80498 and replace it with a different solution. The only problem
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I can see with the original code was that I forgot that this runs after
type legalization and hence the result type will always be i32. (Custom
legalization of EXTRACT_VECTOR_ELT is only enabled for vector types with
8- and 16-bit elements.)
Regarding the FIXME comment: any information about sign and zero-extension
should be captured by separate extension operations. The DAG combiner should
handle those to produce either VGETLANEu or VGETLANEs, and that seems to be
working now. If there are cases that we're missing, let me know.
llvm-svn: 84218
2009-10-15 23:12:05 +00:00
b62d160b3c
More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics
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by creating TargetConstants during instruction selection instead of during
legalization.
llvm-svn: 84042
2009-10-13 22:29:24 +00:00
1fdbe1152d
NEON VLD/VST are now fully implemented. For operations that expand to
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multiple instructions, the expansion is done during selection so there is
no need to do anything special during legalization.
llvm-svn: 84036
2009-10-13 21:55:24 +00:00
75b59fb055
Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar)
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and register spills.
llvm-svn: 83435
2009-10-07 00:06:35 +00:00
32a47ea7b6
getFunctionAlignment should return log2 alignment.
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llvm-svn: 83242
2009-10-02 06:57:25 +00:00
29a44df5f8
ARM does not support offset folding (yet). Disable it for now.
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This fixes PR5031. Unfortunately, there is no small testcase :(
llvm-svn: 82643
2009-09-23 19:04:09 +00:00
9827ad39a7
Fix PR4926. When target hook EmitInstrWithCustomInserter() insert new basic blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks.
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llvm-svn: 82311
2009-09-19 09:51:03 +00:00
270d0f986f
Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
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Not functionality change yet.
llvm-svn: 82273
2009-09-18 21:02:19 +00:00
5d8cfb217c
Expand vector floating-point conversions not supported by NEON.
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llvm-svn: 82074
2009-09-16 20:20:44 +00:00
6cc46577f4
Expand some more vector operations not supported by Neon.
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llvm-svn: 81969
2009-09-16 00:32:15 +00:00
4ed397c141
Neon does not support vector divide or remainder. Expand them.
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llvm-svn: 81966
2009-09-16 00:17:28 +00:00
194a2518e5
Expand all v2f64 arithmetic operations for Neon.
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Radar 7200803. (This should also fix the
SingleSource/UnitTests/Vector/sumarray-dbl test.)
llvm-svn: 81959
2009-09-15 23:55:57 +00:00
a2e8333eed
Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS.
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See the bug report for details.
llvm-svn: 81397
2009-09-09 23:14:54 +00:00
7697d37777
Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's.
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llvm-svn: 81262
2009-09-08 22:51:43 +00:00
1b38952c99
Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172.
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llvm-svn: 80904
2009-09-03 07:04:02 +00:00
68c5f477fa
Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.
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llvm-svn: 80773
2009-09-02 08:44:58 +00:00
d7797754d4
Add support for generating code for vst{234}lane intrinsics.
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llvm-svn: 80707
2009-09-01 18:51:56 +00:00
da9817cddd
Generate code for vld{234}_lane intrinsics.
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llvm-svn: 80656
2009-09-01 04:26:28 +00:00
20eac92d88
Clean up LSDA name generation and use for SJLJ exception handling. This
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makes an eggregious hack somewhat more palatable. Bringing the LSDA forward
and making it a GV available for reference would be even better, but is
beyond the scope of what I'm looking to solve at this point.
Objective C++ code could generate function names that broke the previous
scheme. This fixes that.
llvm-svn: 80649
2009-09-01 01:57:56 +00:00
eab572a8ff
EXTRACT_VECTOR_ELEMENT can have result type different from element type.
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Remove the assertion and generalize the code for ARM NEON stuff.
llvm-svn: 80498
2009-08-30 17:14:54 +00:00
ece642a54c
Do not assert on too wide splats we don't support.
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llvm-svn: 80409
2009-08-29 00:08:18 +00:00
43b9ca6f42
Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer.
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llvm-svn: 80404
2009-08-28 23:18:09 +00:00
ba53af58f0
Hopefully the final missing part :(
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scalar_to_vector is fully legal now
llvm-svn: 80251
2009-08-27 16:25:49 +00:00
58ebae4acd
Transform float scalar_to_vector into subreg accesses.
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No idea whether this is profitable or not.
llvm-svn: 80245
2009-08-27 14:38:44 +00:00
e0636a7aed
Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations.
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The instructions can be selected directly from the intrinsics. We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.
llvm-svn: 80117
2009-08-26 17:39:53 +00:00
0f756b27ae
Expand scalar_to_vector - we don't have any isel logic for it now
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llvm-svn: 80107
2009-08-26 16:26:09 +00:00
682d8c1881
Make x86 test actually test x86 code generation. Fix the
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construct on ARM, which was breaking by coincidence, and add a similar
testcase for ARM.
llvm-svn: 79719
2009-08-22 03:13:10 +00:00
a70623102e
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations,
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now using shuffles instead of intrinsics.
llvm-svn: 79673
2009-08-21 20:54:19 +00:00
232b19c3d5
Fix some typos and use type-based isel for VZIP/VUZP/VTRN
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llvm-svn: 79625
2009-08-21 12:41:42 +00:00
9a232f46a8
Add lowering of ARM 4-element shuffles to multiple instructios via perfectshuffle-generated table.
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llvm-svn: 79624
2009-08-21 12:41:24 +00:00
ce3ff1be8a
Add nodes & dummy matchers for some v{zip,uzp,trn} instructions
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llvm-svn: 79622
2009-08-21 12:40:50 +00:00
e3046618de
Expand EXTRACT_SUBVECTOR
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llvm-svn: 79621
2009-08-21 12:40:35 +00:00
38f284f2ae
Provide vext.{16,32}
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llvm-svn: 79620
2009-08-21 12:40:21 +00:00
c32e99e3ed
Use masks not nodes for vector shuffle predicates. Provide set of 'legal' masks, so legalizer won't infinite cycle
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llvm-svn: 79619
2009-08-21 12:40:07 +00:00
32cd8550ce
Add support for Neon VEXT (vector extract) shuffles.
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This is derived from a patch by Anton Korzh. I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.
llvm-svn: 79428
2009-08-19 17:03:43 +00:00
bae6b2cca3
Reapply r79127. It was fixed by d0k.
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llvm-svn: 79136
2009-08-15 21:21:19 +00:00
d3fade656f
Revert r79127. It was causing compilation errors.
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llvm-svn: 79135
2009-08-15 21:14:01 +00:00
52d4e64711
Change allowsUnalignedMemoryAccesses to take type argument since some targets
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support unaligned mem access only for certain types. (Should it be size
instead?)
ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.
llvm-svn: 79127
2009-08-15 19:23:44 +00:00
6ddd7bcdd1
Turn on if-conversion for thumb2.
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llvm-svn: 79084
2009-08-15 07:59:10 +00:00
a6b3ce203a
Allow targets to specify their choice of calling conventions per
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libcall. Take advantage of this in the ARM backend to rectify broken
choice of CC when hard float is in effect. PIC16 may want to see if
it could be of use in MakePIC16Libcall, which works unchanged.
Patch by Sandeep!
llvm-svn: 79033
2009-08-14 20:10:52 +00:00
dc49a8d3f1
Add Thumb2 lsr hooks.
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llvm-svn: 79032
2009-08-14 20:09:37 +00:00
09c070f4ce
80 col violation.
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llvm-svn: 79026
2009-08-14 19:11:20 +00:00
6f34e278c7
Now that all the legal Neon shuffles (or at least the ones that have been
...
implemented so far) are recognized during legalization, it is easy to fall
back to the default expansion for other shuffles.
llvm-svn: 78995
2009-08-14 05:16:33 +00:00
eb54d51759
Create a new ARM-specific DAG node, VDUP, to represent a splat from a
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scalar_to_vector. Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.
llvm-svn: 78994
2009-08-14 05:13:08 +00:00
cce31f6831
During legalization, change Neon vdup_lane operations from shuffles to
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target-specific VDUPLANE nodes. This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.
llvm-svn: 78993
2009-08-14 05:08:32 +00:00
Evan Cheng