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4 Commits

Author SHA1 Message Date
Matt Arsenault 27c062932a AMDGPU: Select i16 instructions to VOP3 forms 
These were selecting directly to the VOP2 form instead
of VOP3 like the i32 instructions. Fixes regressions in
future commits where an immediate isn't folded because it was
initially used for the second operand.

Because uniform 16-bit operations are promoted to i32, it's
difficult to get a simple testcase where this matters. Fold
failures in SIFoldOperands here tend to be hidden by commute
and fold in SIShrinkInstructions.

llvm-svn: 289189
 2016-12-09 06:19:12 +00:00
Tom Stellard 115a61560e AMDGPU: Add VI i16 support 
Patch By: Wei Ding

Differential Revision: https://reviews.llvm.org/D18049

llvm-svn: 286464
 2016-11-10 16:02:37 +00:00
Tom Stellard 2d2d33f1dc Revert "AMDGPU: Add VI i16 support" 
This reverts commit r285939 and r285948.  These broke some conformance tests.

llvm-svn: 285995
 2016-11-04 13:06:34 +00:00
Tom Stellard 2b3379cdff AMDGPU: Add VI i16 support 
Patch By: Wei Ding

Differential Revision: https://reviews.llvm.org/D18049

llvm-svn: 285939
 2016-11-03 17:13:50 +00:00