8a63cb9044
AMDGPU: Change how exp is printed
...
This is an improvement over a long list of unreadable numbers.
A follow up patch will try to match how sc formats these.
llvm-svn: 288697
2016-12-05 20:31:49 +00:00
7bee6ac798
AMDGPU: Refactor exp instructions
...
Structure the definitions a bit more like the other classes.
The main change here is to split EXP with the done bit set
to a separate opcode, so we can set mayLoad = 1 so that it won't
be reordered before the other exp stores, since this has the special
constraint that if the done bit is set then this should be the last
exp in she shader.
Previously all exp instructions were inferred to have unmodeled
side effects.
llvm-svn: 288695
2016-12-05 20:23:10 +00:00
0d23ebe888
AMDGPU/SI: Implement a custom MachineSchedStrategy
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Summary:
GCNSchedStrategy re-uses most of GenericScheduler, it's just uses
a different method to compute the excess and critical register
pressure limits.
It's not enabled by default, to enable it you need to pass -misched=gcn
to llc.
Shader DB stats:
32464 shaders in 17874 tests
Totals:
SGPRS: 1542846 -> 1643125 (6.50 %)
VGPRS: 1005595 -> 904653 (-10.04 %)
Spilled SGPRs: 29929 -> 27745 (-7.30 %)
Spilled VGPRs: 334 -> 352 (5.39 %)
Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per thread
Code Size: 36688188 -> 37034900 (0.95 %) bytes
LDS: 1913 -> 1913 (0.00 %) blocks
Max Waves: 254101 -> 265125 (4.34 %)
Wait states: 0 -> 0 (0.00 %)
Totals from affected shaders:
SGPRS: 1338220 -> 1438499 (7.49 %)
VGPRS: 886221 -> 785279 (-11.39 %)
Spilled SGPRs: 29869 -> 27685 (-7.31 %)
Spilled VGPRs: 334 -> 352 (5.39 %)
Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per thread
Code Size: 34315716 -> 34662428 (1.01 %) bytes
LDS: 1551 -> 1551 (0.00 %) blocks
Max Waves: 188127 -> 199151 (5.86 %)
Wait states: 0 -> 0 (0.00 %)
Reviewers: arsenm, mareko, nhaehnle, MatzeB, atrick
Subscribers: arsenm, kzhuravl, llvm-commits
Differential Revision: https://reviews.llvm.org/D23688
llvm-svn: 279995
2016-08-29 19:42:52 +00:00
9112758077
AMDGPU/SI: Add latency for export instructions
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Reviewers: arsenm, nhaehnle
Subscribers: nhaehnle, arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D18599
llvm-svn: 265708
2016-04-07 18:30:05 +00:00
df3a20cd80
AMDGPU: Add a shader calling convention
...
This makes it possible to distinguish between mesa shaders
and other kernels even in the presence of compute shaders.
Patch By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Differential Revision: http://reviews.llvm.org/D18559
llvm-svn: 265589
2016-04-06 19:40:20 +00:00
46dadbfab2
AMDGPU/SI: Fix a GPU hang with POS_W_FLOAT enabled
...
Reviewers: tstellarAMD, arsenm
Subscribers: arsenm
Differential Revision: http://reviews.llvm.org/D16037
llvm-svn: 257625
2016-01-13 17:23:20 +00:00
774c0d689f
AMDGPU/SI: Add tests for non-void functions and InitialPSInputAddr
...
Reviewers: tstellarAMD, arsenm
Differential Revision: http://reviews.llvm.org/D16036
llvm-svn: 257624
2016-01-13 17:23:15 +00:00
Matt Arsenault