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17771 Commits

Author SHA1 Message Date
Akira Hatanaka d1465bd68b Fix data layout string. i64 is aligned to 64 bit boundaries. 
llvm-svn: 131642
 2011-05-19 17:21:09 +00:00
Stuart Hastings b476b0cc9f Revise MOVSX16rr8/MOVZX16rr8 (and rm variants) to no longer be 
pseudos.  rdar://problem/8614450

llvm-svn: 131641
 2011-05-19 16:59:50 +00:00
Cameron Zwarich 9eb5a410bd Use the correct register class for Cell varargs spilling. This fixes all of the 
verifier failures in the CodeGen/CellSPU tests.

llvm-svn: 131631
 2011-05-19 04:44:19 +00:00
Mon P Wang 6d9e1c7c2e Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for this change. 
llvm-svn: 131630
 2011-05-19 04:15:07 +00:00
Cameron Zwarich 41025dc95b Make CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll pass with the verifier. 
llvm-svn: 131627
 2011-05-19 03:11:06 +00:00
Cameron Zwarich dadd73390f Fix PR8828 by removing the explicit def in MovePCToLR as well as the pointless 
piclabel operand. The operand in the tablegen definition doesn't actually turn
into an MI operand, so it just confuses anything checking the TargetInstrDesc
for the number of operands. It suffices to just have an implicit def of LR.

llvm-svn: 131626
 2011-05-19 02:56:28 +00:00
Cameron Zwarich 58eafde58b Reuse the TargetInstrDesc. 
llvm-svn: 131625
 2011-05-19 02:56:23 +00:00
Cameron Zwarich 00b780e280 Correctly constrain a register class when computing frame offsets, as the Thumb2 
add instruction takes an rGPR. This fixes the last of PR8825.

llvm-svn: 131619
 2011-05-19 02:18:27 +00:00
Eli Friedman 6fc94dd687 Revert unintentional commit. 
llvm-svn: 131597
 2011-05-18 23:13:10 +00:00
Eli Friedman 1754a25977 More instcombine simplifications towards better debug locations. 
llvm-svn: 131596
 2011-05-18 23:11:30 +00:00
Cameron Zwarich b9bef106c6 Add missing mayLoad / mayStore flags to instruction definitions without patterns, 
which fixes all of the CodeGen/MBlaze verifier failures.

llvm-svn: 131595
 2011-05-18 23:03:10 +00:00
Cameron Zwarich 9ddeceff19 Reserve the segment registers on x86 to fix verifier failures in any code that 
uses them.

llvm-svn: 131591
 2011-05-18 22:24:48 +00:00
Cameron Zwarich 8b2e426555 Reserve r29 on Alpha. This fixes all verifier failures in CodeGen/Alpha. 
llvm-svn: 131587
 2011-05-18 21:54:32 +00:00
Tanya Lattner 1d11720ae4 Handle perfect shuffle case that generates a vrev for vectors of floats. 
Add test case.

llvm-svn: 131582
 2011-05-18 21:44:54 +00:00
Cameron Zwarich ec645bf75d Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing turned on. 
llvm-svn: 131578
 2011-05-18 21:25:14 +00:00
Johnny Chen 071634612d Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand. 
llvm-svn: 131565
 2011-05-18 20:32:41 +00:00
Chad Rosier f4e832b14e Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible. 
llvm-svn: 131560
 2011-05-18 19:59:50 +00:00
Evan Cheng 522fbfea3b Revise r131553. Just use the type of the input node and forgo the bitcast. rdar://9449159. 
llvm-svn: 131555
 2011-05-18 18:59:17 +00:00
Evan Cheng 80632c91b0 Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178 
llvm-svn: 131553
 2011-05-18 18:47:27 +00:00
Justin Holewinski bbdcd17d44 PTX: add flag to disable mad/fma selection 
Patch by Dan Bailey

llvm-svn: 131537
 2011-05-18 15:42:23 +00:00
Tanya Lattner 48b182c3a4 In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. 
Updated test case and reverted change to the PerfectShuffle Table.

llvm-svn: 131529
 2011-05-18 06:42:21 +00:00
Cameron Zwarich f9839e4257 Fix typo. 
llvm-svn: 131519
 2011-05-18 02:29:50 +00:00
Cameron Zwarich d7c55fe2ef Fix more of PR8825 by correctly using rGPR registers when lowering atomic 
compare-and-swap intrinsics.

llvm-svn: 131518
 2011-05-18 02:20:07 +00:00
Cameron Zwarich 33a67ddbd2 Actually, the address operand of the Thumb2 LDREX / STREX instructions *can* 
take r13, so we can just make it a GPR. This fixes PR8825.

llvm-svn: 131507
 2011-05-17 23:26:20 +00:00
Cameron Zwarich c5d272766f Correct a minor problem with the Thumb2 LDREX and STREX instruction encodings. They 
were marked as taking a tGPR when in reality they take an rGPR.

llvm-svn: 131506
 2011-05-17 23:11:12 +00:00
Tanya Lattner c7e291b354 vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case. 
llvm-svn: 131488
 2011-05-17 20:48:40 +00:00
Mon P Wang 6f6b44d19d Enable autodetect of popcnt 
llvm-svn: 131476
 2011-05-17 18:33:37 +00:00
Eli Friedman 7b27942fe7 Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872. 
This is r131438 with a couple small fixes.

llvm-svn: 131474
 2011-05-17 18:29:03 +00:00
Eli Friedman d000a2c26e Clean up the mess created by r131467+r131469. 
llvm-svn: 131471
 2011-05-17 18:02:22 +00:00
Stuart Hastings c65d8eda7b Revert 131467 due to buildbot complaint. 
llvm-svn: 131469
 2011-05-17 16:59:46 +00:00
Stuart Hastings 3cf5308890 Fix an obscure issue in X86_64 parameter passing: if a tiny byval is 
passed as the fifth parameter, insure it's passed correctly (in R9).
rdar://problem/6920088

llvm-svn: 131467
 2011-05-17 16:45:55 +00:00
Nadav Rotem d8edb1d5cc Fix a bug in PerformEXTRACT_VECTOR_ELTCombine. The code created an ADD SDNode 
with two different types, in cases where the index and the ptr had different
types.

llvm-svn: 131461
 2011-05-17 08:31:57 +00:00
Eric Christopher 56a42ebf15 Update comment. 
llvm-svn: 131459
 2011-05-17 08:16:14 +00:00
Eric Christopher a1d9e29552 Support XOR and AND optimization with no return value. 
Finishes off rdar://8470697

llvm-svn: 131458
 2011-05-17 08:10:18 +00:00
Eric Christopher abfe3131e3 Couple less magic numbers. 
llvm-svn: 131457
 2011-05-17 07:50:41 +00:00
Eric Christopher eb47a2a1e5 Make this code a little less magic number laden. 
llvm-svn: 131456
 2011-05-17 07:47:55 +00:00
Chris Lattner 1e81f57bf0 add a note 
llvm-svn: 131455
 2011-05-17 07:22:33 +00:00
Eli Friedman 7335e8a720 Back out r131444 and r131438; they're breaking nightly tests. I'll look into 
it more tomorrow.

llvm-svn: 131451
 2011-05-17 02:36:59 +00:00
Eli Friedman 83ba150f3a Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872. 
llvm-svn: 131438
 2011-05-17 00:13:47 +00:00
Jim Grosbach 4e983166bc Kill some dead code. 
llvm-svn: 131431
 2011-05-16 22:24:07 +00:00
Eli Friedman d4a3609d30 Remove dead code. Fix associated test to use FileCheck. 
llvm-svn: 131424
 2011-05-16 21:28:22 +00:00
Eli Friedman a4d4a0162d Make fast-isel work correctly s/uadd.with.overflow intrinsics. 
llvm-svn: 131420
 2011-05-16 21:06:17 +00:00
Rafael Espindola e90c1cb221 sets bit 0 of the function address of thumb function in .symtab 
("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)

Patch by Koan-Sin Tan!

llvm-svn: 131406
 2011-05-16 16:17:21 +00:00
Eli Friedman 8f1e11cde9 Fix a FIXME by moving the fast-isel implementation of the objectsize intrinsic from the x86 code to the generic code. 
llvm-svn: 131332
 2011-05-14 00:47:51 +00:00
Rafael Espindola df9db7ed92 Don't produce a vmovntdq if we don't have AVX support. 
llvm-svn: 131330
 2011-05-14 00:30:01 +00:00
Eli Friedman f080a57b81 Zap useless code; this hasn't done anything useful since fast-isel switched to being bottom-up (a very long time ago). 
llvm-svn: 131329
 2011-05-14 00:19:32 +00:00
Julien Lerouge 7e11f9e26d Fix a source of non determinism in FindUsedTypes, use a SetVector instead of a 
set.

rdar://9423996

llvm-svn: 131283
 2011-05-13 05:20:42 +00:00
Akira Hatanaka e50a3d16e9 Fix setting of isCommutable flag. 
llvm-svn: 131233
 2011-05-12 17:42:08 +00:00
Eric Christopher 2a9dbbbb12 Turn this into a table, this will make more sense shortly. 
Part of rdar://8470697

llvm-svn: 131200
 2011-05-11 21:44:58 +00:00
Owen Anderson b745623b71 Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan. 
llvm-svn: 131189
 2011-05-11 17:00:48 +00:00