6d9e1c7c2e
Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for this change.
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llvm-svn: 131630
2011-05-19 04:15:07 +00:00
58eafde58b
Reuse the TargetInstrDesc.
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llvm-svn: 131625
2011-05-19 02:56:23 +00:00
00b780e280
Correctly constrain a register class when computing frame offsets, as the Thumb2
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add instruction takes an rGPR. This fixes the last of PR8825.
llvm-svn: 131619
2011-05-19 02:18:27 +00:00
1d11720ae4
Handle perfect shuffle case that generates a vrev for vectors of floats.
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Add test case.
llvm-svn: 131582
2011-05-18 21:44:54 +00:00
ec645bf75d
Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing turned on.
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llvm-svn: 131578
2011-05-18 21:25:14 +00:00
071634612d
Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand.
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llvm-svn: 131565
2011-05-18 20:32:41 +00:00
522fbfea3b
Revise r131553. Just use the type of the input node and forgo the bitcast. rdar://9449159.
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llvm-svn: 131555
2011-05-18 18:59:17 +00:00
80632c91b0
Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178
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llvm-svn: 131553
2011-05-18 18:47:27 +00:00
48b182c3a4
In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32.
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Updated test case and reverted change to the PerfectShuffle Table.
llvm-svn: 131529
2011-05-18 06:42:21 +00:00
f9839e4257
Fix typo.
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llvm-svn: 131519
2011-05-18 02:29:50 +00:00
d7c55fe2ef
Fix more of PR8825 by correctly using rGPR registers when lowering atomic
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compare-and-swap intrinsics.
llvm-svn: 131518
2011-05-18 02:20:07 +00:00
33a67ddbd2
Actually, the address operand of the Thumb2 LDREX / STREX instructions *can*
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take r13, so we can just make it a GPR. This fixes PR8825.
llvm-svn: 131507
2011-05-17 23:26:20 +00:00
c5d272766f
Correct a minor problem with the Thumb2 LDREX and STREX instruction encodings. They
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were marked as taking a tGPR when in reality they take an rGPR.
llvm-svn: 131506
2011-05-17 23:11:12 +00:00
c7e291b354
vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case.
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llvm-svn: 131488
2011-05-17 20:48:40 +00:00
4e983166bc
Kill some dead code.
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llvm-svn: 131431
2011-05-16 22:24:07 +00:00
e90c1cb221
sets bit 0 of the function address of thumb function in .symtab
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("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)
Patch by Koan-Sin Tan!
llvm-svn: 131406
2011-05-16 16:17:21 +00:00
b745623b71
Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan.
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llvm-svn: 131189
2011-05-11 17:00:48 +00:00
50117f8186
Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmp
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intrinsic call. This prevents it from being reordered so that it appears
*before* the setjmp intrinsic (thus making it completely useless).
<rdar://problem/9409683>
llvm-svn: 131174
2011-05-11 01:11:55 +00:00
62f1ab79ec
First cut at getting debugging support for ARM/MC/ELF/.o
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DWARF stuff also gets fixed up by ELFARMAsmBackend::ApplyFixup(),
but the offset is not guaranteed to be mod 4 == 0 as in text/data.
llvm-svn: 131137
2011-05-10 18:07:25 +00:00
92ff16b7bb
Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32
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llvm-svn: 131085
2011-05-09 17:47:27 +00:00
c132174169
Eliminate the ARM sub-register indexes that are not needed by the sources.
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Tablegen will invent its own names for these indexes, and the register file is a
bit simpler.
llvm-svn: 131059
2011-05-07 21:22:42 +00:00
1e3db02bda
Fix the non-MC encoding of pkhbt and pkhtb.
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Patch by Stephen Hines.
llvm-svn: 131045
2011-05-07 04:37:27 +00:00
2518f8376d
Make the logic for determining function alignment more explicit. No functionality change.
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llvm-svn: 131012
2011-05-06 20:34:06 +00:00
a716096677
Dead code elimination.
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llvm-svn: 130984
2011-05-06 14:56:22 +00:00
39ecf816c5
Do not emit location expression size twice.
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llvm-svn: 130854
2011-05-04 19:00:57 +00:00
f8be385c9b
Mark ultra-super-registers QQQQ as call-clobbered instead of the D sub-registers.
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LiveVariables doesn't understand that clobbering D0 and D1 completely overwrites
Q0, so if Q0 is live-in to a function, its live range will extend beyond a
function call that only clobbers D0 and D1. This shows up in the
ARM/2009-11-01-NeonMoves test case.
LiveVariables should probably implement the much stricter rules for physreg
liveness that RAFast imposes - a physreg is killed by the first use of any
alias.
llvm-svn: 130801
2011-05-03 22:31:24 +00:00
09585e1c5d
Temporarily disable use of divmod compiler-rt functions for iOS.
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llvm-svn: 130766
2011-05-03 17:33:22 +00:00
86c6e7057d
Fold ARM coprocessor intrinsics patterns into the instructions defs whenever
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it's possible.
llvm-svn: 130764
2011-05-03 17:29:29 +00:00
168c9005b5
Add a few ARM coprocessor intrinsics. Testcases included
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llvm-svn: 130763
2011-05-03 17:29:22 +00:00
6136e94897
Add an unfolded offset field to LSR's Formula record. This is used to
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model constants which can be added to base registers via add-immediate
instructions which don't require an additional register to materialize
the immediate.
llvm-svn: 130743
2011-05-03 00:46:49 +00:00
39b56b4b9f
Apparently the check for direct calls is unnecessary.
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llvm-svn: 130716
2011-05-02 20:16:33 +00:00
e02e07c3a6
80-col.
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llvm-svn: 130558
2011-04-29 23:12:01 +00:00
468dfabce0
Zap a couple now-unused functions.
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llvm-svn: 130557
2011-04-29 22:56:48 +00:00
328bad02fa
Switch to ImmLeaf (which can be used by FastISel) for a few more common ARM/Thumb2 patterns.
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llvm-svn: 130552
2011-04-29 22:48:03 +00:00
7708746c33
Add FastEmitInst_ii for the arm fast isel generator. It doesn't use it, but
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if it ever did it needs the def machinery.
llvm-svn: 130549
2011-04-29 22:07:50 +00:00
26b8ac4b8c
Some cleanup and optimize fallthrough more.
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llvm-svn: 130546
2011-04-29 21:56:31 +00:00
86caced370
Re-committing r130454, which does not in fact break anything.
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Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
rdar://problem/9338332 .
llvm-svn: 130539
2011-04-29 21:22:56 +00:00
8d46b47787
Add trunc->branch support, this won't help with clang's i8->i1 truncations
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for bools, but is a start.
llvm-svn: 130534
2011-04-29 20:02:39 +00:00
dc3e4cc5ed
MCExpr: Add FindAssociatedSection, which attempts to mirror the 'as' semantics
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that associate sections with expressions.
llvm-svn: 130517
2011-04-29 18:00:03 +00:00
e794e17524
Teach Thumb2 isel to fold and->rotr ==> ROR.
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Generalization of Nate Begeman's patch!
llvm-svn: 130502
2011-04-29 14:18:15 +00:00
1d0c25756e
use the MachineInstrBuilder operator-> to simplify some code.
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There are probably more instances of this floating around.
llvm-svn: 130474
2011-04-29 05:24:29 +00:00
9ade5e2495
Update comments and checks to match reality.
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llvm-svn: 130464
2011-04-29 00:07:20 +00:00
501d2e2c14
Whitespace.
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llvm-svn: 130463
2011-04-29 00:03:10 +00:00
517728b1ae
Revert r130454; apparently this doesn't actually work.
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llvm-svn: 130462
2011-04-28 23:55:14 +00:00
e4ecd42926
Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
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rdar://problem/9338332 .
llvm-svn: 130454
2011-04-28 23:03:25 +00:00
4f012fd0a1
Be more layout aware here and swap the successor and branch condition
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if it means we get a fallthrough.
llvm-svn: 130404
2011-04-28 16:52:09 +00:00
a98cd22d96
Let the immediate leaf pattern take transforms and switch the signed
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immediate patterns in arm to using the pattern.
Handles rdar://9299434
llvm-svn: 130386
2011-04-28 05:49:04 +00:00
3e021533cd
Teach dwarf writer to handle complex address expression for .debug_loc entries.
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This fixes clang generated blocks' variables' debug info.
Radar 9279956.
llvm-svn: 130373
2011-04-28 02:22:40 +00:00
886894cb70
Fix a bug in the case that there is no add or subtract symbol and the offset
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value is zero so it does not add a NULL expr operand.
llvm-svn: 130330
2011-04-27 21:02:27 +00:00
e3745fdcf3
Revert r130178. It turned out to be not the optimal path to emit complex location expressions.
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llvm-svn: 130326
2011-04-27 20:29:27 +00:00
Mon P Wang