b6c7704a8d
Refactor cmov selection code out to a separate function. No functionality change.
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llvm-svn: 89396
2009-11-19 21:45:22 +00:00
82adca8373
80 col violation.
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llvm-svn: 89337
2009-11-19 08:16:50 +00:00
d7cf55cd0e
Use Unified Assembly Syntax for the ARM backend.
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llvm-svn: 86494
2009-11-09 00:11:35 +00:00
d1d002a6fe
Support alignment specifier for NEON vld/vst instructions
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llvm-svn: 86404
2009-11-07 21:25:39 +00:00
b15f4a1cbd
Remove uninteresting and confusing debug output.
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llvm-svn: 86149
2009-11-05 18:47:09 +00:00
e90a4aa703
Prune unnecessary include.
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llvm-svn: 85805
2009-11-02 16:58:31 +00:00
b678a56fef
Test commit. Added '.' to the comment line.
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llvm-svn: 85255
2009-10-27 17:25:15 +00:00
0f55e9ce2e
Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad.
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llvm-svn: 84813
2009-10-22 00:40:00 +00:00
786b15fe12
Match more patterns to movt.
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llvm-svn: 84751
2009-10-21 08:15:52 +00:00
ad03cf02f6
Remove unused variables to fix build warning.
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llvm-svn: 84144
2009-10-14 21:40:45 +00:00
c350cdf3b3
Refactor code to select NEON VST intrinsics.
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llvm-svn: 84122
2009-10-14 18:32:29 +00:00
12b4799787
Refactor code to select NEON VLD intrinsics.
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llvm-svn: 84117
2009-10-14 17:28:52 +00:00
93117bc499
More refactoring. NEON vst lane intrinsics can share almost all the code for
...
vld lane intrinsics.
llvm-svn: 84110
2009-10-14 16:46:45 +00:00
4145e3ac8d
Refactor code for selecting NEON load lane intrinsics.
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llvm-svn: 84109
2009-10-14 16:19:03 +00:00
b62d160b3c
More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics
...
by creating TargetConstants during instruction selection instead of during
legalization.
llvm-svn: 84042
2009-10-13 22:29:24 +00:00
3b51560ae4
Revise ARM inline assembly memory operands to require the memory address to
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be in a register. The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb. Radar 7137468.
llvm-svn: 84022
2009-10-13 20:50:28 +00:00
7460e0822f
Fix method name in comment, per Bob Wilson.
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llvm-svn: 84017
2009-10-13 20:25:58 +00:00
423e42b371
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
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llvm-svn: 84009
2009-10-13 18:59:48 +00:00
84e7967fae
Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.
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llvm-svn: 83600
2009-10-09 00:01:36 +00:00
c409030838
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.
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llvm-svn: 83598
2009-10-08 23:51:31 +00:00
b851eb356a
Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.
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llvm-svn: 83596
2009-10-08 23:38:24 +00:00
38ba47225a
Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.
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Also fix some copy-and-paste errors in previous changes.
llvm-svn: 83590
2009-10-08 22:53:57 +00:00
cf54e934f8
Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
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llvm-svn: 83585
2009-10-08 22:27:33 +00:00
c2728f44a9
Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.
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llvm-svn: 83568
2009-10-08 18:56:10 +00:00
fac9476589
Clean up some unnecessary initializations.
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llvm-svn: 83566
2009-10-08 18:52:56 +00:00
4facd965bd
Clean up a comment (indentation was wrong).
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llvm-svn: 83565
2009-10-08 18:51:31 +00:00
b6b0ab6117
Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.
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llvm-svn: 83526
2009-10-08 05:18:18 +00:00
71387b4b2f
Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.
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llvm-svn: 83518
2009-10-08 00:28:28 +00:00
d4f5670096
Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.
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llvm-svn: 83513
2009-10-08 00:21:01 +00:00
32cc4ec304
Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
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llvm-svn: 83508
2009-10-07 23:54:04 +00:00
5ef3c6d9f4
Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.
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llvm-svn: 83506
2009-10-07 23:39:57 +00:00
763be1a248
Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
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llvm-svn: 83502
2009-10-07 22:57:01 +00:00
e7ef4a9a6b
Add codegen support for NEON vst4 intrinsics with 128-bit vectors.
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llvm-svn: 83486
2009-10-07 20:49:18 +00:00
23464866ad
Add codegen support for NEON vst3 intrinsics with 128-bit vectors.
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llvm-svn: 83484
2009-10-07 20:30:08 +00:00
3dcb5377ef
Add codegen support for NEON vst2 intrinsics with 128-bit vectors.
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llvm-svn: 83482
2009-10-07 18:47:39 +00:00
ab3a9474d6
Add codegen support for NEON vld4 intrinsics with 128-bit vectors.
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llvm-svn: 83479
2009-10-07 18:09:32 +00:00
6bbefc2f67
Add codegen support for NEON vld3 intrinsics with 128-bit vectors.
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llvm-svn: 83471
2009-10-07 17:24:55 +00:00
99e80228a9
Rearrange code for selecting vld2 intrinsics. No functionality change.
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This is just to be more consistent with the forthcoming code for vld3/4.
llvm-svn: 83470
2009-10-07 17:23:09 +00:00
e6b778d5ff
Add codegen support for NEON vld2 operations on quad registers.
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llvm-svn: 83422
2009-10-06 22:01:59 +00:00
2dd957fff6
Pass the optimization level when constructing the ARM instruction selector.
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Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel. Radar 7250345.
llvm-svn: 82988
2009-09-28 14:30:20 +00:00
7c2b1e71c1
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
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This should be better than single load from constpool.
llvm-svn: 82948
2009-09-27 23:52:58 +00:00
32f71d714b
Rename getTargetNode to getMachineNode, for consistency with the
...
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.
llvm-svn: 82790
2009-09-25 18:54:59 +00:00
d7797754d4
Add support for generating code for vst{234}lane intrinsics.
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llvm-svn: 80707
2009-09-01 18:51:56 +00:00
da9817cddd
Generate code for vld{234}_lane intrinsics.
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llvm-svn: 80656
2009-09-01 04:26:28 +00:00
e0636a7aed
Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations.
...
The instructions can be selected directly from the intrinsics. We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.
llvm-svn: 80117
2009-08-26 17:39:53 +00:00
0939595711
Record variable debug info at ISel time directly.
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llvm-svn: 79742
2009-08-22 17:12:53 +00:00
232b19c3d5
Fix some typos and use type-based isel for VZIP/VUZP/VTRN
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llvm-svn: 79625
2009-08-21 12:41:42 +00:00
ce3ff1be8a
Add nodes & dummy matchers for some v{zip,uzp,trn} instructions
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llvm-svn: 79622
2009-08-21 12:40:50 +00:00
51c7aa04ec
Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as
...
vector shuffles. Temporarily remove the tests for these operations until the
new implementation is working.
llvm-svn: 79579
2009-08-21 00:01:42 +00:00
9a58aff837
Indentation.
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llvm-svn: 79022
2009-08-14 19:01:37 +00:00
cce31f6831
During legalization, change Neon vdup_lane operations from shuffles to
...
target-specific VDUPLANE nodes. This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.
llvm-svn: 78993
2009-08-14 05:08:32 +00:00
55f1c09e31
Push LLVMContexts through the IntegerType APIs.
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llvm-svn: 78948
2009-08-13 21:58:54 +00:00
bb2af3555c
Shrink Thumb2 movcc instructions.
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llvm-svn: 78790
2009-08-12 05:17:19 +00:00
f042eadd1e
Add missing chain operands for VLD* and VST* instructions.
...
Set "mayLoad" and "mayStore" on the load/store instructions.
llvm-svn: 78761
2009-08-12 00:49:01 +00:00
f6a9d06241
Shrinkify Thumb2 r = add sp, imm.
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llvm-svn: 78745
2009-08-11 23:00:31 +00:00
9f94459d24
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
...
the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
f24f9d9cb6
Whitespace cleanup. Remove trailing whitespace.
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llvm-svn: 78666
2009-08-11 15:33:49 +00:00
3606467709
Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to
...
match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.
llvm-svn: 78658
2009-08-11 08:52:18 +00:00
12842f9865
Use vAny type to get rid of Neon intrinsics that differed only in whether
...
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.
If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.
llvm-svn: 78646
2009-08-11 05:39:44 +00:00
733a64db57
Fix a bug where DAGCombine was producing an illegal ConstantFP
...
node after legalize, and remove the workaround code from the
ARM backend.
llvm-svn: 78615
2009-08-10 23:15:10 +00:00
53aa7a960c
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
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llvm-svn: 78610
2009-08-10 22:56:29 +00:00
f72c13bdf5
Handle the constantfp created during post-legalization dag combiner phase.
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llvm-svn: 78594
2009-08-10 20:25:59 +00:00
887d05ce9b
Use VLDM / VSTM to spill/reload 128-bit Neon registers
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llvm-svn: 78468
2009-08-08 13:35:48 +00:00
e2231070ff
Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,
...
so I generalized the class for VTRN in the .td file to handle all 3 of them.
llvm-svn: 78460
2009-08-08 06:13:25 +00:00
db46af0461
Implement Neon VTRN instructions. For now, anyway, these are selected
...
directly from the intrinsics produced by the frontend. If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.
llvm-svn: 78459
2009-08-08 05:53:00 +00:00
b972e5633f
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
...
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
llvm-svn: 78361
2009-08-07 00:34:42 +00:00
0127031c20
Implement Neon VST[234] operations.
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llvm-svn: 78330
2009-08-06 18:47:44 +00:00
488db94e7b
Neon does not actually have VLD{234}.64 instructions.
...
These operations will have to be synthesized from other instructions.
llvm-svn: 78263
2009-08-06 00:24:27 +00:00
20f79e321e
Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.
...
Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions. The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.
llvm-svn: 78136
2009-08-05 00:49:09 +00:00
f307e0bd6d
Lower CONCAT_VECTOR during legalization instead of matching it during isel.
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Add a testcase.
llvm-svn: 77992
2009-08-03 20:36:38 +00:00
e6e8289d72
Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate.
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llvm-svn: 77764
2009-08-01 01:43:45 +00:00
5aae45fb6f
Remove redundant match for frame index from imm8 addrmode, it is handled by the imm12 addrmode.
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llvm-svn: 77632
2009-07-30 22:45:52 +00:00
79c079b478
Cleanup and include code selection for some frame index cases.
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llvm-svn: 77622
2009-07-30 18:56:48 +00:00
faede73a32
Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir.
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llvm-svn: 77172
2009-07-26 23:59:01 +00:00
edb4a70325
Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come.
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llvm-svn: 77011
2009-07-24 23:12:02 +00:00
cdd405d804
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
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llvm-svn: 76919
2009-07-24 00:16:18 +00:00
e270d4a4dd
Use getTargetConstant instead of getConstant since it's meant as an constant operand.
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llvm-svn: 76803
2009-07-22 22:03:29 +00:00
1ec4396ee3
Eliminate a redudant check Eli pointed out.
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llvm-svn: 76762
2009-07-22 18:08:05 +00:00
0d8b0cf3b8
Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1.
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llvm-svn: 76520
2009-07-21 00:31:12 +00:00
802a0b576f
Use t2LDRri12 for frame index loads.
...
llvm-svn: 76424
2009-07-20 15:55:39 +00:00
f39120571b
Thumb-2 only support [base_reg + offset_reg] addressing, not [base_reg - offset_reg].
...
llvm-svn: 75789
2009-07-15 15:50:19 +00:00
b6b2530000
Move EVER MORE stuff over to LLVMContext.
...
llvm-svn: 75703
2009-07-14 23:09:55 +00:00
95bad85498
Check for PRE_INC and POST_INC.
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llvm-svn: 75683
2009-07-14 21:29:29 +00:00
4ad7797e1c
hasThumb2() does not mean we are compiling for thumb, must also check isThumb().
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llvm-svn: 75660
2009-07-14 18:48:51 +00:00
0794c6a083
Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible.
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llvm-svn: 75360
2009-07-11 07:08:13 +00:00
cd4cdd1157
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
...
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
llvm-svn: 75359
2009-07-11 06:43:01 +00:00
7591d02c84
Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit.
...
Note, we are not yet generating these instructions.
llvm-svn: 75181
2009-07-09 22:21:59 +00:00
22c2fba978
Use common code for both ARM and Thumb-2 instruction and register info.
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llvm-svn: 75067
2009-07-08 23:10:31 +00:00
e3a53c448b
Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
...
llvm-svn: 75048
2009-07-08 21:03:57 +00:00
fb8d6d5b58
Implement changes from Chris's feedback.
...
Finish converting lib/Target.
llvm-svn: 75043
2009-07-08 20:53:28 +00:00
d0611f9a37
Add Thumb2 movcc instructions.
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llvm-svn: 74946
2009-07-07 20:39:03 +00:00
b24e51e2d9
Add some more Thumb2 multiplication instructions.
...
llvm-svn: 74889
2009-07-07 01:17:28 +00:00
8ecd7eb3f7
Sign extending pre/post indexed loads.
...
llvm-svn: 74736
2009-07-02 23:16:11 +00:00
84c6cda2ef
Thumb2 pre/post indexed loads.
...
llvm-svn: 74696
2009-07-02 07:28:31 +00:00
d9c55368e7
Factor out ARM indexed load matching code.
...
llvm-svn: 74681
2009-07-02 01:23:32 +00:00
deb35afd23
Add a new addressing mode for NEON load/store instructions.
...
llvm-svn: 74658
2009-07-01 23:16:05 +00:00
a83100f687
Thumb-2 load and store double description. But nothing yet creates them.
...
llvm-svn: 74566
2009-06-30 22:50:01 +00:00
27303cde82
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
...
llvm-svn: 74543
2009-06-30 18:04:13 +00:00
b23b50d54d
Implement Thumb2 ldr.
...
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
eab9ca7ea6
Renaming for consistency.
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llvm-svn: 74368
2009-06-27 02:26:13 +00:00
Evan Cheng