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Author SHA1 Message Date
Bob Wilson da9817cddd Generate code for vld{234}_lane intrinsics. 
llvm-svn: 80656
 2009-09-01 04:26:28 +00:00
Bob Wilson 4b35448360 Generate Neon VTBL and VTBX instructions from the corresponding intrinsics. 
llvm-svn: 78835
 2009-08-12 20:51:55 +00:00
Bob Wilson 0127031c20 Implement Neon VST[234] operations. 
llvm-svn: 78330
 2009-08-06 18:47:44 +00:00
Bob Wilson 488db94e7b Neon does not actually have VLD{234}.64 instructions. 
These operations will have to be synthesized from other instructions.

llvm-svn: 78263
 2009-08-06 00:24:27 +00:00
Bob Wilson e148ceaf65 Add a new pre-allocation pass to assign adjacent registers for Neon instructions 
that have that constraint.  This is currently just assigning a fixed set of
registers, and it only handles VLDn for n=2,3,4 with DPR registers.
I'm going to expand it to handle more operations next; we can make it smarter
once everything is working correctly.

llvm-svn: 78256
 2009-08-05 23:12:45 +00:00