b7f872197a
Remove unused functions.
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llvm-svn: 111155
2010-08-16 17:18:18 +00:00
d0fcc9a818
Revert r111082. No warnings for this common pattern.
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llvm-svn: 111102
2010-08-15 10:27:23 +00:00
54194bd127
Rework how the non-sse2 memory barrier is lowered so that the
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encoding is correct for the built-in assembler.
Based on a patch from Chris.
llvm-svn: 111083
2010-08-14 21:51:50 +00:00
7c09ddf0ae
Add ATTRIBUTE_UNUSED to methods that are not supposed to be used.
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llvm-svn: 111082
2010-08-14 21:35:10 +00:00
2f6c3434ac
improve indentation
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llvm-svn: 111073
2010-08-14 17:26:09 +00:00
160be2936b
Add comments to some pattern fragments in x86
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llvm-svn: 111041
2010-08-13 20:39:01 +00:00
8d3c89e765
Revert 110491. While not wrong, it was based on a
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misanalysis and is undesirable.
llvm-svn: 111028
2010-08-13 18:43:45 +00:00
081861b6b7
Fix comment to reflect code, and remove an unused argument
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llvm-svn: 111022
2010-08-13 17:50:47 +00:00
1187e3f09b
Improve comment to make explicit why not to touch this could before JIT goes MC
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llvm-svn: 111021
2010-08-13 17:44:10 +00:00
6e5b67ccc4
Revert last patch and r110954 as I meant to.
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llvm-svn: 111001
2010-08-13 02:37:50 +00:00
5e027fe113
Revert r110954 for now, pseudo instructions can't make it through to the JIT.
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llvm-svn: 111000
2010-08-13 02:30:00 +00:00
cc20fe5937
Some small clean-up: use of pseudo instructions
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llvm-svn: 110954
2010-08-12 20:55:18 +00:00
7f704b31a9
- Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary.
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- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.
llvm-svn: 110946
2010-08-12 20:20:53 +00:00
7e1a30c0d3
Define AVX 128-bit pattern versions of SET0PS/PD.
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llvm-svn: 110937
2010-08-12 18:20:59 +00:00
1401e040eb
Fix comment order
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llvm-svn: 110898
2010-08-12 02:08:52 +00:00
7306c86886
Begin to support some vector operations for AVX 256-bit intructions. The long
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term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.
llvm-svn: 110897
2010-08-12 02:06:36 +00:00
7d7b4d1b0f
MC/X86/AsmParser: Give an explicit error message when we reject an instruction
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because it could have an ambiguous suffix.
llvm-svn: 110890
2010-08-12 00:55:42 +00:00
2ecc3bb4f7
MC/AsmParser: Push the burdon of emitting diagnostics about unmatched
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instructions onto the target specific parser, which can do a better job.
llvm-svn: 110889
2010-08-12 00:55:38 +00:00
167b9d7f30
tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl',
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target specific parsers can adapt the TargetAsmParser to this.
llvm-svn: 110888
2010-08-12 00:55:32 +00:00
9c473e46f3
Fix <rdar://problem/8282498> even if it doesn't reproduce on trunk.
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When a register is defined by a partial load:
%reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234
That load cannot be folded into an instruction using the full 64-bit register.
It would become a 64-bit load.
This is related to the recent change to have isLoadFromStackSlot return false on
a sub-register load.
llvm-svn: 110874
2010-08-11 23:08:22 +00:00
5531aa4de1
Use ISD::ADD instead of ISD::SUB with a negated constant. This
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avoids trouble if the return type of TD->getPointerSize() is
changed to something which doesn't promote to a signed type,
and is simpler anyway.
Also, use getCopyFromReg instead of getRegister to read a
physical register's value.
llvm-svn: 110835
2010-08-11 18:14:00 +00:00
ebace2248f
MCAsmParser: Add dump() hook to MCParsedAsmOperand.
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llvm-svn: 110790
2010-08-11 06:37:04 +00:00
91d61df3eb
Add AVX matching patterns to Packed Bit Test intrinsics.
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Apply the same approach of SSE4.1 ptest intrinsics but
create a new x86 node "testp" since AVX introduces
vtest{ps}{pd} instructions which set ZF and CF depending
on sign bit AND and ANDN of packed floating-point sources.
This is slightly different from what the "ptest" does.
Tests comming with the other 256 intrinsics tests.
llvm-svn: 110744
2010-08-10 23:25:42 +00:00
39f215bd33
Add AVX movnt{pd,ps,dq} 256-bit intrinsics
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llvm-svn: 110650
2010-08-10 02:49:24 +00:00
cedf23dfe5
Add AVX movmsk 256-bit intrinsics
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llvm-svn: 110648
2010-08-10 02:34:56 +00:00
85da72a88f
Support AVX 256-bit load and store intrinsics
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llvm-svn: 110645
2010-08-10 01:43:16 +00:00
b2b6b65b86
Patterns to match AVX cmp instructions
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llvm-svn: 110633
2010-08-10 00:13:20 +00:00
001d6fa174
Add matching patterns for vblend AVX intrinsics
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llvm-svn: 110630
2010-08-10 00:02:05 +00:00
b9627ee79b
Wording.
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llvm-svn: 110618
2010-08-09 22:52:47 +00:00
685cb32d2b
Add VCVTPD2PS, VCVTPS2DQ, VCVTPS2PDY, VCVTTPD2DQY, VCVTTPS2DQ and VCVTPD2DQ 256-bit conversion intrinsics
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llvm-svn: 110608
2010-08-09 21:51:56 +00:00
3e9b567643
Add patterns to AVX conversions instructions. Do that instead of declaring more intructions whenever is possible, more coming
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llvm-svn: 110605
2010-08-09 21:24:59 +00:00
212cfde6ec
CMake: eliminated unnecessary target_link_libraries.
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Next time the build is broken due to wrong library dependencies, just
try building again (if you are on some Unix and are building all LLVM
targets) or ask someone to commit the regenerated LLVMLibDeps.cmake.
llvm-svn: 110593
2010-08-09 20:33:08 +00:00
c33940b3aa
Memory version of vcvtdq2pd intrinsic
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llvm-svn: 110582
2010-08-09 18:20:14 +00:00
828f6aeced
Patterns to match vinsert, vbroadcast, vmovmask and vcvtdq2pd AVX intrinsics
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llvm-svn: 110580
2010-08-09 18:03:43 +00:00
a3bd31a923
Use sdmem and sse_load_f64 (etc.) for the vector
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form of CMPSD (etc.) Matching a 128-bit memory
operand is wrong, the instruction uses only 64 bits
(same as ADDSD etc.) 8193553.
llvm-svn: 110491
2010-08-07 00:33:42 +00:00
93cc666a58
Patterns to match AVX 256-bit vzero intrinsics
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llvm-svn: 110480
2010-08-06 22:10:01 +00:00
3d6a3a0ede
Patterns to match AVX 256-bit permutation intrinsics
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llvm-svn: 110468
2010-08-06 20:03:27 +00:00
a7aed18624
Reapply r110396, with fixes to appease the Linux buildbot gods.
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llvm-svn: 110460
2010-08-06 18:33:48 +00:00
1cf067cb3d
Patterns to match AVX 256-bit horizontal arithmetic intrinsics
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llvm-svn: 110427
2010-08-06 02:10:30 +00:00
b9ad94fbf7
Patterns to match AVX 256-bit arithmetic intrinsics
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llvm-svn: 110425
2010-08-06 01:52:29 +00:00
bda59bd247
Revert r110396 to fix buildbots.
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llvm-svn: 110410
2010-08-06 00:23:35 +00:00
e1fb772aa5
Add an option to always emit realignment code for a particular module.
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llvm-svn: 110404
2010-08-05 23:57:43 +00:00
755aceb5d0
Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
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ID member as the sole unique type identifier. Clean up APIs related to this change.
llvm-svn: 110396
2010-08-05 23:42:04 +00:00
77954bdf7a
Support very basic (doesn't include ABI support in the front-end, varags, ...) 256-bit argument passing and return for AVX
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llvm-svn: 110394
2010-08-05 23:35:51 +00:00
4d9c3400f3
Handle the memory barrier pseudo that goes to nothing for the JIT.
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llvm-svn: 110371
2010-08-05 20:04:36 +00:00
7fd06eb8ce
Set hasSideEffects on the 64-bit no-sse memory barrier.
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llvm-svn: 110369
2010-08-05 19:54:59 +00:00
32f5d6b9be
Be a little bit more specific about target for the memory barrier
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instructions.
llvm-svn: 110360
2010-08-05 18:36:20 +00:00
4abffad17c
Handle the pseudo in MCInstLower.
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llvm-svn: 110359
2010-08-05 18:34:30 +00:00
2db8464282
Make x86-64 membarriers work without sse and clean up some of the
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uses.
llvm-svn: 110274
2010-08-04 23:03:04 +00:00
39d0f57cab
PR7814: Truncates cannot be ignored for signed comparisons.
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llvm-svn: 110268
2010-08-04 22:40:58 +00:00
Jakob Stoklund Olesen