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Author SHA1 Message Date
Alex Bradbury 7d0e18d0dd [RISCV][MC] Reject bare symbols for the simm12 operand type 
addi a0, a0, foo and lw a0, foo(a0) and similar are now rejected. An explicit 
%lo and %pcrel_lo modifier is required. This matches gas behaviour.

llvm-svn: 342487
 2018-09-18 15:13:29 +00:00
Alex Bradbury 7bc2a95bb9 [RISCV] MC layer support for the standard RV32D instruction set extension 
As the FPR32 and FPR64 registers have the same names, use 
validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an 
FPR64 when necessary. The rest of this patch is very similar to the RV32F 
patch.

Differential Revision: https://reviews.llvm.org/D39895

llvm-svn: 320023
 2017-12-07 10:46:23 +00:00