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17428 Commits

Author SHA1 Message Date
Evan Cheng 88530e6568 Avoid de-referencing pass beginning of a basic block. No small test case possible. rdar://9216009 
llvm-svn: 128743
 2011-04-01 22:09:28 +00:00
Akira Hatanaka 3d9df607ba Remove redundant code. There are assignments to variables Base and Offset right after the code that is removed. 
llvm-svn: 128742
 2011-04-01 21:56:02 +00:00
Akira Hatanaka 56d9ef53a2 Simplifies logic for printing target flags. 
llvm-svn: 128741
 2011-04-01 21:41:06 +00:00
Owen Anderson 975ddf8035 When the architecture is explicitly armv6 or thumbv6, we need to mark the object file appropriately. 
llvm-svn: 128739
 2011-04-01 21:07:39 +00:00
Jim Grosbach 360c369967 LDRD/STRD instructions should print both Rt and Rt2 in the asm string. 
llvm-svn: 128736
 2011-04-01 20:26:57 +00:00
Johnny Chen 3dfb80afbf Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction 
as invalid.

llvm-svn: 128734
 2011-04-01 20:21:38 +00:00
Akira Hatanaka e625ba46b7 Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it handles delay slots correctly. 
llvm-svn: 128724
 2011-04-01 18:57:38 +00:00
Johnny Chen fe6fba3fe6 Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). 
rdar://problem/9219356

llvm-svn: 128722
 2011-04-01 18:26:38 +00:00
Akira Hatanaka 93f898f643 Add code for analyzing FP branches. Clean up branch Analysis functions. 
llvm-svn: 128718
 2011-04-01 17:39:08 +00:00
Benjamin Kramer bb21fac250 Initialize HasVMLxForwarding. 
llvm-svn: 128709
 2011-04-01 09:20:31 +00:00
Evan Cheng bd76679700 Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs. 
rdar://8911343

llvm-svn: 128696
 2011-04-01 00:42:02 +00:00
Matt Beaumont-Gay d911f92c46 Remove unused variables 
llvm-svn: 128692
 2011-04-01 00:06:01 +00:00
Bruno Cardoso Lopes ab8305063b Apply again changes to support ARM memory asm parsing. I removed 
all LDR/STR changes and left them to a future patch. Passing all
checks now.

- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

llvm-svn: 128689
 2011-03-31 23:26:08 +00:00
Jakob Stoklund Olesen 0709342652 Provide a legal pointer register class when targeting thumb1. 
The LocalStackSlotAllocation pass was creating illegal registers.

llvm-svn: 128687
 2011-03-31 23:02:15 +00:00
Evan Cheng 38bf5adcea Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier 
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2

llvm-svn: 128665
 2011-03-31 19:38:48 +00:00
Johnny Chen 7b203f9cae Fix single word and unsigned byte data transfer instruction encodings so that 
Inst{4} = 0.

rdar://problem/9213022

llvm-svn: 128662
 2011-03-31 19:28:35 +00:00
Akira Hatanaka a535270d91 Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. 
llvm-svn: 128650
 2011-03-31 18:26:17 +00:00
Johnny Chen 13baa0e650 Add BLXi to the instruction table for disassembly purpose. 
A8.6.23 BLX (immediate)

rdar://problem/9212921

llvm-svn: 128644
 2011-03-31 17:53:50 +00:00
Bruno Cardoso Lopes c2452a6f1d Revert r128632 again, until I figure out what break the tests 
llvm-svn: 128635
 2011-03-31 15:54:36 +00:00
Richard Osborne 9a827b30ab Add XCore intrinsics for initializing / starting / synchronizing threads. 
llvm-svn: 128633
 2011-03-31 15:13:13 +00:00
Bruno Cardoso Lopes 4c0aebfb91 Reapply r128585 without generating a lib depedency cycle. An updated log: 
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
  addrmode2.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

llvm-svn: 128632
 2011-03-31 14:52:28 +00:00
Matt Beaumont-Gay 73906b05ca Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and" 
This revision introduced a dependency cycle, as nlewycky mentioned by email.

llvm-svn: 128597
 2011-03-31 00:39:16 +00:00
Owen Anderson abda3caf67 Somehow we managed to forget to encode the lane index for a large swathe of NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler. 
llvm-svn: 128587
 2011-03-30 23:45:29 +00:00
Evan Cheng ee9d45dd55 Don't try to create zero-sized stack objects. 
llvm-svn: 128586
 2011-03-30 23:44:13 +00:00
Bruno Cardoso Lopes 280264b889 - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and 
{STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser

llvm-svn: 128585
 2011-03-30 23:32:32 +00:00
Cameron Zwarich 53dd03d537 Add a ARM-specific SD node for VBSL so that forms with a constant first operand 
can be recognized. This fixes <rdar://problem/9183078>.

llvm-svn: 128584
 2011-03-30 23:01:21 +00:00
Akira Hatanaka 4e9ca1b3ba fixed typo 
llvm-svn: 128574
 2011-03-30 21:15:35 +00:00
Jay Foad 52131344a2 Remove PHINode::reserveOperandSpace(). Instead, add a parameter to 
PHINode::Create() giving the (known or expected) number of operands.

llvm-svn: 128537
 2011-03-30 11:28:46 +00:00
Evan Cheng 18381b4257 Add intrinsics @llvm.arm.neon.vmulls and @llvm.arm.neon.vmullu.* back. Frontends 
was lowering them to sext / uxt + mul instructions. Unfortunately the
optimization passes may hoist the extensions out of the loop and separate them.
When that happens, the long multiplication instructions can be broken into
several scalar instructions, causing significant performance issue.

Note the vmla and vmls intrinsics are not added back. Frontend will codegen them
as intrinsics vmull* + add / sub. Also note the isel optimizations for catching
mul + sext / zext are not changed either.

First part of rdar://8832507, rdar://9203134

llvm-svn: 128502
 2011-03-29 23:06:19 +00:00
Cameron Zwarich 143f9aea2b Add Neon SINT_TO_FP and UINT_TO_FP lowering from v4i16 to v4f32. Fixes 
<rdar://problem/8875309> and <rdar://problem/9057191>.

llvm-svn: 128492
 2011-03-29 21:41:55 +00:00
Owen Anderson 7ac53ad643 Check early if this is an unsupported opcode, so that we can avoid needlessly instantiating the base register in some cases. 
llvm-svn: 128481
 2011-03-29 20:27:38 +00:00
Johnny Chen 4bc2baeb28 A8.6.188 STC, STC2 
The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}.

rdar://problem/9200661

llvm-svn: 128478
 2011-03-29 19:49:38 +00:00
Owen Anderson c48981f729 Add safety check that didn't show up in testing. 
llvm-svn: 128467
 2011-03-29 17:42:25 +00:00
Owen Anderson d6c5a741b5 Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist. 
llvm-svn: 128461
 2011-03-29 16:45:53 +00:00
Evan Cheng e2086e740f Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during 
isel lowering to fold the zero-extend's and take advantage of no-stall
back to back vmul + vmla:
 vmull q0, d4, d6
 vmlal q0, d5, d6
is faster than
 vaddl q0, d4, d5
 vmovl q1, d6                                                                                                                                                                             
 vmul  q0, q0, q1

This allows us to vmull + vmlal for:
    f = vmull_u8(   vget_high_u8(s), c);
    f = vmlal_u8(f, vget_low_u8(s),  c);

rdar://9197392

llvm-svn: 128444
 2011-03-29 01:56:09 +00:00
Daniel Dunbar 3e2b335903 Integrated-As: Add support for setting the AllowTemporaryLabels flag via 
integrated-as.

llvm-svn: 128431
 2011-03-28 22:49:19 +00:00
Johnny Chen f9cd139369 Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add some test cases. 
Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly.

llvm-svn: 128417
 2011-03-28 18:41:58 +00:00
Che-Liang Chiou cdedaf1f7d ptx: clean up branch code a bit 
llvm-svn: 128405
 2011-03-28 10:23:13 +00:00
Benjamin Kramer 8d2227373d Make helper static. 
llvm-svn: 128338
 2011-03-26 12:38:19 +00:00
Johnny Chen 923f3dac01 Fixed the t2PLD and friends disassembly and add two test cases. 
llvm-svn: 128322
 2011-03-26 01:32:48 +00:00
Eric Christopher d553096688 Fix the bfi handling for or (and a mask) (and b mask). We need the two 
masks to match inversely for the code as is to work. For the example given
we actually want:

bfi r0, r2, #1, #1

not #0, however, given the way the pattern is written it's not possible
at the moment.

Fixes rdar://9177502

llvm-svn: 128320
 2011-03-26 01:21:03 +00:00
Johnny Chen 49316e40ba Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID. 
Also add some test cases.

rdar://problem/9189829

llvm-svn: 128304
 2011-03-25 22:19:07 +00:00
Johnny Chen aaf2c69400 DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases. 
rdar://problem/9182892

llvm-svn: 128299
 2011-03-25 19:35:37 +00:00
Johnny Chen b35548f44d Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to 
t2LDREX/t2STREX instructions.  Add two test cases.

llvm-svn: 128293
 2011-03-25 18:29:49 +00:00
Benjamin Kramer dc0082b087 Add a note. 
llvm-svn: 128286
 2011-03-25 17:32:40 +00:00
Johnny Chen aa84d41dfc Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that. 
rdar://problem/9184053

llvm-svn: 128285
 2011-03-25 17:31:16 +00:00
Johnny Chen 757ca69770 Also need to handle invalid imod values for CPS2p. 
rdar://problem/9186136

llvm-svn: 128283
 2011-03-25 17:03:12 +00:00
Jakob Stoklund Olesen a1e3156ebd Ignore special ARM allocation hints for unexpected register classes. 
Add an assertion to linear scan to prevent it from allocating registers outside
the register class.

<rdar://problem/9183021>

llvm-svn: 128254
 2011-03-25 01:48:18 +00:00
Johnny Chen a52143bff3 Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed), 
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.

llvm-svn: 128252
 2011-03-25 01:09:48 +00:00
Matt Beaumont-Gay 303e3161bb Suppress an unused variable warning in -asserts builds 
llvm-svn: 128244
 2011-03-24 22:05:48 +00:00