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1321 Commits

Author SHA1 Message Date
Evan Cheng 9456dd8b81 Fix comments. 
llvm-svn: 31414
 2006-11-03 07:31:32 +00:00
Evan Cheng 1dfd26a151 Rename 
llvm-svn: 31413
 2006-11-03 07:21:16 +00:00
Reid Spencer 52f958741a Remove dead variable. Fix 80 column violations. 
llvm-svn: 31412
 2006-11-03 03:30:34 +00:00
Evan Cheng 357017f4a9 Added DAG combiner transformation to generate pre-indexed loads. 
llvm-svn: 31410
 2006-11-03 03:06:21 +00:00
Evan Cheng c176f038b9 Added isPredecessor. 
llvm-svn: 31409
 2006-11-03 03:05:24 +00:00
Chris Lattner cd7b92251d silence warning 
llvm-svn: 31397
 2006-11-03 01:28:29 +00:00
Reid Spencer de46e48420 For PR786: 
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.

llvm-svn: 31380
 2006-11-02 20:25:50 +00:00
Reid Spencer 7eb55b395f For PR950: 
Replace the REM instruction with UREM, SREM and FREM.

llvm-svn: 31369
 2006-11-02 01:53:59 +00:00
Chris Lattner 55402d4403 Allow the getRegForInlineAsmConstraint method to return a register class with 
no fixes physreg.  Treat this as permission to use any register in the register
class.  When this happens and it is safe, allow the llvm register allcoator to
allocate the register instead of doing it at isel time.  This eliminates a ton
of copies around common inline asms.  For example:

int test2(int Y, int X) {
  asm("foo %0, %1" : "=r"(X): "r"(X));
  return X;
}

now compiles to:

_test2:
        foo r3, r4
        blr

instead of:

_test2:
        mr r2, r4
        foo r2, r2
        mr r3, r2
        blr

GCC produces:

_test2:
        foo r4, r4
        mr r3,r4
        blr

llvm-svn: 31366
 2006-11-02 01:41:49 +00:00
Evan Cheng 1359196c4e Clean up. 
llvm-svn: 31359
 2006-11-01 22:39:30 +00:00
Evan Cheng 47218fab42 CopyFromReg starts a live range so its use should not be considered a floater. 
llvm-svn: 31356
 2006-11-01 22:17:06 +00:00
Evan Cheng 415f365e5c Print jumptable index. 
llvm-svn: 31340
 2006-11-01 04:48:30 +00:00
Chris Lattner fe43befeda Compile CodeGen/PowerPC/fp-branch.ll to: 
_intcoord_cond_next55:
LBB1_3: ;cond_next55
        lis r2, ha16(LCPI1_0)
        lfs f0, lo16(LCPI1_0)(r2)
        fcmpu cr0, f1, f0
        blt cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
        li r3, 1
        blr
LBB1_2: ;cond_next62.exitStub
        li r3, 0
        blr

instead of:

_intcoord_cond_next55:
LBB1_3: ;cond_next55
        lis r2, ha16(LCPI1_0)
        lfs f0, lo16(LCPI1_0)(r2)
        fcmpu cr0, f1, f0
        bge cr0, LBB1_1 ;bb72.exitStub
LBB1_4: ;cond_next55
        lis r2, ha16(LCPI1_0)
        lfs f0, lo16(LCPI1_0)(r2)
        fcmpu cr0, f1, f0
        bnu cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
        li r3, 1
        blr
LBB1_2: ;cond_next62.exitStub
        li r3, 0
        blr

llvm-svn: 31330
 2006-10-31 23:06:00 +00:00
Chris Lattner 427301fdae look through isunordered to inline it into branch blocks. 
llvm-svn: 31328
 2006-10-31 22:37:42 +00:00
Chris Lattner 1fd360e13a handle global address constant sdnodes 
llvm-svn: 31323
 2006-10-31 20:01:56 +00:00
Chris Lattner 6f043b90ea TargetLowering::isOperandValidForConstraint 
llvm-svn: 31319
 2006-10-31 19:41:18 +00:00
Chris Lattner 8c6949e5b2 Change the prototype for TargetLowering::isOperandValidForConstraint 
llvm-svn: 31318
 2006-10-31 19:40:43 +00:00
Chris Lattner 968f803928 Turn an assert into an error message. This is commonly triggered when 
we don't support a specific constraint yet.  When this happens, print the
unsupported constraint.

llvm-svn: 31310
 2006-10-31 07:33:13 +00:00
Evan Cheng e6d584765f Fix a typo which can break jumptables. 
llvm-svn: 31305
 2006-10-31 02:31:00 +00:00
Evan Cheng 84a28d4e76 Lower jumptable to BR_JT. The legalizer can lower it to a BRIND or let the target custom lower it. 
llvm-svn: 31293
 2006-10-30 08:00:44 +00:00
Evan Cheng c3e695137d Added a new SDNode type: BR_JT for jumptable branch. 
llvm-svn: 31292
 2006-10-30 07:59:36 +00:00
Chris Lattner e60ae823e8 fix Generic/2006-10-29-Crash.ll 
llvm-svn: 31281
 2006-10-29 21:01:20 +00:00
Chris Lattner f31b9ef458 Fix a load folding issue that Evan noticed: there is no need to export values 
used by comparisons in the main block.

llvm-svn: 31279
 2006-10-29 18:23:37 +00:00
Evan Cheng 7ab6123c42 VLOAD is not the LoadSDNode opcode. 
llvm-svn: 31276
 2006-10-29 06:14:47 +00:00
Nick Lewycky dc146a9fb9 Remove spurious case. EXTLOAD is not one of the node opcodes. 
llvm-svn: 31275
 2006-10-29 02:26:30 +00:00
Chris Lattner bba52191fa split critical edges more carefully and intelligently. In particular, critical 
edges whose destinations are not phi nodes don't bother us.  Also, share
split edges, since the split edge can't have a phi.  This significantly
reduces the complexity of generated code in some cases.

llvm-svn: 31274
 2006-10-28 19:22:10 +00:00
Jim Laskey eef273a16f Load and stores have not been uniqued properly. 
llvm-svn: 31261
 2006-10-28 17:25:28 +00:00
Chris Lattner 3e6b1c6157 Split *all* critical edges before isel. This resolves issues with spill code 
being inserted on unsplit critical edges, which introduces (sometimes large
amounts of) partially dead spill code.

This also fixes PR925 + CodeGen/Generic/switch-crit-edge-constant.ll

llvm-svn: 31260
 2006-10-28 17:04:37 +00:00
Chris Lattner b78eb6c8d1 Fix a serious bug that caused any x86 vector stuff to infinite loop 
llvm-svn: 31254
 2006-10-28 06:15:26 +00:00
Jim Laskey bd0f088743 Clean up. 
llvm-svn: 31243
 2006-10-27 23:52:51 +00:00
Chris Lattner 84a035056e Fix a bug in merged condition handling (CodeGen/Generic/2006-10-27-CondFolding.ll). 
Add many fewer CFG edges and PHI node entries.  If there is a switch which has
the same block as multiple destinations, only add that block once as a successor/phi
node (in the jumptable case)

llvm-svn: 31242
 2006-10-27 23:50:33 +00:00
Jim Laskey f576b42bb2 Switch over from SelectionNodeCSEMap to FoldingSet. 
llvm-svn: 31240
 2006-10-27 23:46:08 +00:00
Chris Lattner b9392fb635 remove debug code 
llvm-svn: 31233
 2006-10-27 21:58:03 +00:00
Chris Lattner f1b54fd7a5 Codegen cond&cond with two branches. This compiles (f.e.) PowerPC/and-branch.ll to: 
cmpwi cr0, r4, 4
        bgt cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_3: ;entry
        cmplwi cr0, r3, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock

instead of:

        cmpwi cr7, r4, 4
        mfcr r2
        addic r4, r3, -1
        subfe r3, r4, r3
        rlwinm r2, r2, 30, 31, 31
        or r2, r2, r3
        cmplwi cr0, r2, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_1: ;cond_true

llvm-svn: 31232
 2006-10-27 21:54:23 +00:00
Chris Lattner ed0110b949 Turn conditions like x<Y|z==q into multiple blocks. 
This compiles Regression/CodeGen/X86/or-branch.ll into:

_foo:
        subl $12, %esp
        call L_bar$stub
        movl 20(%esp), %eax
        movl 16(%esp), %ecx
        cmpl $5, %eax
        jl LBB1_1       #cond_true
LBB1_3: #entry
        testl %ecx, %ecx
        jne LBB1_2      #UnifiedReturnBlock
LBB1_1: #cond_true
        call L_bar$stub
        addl $12, %esp
        ret
LBB1_2: #UnifiedReturnBlock
        addl $12, %esp
        ret

instead of:

_foo:
        subl $12, %esp
        call L_bar$stub
        movl 20(%esp), %eax
        movl 16(%esp), %ecx
        cmpl $4, %eax
        setg %al
        testl %ecx, %ecx
        setne %cl
        testb %cl, %al
        jne LBB1_2      #UnifiedReturnBlock
LBB1_1: #cond_true
        call L_bar$stub
        addl $12, %esp
        ret
LBB1_2: #UnifiedReturnBlock
        addl $12, %esp
        ret

And on ppc to:

        cmpwi cr0, r29, 5
        blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
        cmplwi cr0, r30, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock

instead of:

        cmpwi cr7, r4, 4
        mfcr r2
        addic r4, r3, -1
        subfe r30, r4, r3
        rlwinm r29, r2, 30, 31, 31
        and r2, r29, r30
        cmplwi cr0, r2, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock

llvm-svn: 31230
 2006-10-27 21:36:01 +00:00
Evan Cheng 96d6bf50ae getPreIndexedLoad -> getIndexedLoad. 
llvm-svn: 31209
 2006-10-26 21:53:40 +00:00
Reid Spencer 7e80b0b31e For PR950: 
Make necessary changes to support DIV -> [SUF]Div. This changes llvm to
have three division instructions: signed, unsigned, floating point. The
bytecode and assembler are bacwards compatible, however.

llvm-svn: 31195
 2006-10-26 06:15:43 +00:00
Chris Lattner 61bcf9154d visitSwitchCase knows how to insert conditional branches well. Change 
visitBr to just call visitSwitchCase, eliminating duplicate logic.

llvm-svn: 31167
 2006-10-24 18:07:37 +00:00
Chris Lattner 963ddad31a Generalize CaseBlock a bit more: 
Rename LHSBB/RHSBB to TrueBB/FalseBB.  Allow the RHS value to be null,
in which case the LHS is treated as a bool.

llvm-svn: 31166
 2006-10-24 17:57:59 +00:00
Chris Lattner 3f179d24c6 generalize 'CaseBlock'. It really allows any comparison to be inserted. 
llvm-svn: 31161
 2006-10-24 17:03:35 +00:00
Chris Lattner 4c931502cc Minor tweak. Instead of generating: 
movl 32(%esp), %eax
        cmpl $1, %eax
        je LBB1_1       #bb
LBB1_4: #entry
        cmpl $2, %eax
        je LBB1_2       #bb2
        jmp LBB1_3      #UnifiedReturnBlock
LBB1_1: #bb

notice that we would miss the fall through and emit this instead:

        movl 32(%esp), %eax
        cmpl $2, %eax
        je LBB1_2       #bb2
LBB1_4: #entry
        cmpl $1, %eax
        jne LBB1_3      #UnifiedReturnBlock
LBB1_1: #bb

llvm-svn: 31130
 2006-10-23 18:38:22 +00:00
Chris Lattner 76a7bc8c55 Fix phi node updating for switches lowered to linear sequences of branches. 
llvm-svn: 31125
 2006-10-22 23:00:53 +00:00
Chris Lattner 4c3ef4782d disable this code for now, it's not yet safely updating phi nodes 
llvm-svn: 31124
 2006-10-22 22:47:10 +00:00
Chris Lattner 6d6fc26257 Implement PR964 and Regression/CodeGen/Generic/SwitchLowering.ll 
llvm-svn: 31119
 2006-10-22 21:36:53 +00:00
Chris Lattner c5ab6ce613 Make flag and chain edges visually distinguishable from value edges in DOT 
output.

llvm-svn: 31067
 2006-10-20 18:06:09 +00:00
Reid Spencer e0fc4dfc22 For PR950: 
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.

llvm-svn: 31063
 2006-10-20 07:07:24 +00:00
Bill Wendling be96e1cd09 Partially in response to PR926: insert the newly created machine basic 
blocks into the basic block list when lowering the switch inst. into a
binary tree of if-then statements. This allows the "visitSwitchCase" func
to allow for fall-through behavior.

llvm-svn: 31057
 2006-10-19 21:46:38 +00:00
Jim Laskey 55e4dcad36 Add option for controlling inclusion of global AA. 
llvm-svn: 31040
 2006-10-18 19:08:31 +00:00
Jim Laskey a15b0ebb5e Use global info for alias analysis. 
llvm-svn: 31035
 2006-10-18 12:29:57 +00:00
Chris Lattner 78fd0f83ff Trivial patch to speed up legalizing common i64 constants. 
llvm-svn: 31020
 2006-10-17 21:47:13 +00:00