Summary:
This patch adds clang system include path when offloading tool chains, e.g. CUDA, are used in the current compilation.
This fixes an issue detected by @rsmith in response to r275645.
Reviewers: rsmith, tra
Subscribers: rsmith, cfe-commits
Differential Revision: https://reviews.llvm.org/D22490
llvm-svn: 275931
Compute an effective target triple exactly once in ConstructJob(), and
then simply pass around references to it. This eliminates wasteful
re-computation of effective triples (e.g in getARMFloatABI()).
Differential Revision: https://reviews.llvm.org/D22290
llvm-svn: 275895
No in-tree targets access this `DefaultTargetTriple` directly, and usage
of default triples is generally discouraged. Make the field private.
This is part of en effort to make the clang driver use effective triples
more pervasively.
Differential Revision: https://reviews.llvm.org/D22289
llvm-svn: 275894
For assembly files without .intel_syntax or .att_syntax directives, allow the
-masm= flag to supply a default assembly dialect. For example,
C:\TMP> type intel.s
.text
mov al,0
C:\TMP> clang -masm=intel -c intel.s
Without this patch, one would need to pass an "-mllvm -x86-asm-syntax=" flag
directly to the backend.
C:\TMP> clang -mllvm --x86-asm-syntax=intel -c intel.s
Differentials Review: http://reviews.llvm.org/D22285
llvm-svn: 275877
Summary:
This patch replaces the CUDA specific action by a generic offload action. The offload action may have multiple dependences classier in “host” and “device”. The way this generic offloading action is used is very similar to what is done today by the CUDA implementation: it is used to set a specific toolchain and architecture to its dependences during the generation of jobs.
This patch also proposes propagating the offloading information through the action graph so that that information can be easily retrieved at any time during the generation of commands. This allows e.g. the "clang tool” to evaluate whether CUDA should be supported for the device or host and ptas to easily retrieve the target architecture.
This is an example of how the action graphs would look like (compilation of a single CUDA file with two GPU architectures)
```
0: input, "cudatests.cu", cuda, (host-cuda)
1: preprocessor, {0}, cuda-cpp-output, (host-cuda)
2: compiler, {1}, ir, (host-cuda)
3: input, "cudatests.cu", cuda, (device-cuda, sm_35)
4: preprocessor, {3}, cuda-cpp-output, (device-cuda, sm_35)
5: compiler, {4}, ir, (device-cuda, sm_35)
6: backend, {5}, assembler, (device-cuda, sm_35)
7: assembler, {6}, object, (device-cuda, sm_35)
8: offload, "device-cuda (nvptx64-nvidia-cuda:sm_35)" {7}, object
9: offload, "device-cuda (nvptx64-nvidia-cuda:sm_35)" {6}, assembler
10: input, "cudatests.cu", cuda, (device-cuda, sm_37)
11: preprocessor, {10}, cuda-cpp-output, (device-cuda, sm_37)
12: compiler, {11}, ir, (device-cuda, sm_37)
13: backend, {12}, assembler, (device-cuda, sm_37)
14: assembler, {13}, object, (device-cuda, sm_37)
15: offload, "device-cuda (nvptx64-nvidia-cuda:sm_37)" {14}, object
16: offload, "device-cuda (nvptx64-nvidia-cuda:sm_37)" {13}, assembler
17: linker, {8, 9, 15, 16}, cuda-fatbin, (device-cuda)
18: offload, "host-cuda (powerpc64le-unknown-linux-gnu)" {2}, "device-cuda (nvptx64-nvidia-cuda)" {17}, ir
19: backend, {18}, assembler
20: assembler, {19}, object
21: input, "cuda", object
22: input, "cudart", object
23: linker, {20, 21, 22}, image
```
The changes in this patch pass the existent regression tests (keeps the existent functionality) and resulting binaries execute correctly in a Power8+K40 machine.
Reviewers: echristo, hfinkel, jlebar, ABataev, tra
Subscribers: guansong, andreybokhanko, tcramer, mkuron, cfe-commits, arpith-jacob, carlo.bertolli, caomhin
Differential Revision: https://reviews.llvm.org/D18171
llvm-svn: 275645
Summary: Fix the build to use hasFlag instead of hasArg for checking some flags.
Reviewers: echristo
Subscribers: mehdi_amini, cfe-commits
Differential Revision: http://reviews.llvm.org/D22338
llvm-svn: 275377
Summary:
Depends on D21982 which implements the in-memory logging implementation of the
XRay runtime. These additional changes also depends on D20352 which adds the
bulk of XRay flags/dependencies when using the `-fxray-instrument` flag from
Clang.
Reviewers: echristo, rnk, aaron.ballman
Subscribers: mehdi_amini, cfe-commits
Differential Revision: http://reviews.llvm.org/D21983
llvm-svn: 275368
-fxray-instrument: enables XRay annotation of IR
-fxray-instruction-threshold: configures the threshold for function size (looking at IR instructions), and allow LLVM to decide whether to add the nop sleds later on in the process.
Also implements the related xray_always_instrument and xray_never_instrument function attributes.
Patch by Dean Michael Berris.
llvm-svn: 275330
Original Commit Message
Driver: Stop linking to C++ when using sanitizers on Darwin
Sanitizers on Darwin are built as dynamic libraries, not static libraries.
Sanitizers will have their C++ dependency satisfied internally (LC_LOAD_DYLIB)
in the libclang_rt dylib. As long as the sanitizers stay dynamic and not static,
linking against C++ when enabling a sanitizer becomes over linkage.
Patch by Dave Lee!
llvm-svn: 275032
MASM (ML.exe and ML64.exe) and older versions of MSVC (CL.exe) support a
flag called /Zd which is more-or-less -gline-tables-only.
It seems nicer to support this flag instead of exposing
-gline-tables-only.
llvm-svn: 274991
Add OCL option -cl-no-signed-zeros to driver options.
Also added to opencl.cl testcases.
Patch by Aaron En Ye Shi.
Differential Revision: http://reviews.llvm.org/D22067
llvm-svn: 274923
Sanitizers on Darwin are built as dynamic libraries, not static libraries.
Sanitizers will have their C++ dependency satisfied internally (LC_LOAD_DYLIB)
in the libclang_rt dylib. As long as the sanitizers stay dynamic and not static,
linking against C++ when enabling a sanitizer becomes over linkage.
Patch by Dave Lee!
llvm-svn: 274797
Summary:
Raise an error if you're using a CUDA installation that's too old for
the requested architectures. In practice, this means that you need a
CUDA 8 install to compile for sm_6*.
Reviewers: tra
Subscribers: cfe-commits
Differential Revision: http://reviews.llvm.org/D21869
llvm-svn: 274781
Summary:
Remove the "Cuda" prefix from these variables -- it's clear that they
related to CUDA given their containing type.
Reviewers: tra
Subscribers: cfe-commits
Differential Revision: http://reviews.llvm.org/D21868
llvm-svn: 274682
Summary:
Currently our handling of CUDA architectures is scattered all around
clang. This patch centralizes it.
A key advantage of this centralization is that you can now write a C++
switch on e.g. CudaArch and get a compile error if you don't handle one
of the enum values.
Reviewers: tra
Subscribers: cfe-commits
Differential Revision: http://reviews.llvm.org/D21867
llvm-svn: 274681
Summary: Also add sm_32, which was missing.
Reviewers: tra
Subscribers: cfe-commits
Differential Revision: http://reviews.llvm.org/D21778
llvm-svn: 274680
Summary: This change exposes the recently added LEON CPUs (D19359) in the LLVM Sparc backend to Clang, allowing the cpu's to be selected using the -mcpu flag.
Reviewers: jyknight, lero_chris
Subscribers: jyknight, cfe-commits
Differential Revision: http://reviews.llvm.org/D21683
llvm-svn: 274487
Allow -cl-std and other standard -cl- options from cc1 to driver.
Added a test for the options moved.
Patch by Aaron En Ye Shi.
Differential Revision: http://reviews.llvm.org/D21031
llvm-svn: 274150
Summary:
Currently output of child process, however in my use case, it
needs to be captured and presented to the user.
Add Redirect method to Compilation and use existing infrastructure
for redirecting output of commands.
Reviewers: tstellarAMD
Subscribers: cfe-commits
Differential Revision: http://reviews.llvm.org/D21224
llvm-svn: 273997
The PIC and PIE levels are not independent. In fact, if PIE is defined
it is always the same as PIC.
This is clear in the driver where ParsePICArgs returns a PIC level and
a IsPIE boolean. Unfortunately that is currently lost and we pass two
redundant levels down the pipeline.
This patch keeps a bool and a PIC level all the way down to codegen.
llvm-svn: 273566
No extra tests required as this is currently covered by existing testing, and this is basically impossible to write Unicode-specific tests for.
llvm-svn: 273563
The findMIPSMultilibs is too long. One more reason for splitting is to
escape redundant calls of MultilibSet::FilterOut method which lead to
disk access.
llvm-svn: 273465
Add support for /Ob1 (and equivalent -finline-hint-functions), which enable
inlining only for functions marked inline, either explicitly (via inline
keyword, for example), or implicitly (function definition in class body,
for example).
This works by enabling inlining pass, and adding noinline attribute to
every function not marked inline.
Patch by Rudy Pons <rudy.pons@ilod.org>!
Differential Revision: http://reviews.llvm.org/D20647
llvm-svn: 273440
Add -mno-iamcu option to:
1) Countervail -miamcu option easily
2) Be compatible with GCC which supports this option
Differential Revision: http://reviews.llvm.org/D21469
llvm-svn: 273147
This mirrors the many other -i*after options to insert a new system search
directory at the end of the search path. This makes it possible to actually
inject a search path after the resource dir. This option is similar in spirit
to the /imsvc option in the clang-cl driver. This is needed to properly use the
driver for Windows targets where the clang headers wrap some of the system
headers.
This concept is actually useful on other targets (e.g. Linux) and would be
really easy to support on the core toolchain.
llvm-svn: 273016
Summary:
Some GCC 5 installations store the libstdc++ includes and GCC-specific files in paths without
the minor part of the version number, such as
/usr/include/c++/5
/usr/lib64/gcc/x86_64-suse-linux/5
Reviewers: cfe-commits, thiagomacieira, jroelofs
Subscribers: tinti, jroelofs
Differential Revision: http://reviews.llvm.org/D14727
llvm-svn: 273012
This is the last patch required to support compilation for Intel MCU target (e.g. Intel(R) Quark(TM) micro controller D 2000).
When IAMCU triple is used:
* Use IAMCU linker output format
* Link with IAMCU crt objects
* Link with IAMCU libraries
Differential Revision: http://reviews.llvm.org/D20675
llvm-svn: 272885
This is the second patch required to support compilation for Intel MCU target (e.g. Intel(R) Quark(TM) micro controller D 2000).
When IAMCU triple is used:
* Recognize and use IAMCU GCC toolchain
* Set up include paths
* Forbid C++
Differential Revision: http://reviews.llvm.org/D19274
llvm-svn: 272883
Summary:
Previously if you did e.g.
$ clang -march=haswell -x cuda foo.cu
we would pass "-march=haswell -march=sm_20" down to the ptxas tool.
This causes it to assert, and rightly so!
Reviewers: tra
Subscribers: cfe-commits, echristo
Differential Revision: http://reviews.llvm.org/D21419
llvm-svn: 272857
Sylvestre Ledru