eabd647cd5
Change target-specific classes to use more precise static types.
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This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.
llvm-svn: 51091
2008-05-14 01:58:56 +00:00
1e11768a4f
Constify the machine instruction passed into the
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"is{Trivially,Really}ReMaterializable" methods.
llvm-svn: 51001
2008-05-12 20:54:26 +00:00
fa8f9f937a
Undo r50574. We are already ensuring the folded load address is 16-byte aligned.
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llvm-svn: 50578
2008-05-02 17:01:01 +00:00
50f82f2c8e
Not safe folding a load + FsXORPSrr into FsXORPSrm. It's loading a FR64 value but the load folding variant expects a 16-byte aligned address.
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llvm-svn: 50574
2008-05-02 07:50:58 +00:00
984e7199cc
Don't forget to update the current operand when getting the size of an instruction.
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llvm-svn: 50007
2008-04-20 23:36:47 +00:00
147cb764b5
Don't forget about sub-register indices when rematting instructions.
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llvm-svn: 49830
2008-04-16 23:44:44 +00:00
ae84bbdbed
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
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llvm-svn: 49809
2008-04-16 20:10:13 +00:00
3bc3ddd638
Rename MemOperand to MachineMemOperand. This was suggested by
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review feedback from Chris quite a while ago. No functionality
change.
llvm-svn: 49348
2008-04-07 19:35:22 +00:00
b86595fb0a
ReMat of load from stub in pic mode extends the life of pic base. Currently spiller doesn't do a good job of estimating the impact. Disable for now.
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llvm-svn: 49059
2008-04-01 23:26:12 +00:00
19a6dd9f2a
Remove unnecessary and non-deterministic checking code. Re-enable remat of load from gv stub.
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llvm-svn: 49054
2008-04-01 21:38:20 +00:00
306e3dcff4
Disabling remat of load from gv stub (temporarily) again to fix llvmgcc bootstrap miscompare.
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llvm-svn: 49037
2008-04-01 07:33:13 +00:00
e4f77c69ac
It's not safe to fold a load from GV stub or constantpool into a two-address use.
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llvm-svn: 49002
2008-03-31 23:19:51 +00:00
ed6e34fe41
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
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llvm-svn: 48995
2008-03-31 20:40:39 +00:00
1973a46cd3
Re-apply 48911.
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llvm-svn: 48977
2008-03-31 07:54:19 +00:00
b8654202dd
Backing out 48911 for now. It's breaking stuff.
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llvm-svn: 48922
2008-03-28 17:49:06 +00:00
9ae4d7b719
Load from stub is already re-materializable.
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llvm-svn: 48911
2008-03-28 06:49:25 +00:00
308e564693
Code clean up.
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llvm-svn: 48856
2008-03-27 01:45:11 +00:00
29e62a59f3
Allow certain lea instructions to be rematerialized.
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llvm-svn: 48855
2008-03-27 01:41:09 +00:00
4fb07c6500
Remove an unused command line option.
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llvm-svn: 48854
2008-03-27 01:30:24 +00:00
883cbfd0ba
Add CMP32mr and friends to the load-unfolding table. Among
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other things, this allows the scheduler to unfold a load operand
in the 2008-01-08-SchedulerCrash.ll testcase, so it now successfully
clones the comparison to avoid a pushf+popf.
llvm-svn: 48777
2008-03-25 16:53:19 +00:00
5abbe6cef5
Add support for calls that return two FP values in
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ST(0)/ST(1).
llvm-svn: 48634
2008-03-21 06:38:26 +00:00
d3d0ad3f58
Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
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llvm-svn: 48412
2008-03-16 03:12:01 +00:00
dd55d3f1b2
Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.
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Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329
2008-03-13 05:47:01 +00:00
7b27ccfd5e
coalesce away 80-bit floating point copies.
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llvm-svn: 48241
2008-03-11 19:30:09 +00:00
7930d8e775
convert a massive if statement to a switch.
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llvm-svn: 48240
2008-03-11 19:28:17 +00:00
342e4104d3
Missed part of recommit.
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llvm-svn: 48224
2008-03-11 10:27:36 +00:00
a4fa0ad30d
abort with an assert instead of a cerr to get line#
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llvm-svn: 48199
2008-03-10 23:56:08 +00:00
d4e1d9eeb2
Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
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llvm-svn: 48167
2008-03-10 19:31:26 +00:00
4ba3f0430b
Allow insert_subreg into implicit, target-specific values.
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Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.
llvm-svn: 48130
2008-03-10 06:12:08 +00:00
86829f0ff7
teach X86InstrInfo::copyRegToReg how to copy into ST(0) from
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an RFP register class.
Teach ScheduleDAG how to handle CopyToReg with different src/dst
reg classes.
This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.
llvm-svn: 48107
2008-03-09 09:15:31 +00:00
b79bafcec8
add some code to support cross-register class copying from
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RST -> RFP{32/64/80}. We only handle ST(0) for now.
llvm-svn: 48104
2008-03-09 08:46:19 +00:00
c4c9dde04c
rearrange some code, no functionality change.
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llvm-svn: 48101
2008-03-09 07:58:04 +00:00
42cb72e52c
Turning on remat of pic loads.
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llvm-svn: 47524
2008-02-23 02:07:42 +00:00
4d17671997
No need recognize load from a fixed argument slot as re-materializable. LiveIntervalAnalysis already handles it as a special case.
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llvm-svn: 47522
2008-02-23 01:47:44 +00:00
94ba37f8e3
Allow re-materialization of pic load (controlled by -remat-pic-load for now).
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llvm-svn: 47476
2008-02-22 09:25:47 +00:00
244183ef0d
commuteInstr() can now commute non-ssa machine instrs.
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llvm-svn: 47043
2008-02-13 02:46:49 +00:00
3b3286d4bc
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
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llvm-svn: 46893
2008-02-08 21:20:40 +00:00
8d59dd119b
Added missing entries in X86 load / store folding tables.
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llvm-svn: 46866
2008-02-08 00:12:56 +00:00
1bc1cae318
In some cases, e.g. ADD32ri, no transformation is made. Guide against it.
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llvm-svn: 46849
2008-02-07 08:29:53 +00:00
18df33d0c8
fix a wordo that gordon noticed :)
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llvm-svn: 45896
2008-01-12 00:53:16 +00:00
6da61c2515
Any x86 instruction that reads from an invariant location is invariant.
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This allows us to sink things like:
cvtsi2sd 32(%esp), %xmm1
when reading from the argument area, for example.
llvm-svn: 45895
2008-01-12 00:35:08 +00:00
596875118c
rename MachineInstr::setInstrDescriptor -> setDesc
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llvm-svn: 45871
2008-01-11 18:10:50 +00:00
806dd0e2ac
remove xchg and shift-reg-by-1 instructions, which are dead.
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llvm-svn: 45870
2008-01-11 18:00:50 +00:00
c8226f32e9
Simplify the side effect stuff a bit more and make licm/sinking
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both work right according to the new flags.
This removes the TII::isReallySideEffectFree predicate, and adds
TII::isInvariantLoad.
It removes NeverHasSideEffects+MayHaveSideEffects and adds
UnmodeledSideEffects as machine instr flags. Now the clients
can decide everything they need.
I think isRematerializable can be implemented in terms of the
flags we have now, though I will let others tackle that.
llvm-svn: 45843
2008-01-10 23:08:24 +00:00
f171482a66
verify that the frame index is immutable before remat'ing (still disabled)
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or being side-effect free.
llvm-svn: 45816
2008-01-10 04:16:31 +00:00
9129f51f9b
add a testcase
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llvm-svn: 45768
2008-01-09 00:37:18 +00:00
a3bdad153f
Operand 1 should be a register. We don't care if it's a preg, vreg, or 0.
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llvm-svn: 45699
2008-01-07 08:05:29 +00:00
03ad885039
rename TargetInstrDescriptor -> TargetInstrDesc.
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Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
llvm-svn: 45695
2008-01-07 07:27:27 +00:00
b0d06b4381
Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
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llvm-svn: 45680
2008-01-07 03:13:06 +00:00
f0f438a517
remove MachineOpCode typedef.
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llvm-svn: 45679
2008-01-07 02:48:55 +00:00
Dan Gohman