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Author SHA1 Message Date
Justin Holewinski 11d70b6b32 PTX: add PTX 2.3 language target 
Patch by Wei-Ren Chen

llvm-svn: 130980
 2011-05-06 11:40:36 +00:00
Eli Friedman 5401962643 Re-revert r130877; it's apparently causing a regression on 197.parser, 
possibly related to cbnz formation.

llvm-svn: 130977
 2011-05-06 05:23:07 +00:00
Rafael Espindola a4982bddf3 Don't produce a __debug_frame. 
I tested both gdb on a bootstrapped clang and and the gdb testsuite on OS X (snow leopard)
and both are happy using __eh_frame.

llvm-svn: 130937
 2011-05-05 18:43:39 +00:00
Eli Friedman 441a01a2b8 Avoid extra vreg copies for arguments passed in registers. Specifically, this can make MachineCSE more effective in some cases (especially in small functions). PR8361 / part of rdar://problem/8259436 . 
llvm-svn: 130928
 2011-05-05 16:53:34 +00:00
Jakob Stoklund Olesen 17d4f9bbcc Prepare remaining tests for -join-physreg going away. 
llvm-svn: 130893
 2011-05-04 23:54:59 +00:00
Jakob Stoklund Olesen 369bddf5ad Fix a batch of x86 tests to be coalescer independent. 
Most of these tests require a single mov instruction that can come either before
or after a 2-addr instruction. -join-physregs changes the behavior, but the
results are equivalent.

llvm-svn: 130891
 2011-05-04 23:54:51 +00:00
Dan Gohman dd550305e6 Give this test an explicit register allocator, so that it can work even if 
the default register allocator is changed.

llvm-svn: 130883
 2011-05-04 23:14:02 +00:00
Bill Wendling 2a40131f6b SjLj EH could produce a machine basic block that legitimately has more than one 
landing pad as its successor.

SjLj exception handling jumps to the correct landing pad via a switch statement
that's generated right before code-gen. Loosen the constraint in the machine
instruction verifier to allow for this. Note, this isn't the most rigorous check
since we cannot determine where that switch statement came from. But it's
marginally better than turning this check off when SjLj exceptions are used.
<rdar://problem/9187612>

llvm-svn: 130881
 2011-05-04 22:54:05 +00:00
Eli Friedman 0fe4608af2 Re-commit r130862 with a minor change to avoid an iterator running off the edge in some cases. 
Original message:

Teach MachineCSE how to do simple cross-block CSE involving physregs.  This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 .

llvm-svn: 130877
 2011-05-04 22:10:36 +00:00
Galina Kistanova e53ae508ec This test fails on ARM. The test shouldn't explicitly specify alignment (and alignment 4 is wrong) and requires hard-float. 
llvm-svn: 130875
 2011-05-04 21:57:44 +00:00
Eli Friedman 3bd79ba856 Back out r130862; it appears to be breaking bootstrap. 
llvm-svn: 130867
 2011-05-04 20:48:42 +00:00
Eli Friedman a16fc2fec0 Teach MachineCSE how to do simple cross-block CSE involving physregs. This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 . 
llvm-svn: 130862
 2011-05-04 19:54:24 +00:00
Jakob Stoklund Olesen 28a93a49bb Fix more register and coalescing dependencies. 
llvm-svn: 130859
 2011-05-04 19:02:11 +00:00
Jakob Stoklund Olesen d7fd7bfc31 Explicitly request physreg coalesing for a bunch of Thumb2 unit tests. 
These tests all follow the same pattern:

	mov	r2, r0
	movs	r0, #0
	$CMP	r2, r1
	it	eq
	moveq	r0, #1
	bx	lr

The first 'mov' can be eliminated by rematerializing 'movs r0, #0' below the
test instruction:

	$CMP	r0, r1
	mov.w	r0, #0
	it	eq
	moveq	r0, #1
	bx	lr

So far, only physreg coalescing can do that. The register allocators won't yet
split live ranges just to eliminate copies. They can learn, but this particular
problem is not likely to show up in real code. It only appears because r0 is
used for both the function argument and return value.

llvm-svn: 130858
 2011-05-04 19:02:07 +00:00
Jakob Stoklund Olesen e7528c45ea FileCheckize and break dependence on coalescing order. 
llvm-svn: 130856
 2011-05-04 19:02:01 +00:00
Jakob Stoklund Olesen 067ba3c23c Explicitly request -join-physregs for some tests that depend on it. 
llvm-svn: 130855
 2011-05-04 19:01:59 +00:00
Devang Patel 39ecf816c5 Do not emit location expression size twice. 
llvm-svn: 130854
 2011-05-04 19:00:57 +00:00
Akira Hatanaka 3bace5d223 Remove LLVM IR metadata in test case committed in r130847. 
llvm-svn: 130849
 2011-05-04 18:28:36 +00:00
Akira Hatanaka 23e8ecf125 Prevent instructions using $gp from being placed between a jalr and the instruction that restores the clobbered $gp. 
llvm-svn: 130847
 2011-05-04 17:54:27 +00:00
Jakob Stoklund Olesen f1b401800a Don't depend on the physreg coalescing order. 
llvm-svn: 130818
 2011-05-04 01:01:47 +00:00
Jakob Stoklund Olesen 5b5abb4ea1 Don't run this test through -regalloc=basic. 
The basic allocator is really bad about hinting, so it doesn't eliminate all
copies when physreg joining is disabled.

llvm-svn: 130817
 2011-05-04 01:01:44 +00:00
Jakob Stoklund Olesen d3b2f44c9d Fix register-dependent XCore tests 
llvm-svn: 130816
 2011-05-04 01:01:41 +00:00
Jakob Stoklund Olesen 7f7fc82141 Fix register-dependent test in MSP430. 
llvm-svn: 130815
 2011-05-04 01:01:39 +00:00
Jakob Stoklund Olesen 51b35f7bb1 Fix a bunch of ARM tests to be register allocation independent. 
llvm-svn: 130800
 2011-05-03 22:31:21 +00:00
Bill Wendling db0996c822 Replace the "movnt" intrinsics with a native store + nontemporal metadata bit. 
<rdar://problem/8460511>

llvm-svn: 130791
 2011-05-03 21:11:17 +00:00
Evan Cheng 93b5cdc5ab Make the test less likely to fail with minor changes. 
llvm-svn: 130778
 2011-05-03 19:09:32 +00:00
Bob Wilson c5242b0e78 Remove test for iOS divmod function, since that is disabled for now. 
llvm-svn: 130769
 2011-05-03 17:54:49 +00:00
Bruno Cardoso Lopes 168c9005b5 Add a few ARM coprocessor intrinsics. Testcases included 
llvm-svn: 130763
 2011-05-03 17:29:22 +00:00
Dan Gohman 6136e94897 Add an unfolded offset field to LSR's Formula record. This is used to 
model constants which can be added to base registers via add-immediate
instructions which don't require an additional register to materialize
the immediate.

llvm-svn: 130743
 2011-05-03 00:46:49 +00:00
Rafael Espindola 5164e6e8b2 Add 130690 back. 
llvm-svn: 130693
 2011-05-02 15:58:16 +00:00
Rafael Espindola a392475865 Revert while I debug the tests that use march but not mtriple. 
llvm-svn: 130691
 2011-05-02 15:42:31 +00:00
Rafael Espindola c2aad4f2a3 Move ppc OS X to cfi too. I am building it on an old ppc mini, but it will take some time. 
llvm-svn: 130690
 2011-05-02 15:00:52 +00:00
Rafael Espindola fc8223670a Add r130623 back now that ELF has been fixed to work with -fno-dwarf2-cfi-asm. 
llvm-svn: 130658
 2011-05-01 15:44:13 +00:00
Rafael Espindola 750cb61553 GCC uses a different encoding of pointers in the FDE when using 
-fno-dwarf2-cfi-asm. Implement the same behavior.

llvm-svn: 130637
 2011-05-01 04:49:54 +00:00
Rafael Espindola b7c2286055 Revert the previous patch while I figure out how to make llvm-gcc 
less agressive about disabling cfi on linux :-(

llvm-svn: 130626
 2011-04-30 23:03:44 +00:00
Rafael Espindola 5265bc483e Enable CFI on OS X. 
Currently the output should be almost identical to the one produced by CodeGen
to make the transition easier.

The only two differences I know of are:

* Some files get an extra advance loc of size 0. This will be fixed when
relaxations are enabled.
* The optimization of declaring an EH symbol as an external variable is not
implemented. This is a subset of adding the nounwind attribute, so we if really
this at -O0 we should probably do it at the IL level.

llvm-svn: 130623
 2011-04-30 22:29:54 +00:00
Jakob Stoklund Olesen f5eaa8dc62 Allow folded spills in test. 
llvm-svn: 130599
 2011-04-30 08:00:50 +00:00
Jakob Stoklund Olesen edfabc9aad Weekly fix of register allocation dependent unit tests. 
llvm-svn: 130567
 2011-04-30 01:37:52 +00:00
Eli Friedman 4105ed1523 Make FastEmit_ri_ try a bit harder to succeed for supported operations; FastEmit_i can fail for non-Thumb2 ARM. Makes ARMSimplifyAddress work correctly, and reduces the number of fast-isel bailouts on non-Thumb ARM. 
llvm-svn: 130560
 2011-04-29 23:34:52 +00:00
Eli Friedman 328bad02fa Switch to ImmLeaf (which can be used by FastISel) for a few more common ARM/Thumb2 patterns. 
llvm-svn: 130552
 2011-04-29 22:48:03 +00:00
Eli Friedman dd937843d3 Fix run-line, again. :( 
llvm-svn: 130540
 2011-04-29 21:33:03 +00:00
Eli Friedman 86caced370 Re-committing r130454, which does not in fact break anything. 
Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
rdar://problem/9338332 .

llvm-svn: 130539
 2011-04-29 21:22:56 +00:00
Eric Christopher 8d46b47787 Add trunc->branch support, this won't help with clang's i8->i1 truncations 
for bools, but is a start.

llvm-svn: 130534
 2011-04-29 20:02:39 +00:00
Rafael Espindola 697edc89a5 Change DwarfCFIException's member variables to track what it actually 
emmits: .cfi_personality, .cfi_lsda and the moves.

llvm-svn: 130503
 2011-04-29 14:48:51 +00:00
Andrew Trick e794e17524 Teach Thumb2 isel to fold and->rotr ==> ROR. 
Generalization of Nate Begeman's patch!

llvm-svn: 130502
 2011-04-29 14:18:15 +00:00
Andrew Trick 65266ed4d7 Combine thumb2-ror tests. 
llvm-svn: 130498
 2011-04-29 14:02:41 +00:00
Eli Friedman 517728b1ae Revert r130454; apparently this doesn't actually work. 
llvm-svn: 130462
 2011-04-28 23:55:14 +00:00
Eli Friedman 37b9ede969 Fix runline. 
llvm-svn: 130455
 2011-04-28 23:12:24 +00:00
Eli Friedman e4ecd42926 Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register. 
rdar://problem/9338332 .

llvm-svn: 130454
 2011-04-28 23:03:25 +00:00
Eli Friedman 7cd5101ad3 fast-isel sret calls, try 2. We actually do need to do something on x86-32. rdar://problem/9303592 . 
llvm-svn: 130429
 2011-04-28 20:19:12 +00:00