3bb1267431
Use COPY in FastISel everywhere it is safe and trivial.
...
The remaining copyRegToReg calls actually check the return value (shock!), so we
cannot trivially replace them with COPY instructions.
llvm-svn: 108069
2010-07-11 03:31:00 +00:00
a64a323564
Fix a bug in the code which re-inserts DBG_VALUE nodes after scheduling;
...
if a block is split (by a custom inserter), the insert point may be in a
different block than it was originally. This fixes 32-bit llvm-gcc
bootstrap builds, and I haven't been able to reproduce it otherwise.
llvm-svn: 108060
2010-07-10 22:42:31 +00:00
e50d30d586
Emit COPY instructions instead of using copyRegToReg in InstrEmitter,
...
ScheduleDAGEmit, TwoAddressLowering, and PHIElimination.
This switches the bulk of register copies to using COPY, but many less used
copyRegToReg calls remain.
llvm-svn: 108050
2010-07-10 19:08:25 +00:00
fbdba81550
Insert IMPLICIT_DEF instructions at the current insert position, not
...
at the end of the block.
llvm-svn: 108045
2010-07-10 13:55:45 +00:00
d7b5ce3312
Reapply bottom-up fast-isel, with several fixes for x86-32:
...
- Check getBytesToPopOnReturn().
- Eschew ST0 and ST1 for return values.
- Fix the PIC base register initialization so that it doesn't ever
fail to end up the top of the entry block.
llvm-svn: 108039
2010-07-10 09:00:22 +00:00
f831d86311
Clarify what mysterious check means.
...
llvm-svn: 108005
2010-07-09 19:44:12 +00:00
6586e9b203
--- Reverse-merging r107947 into '.':
...
U utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U test/CodeGen/X86/fast-isel.ll
U test/CodeGen/X86/fast-isel-loads.ll
U include/llvm/Target/TargetLowering.h
U include/llvm/Support/PassNameParser.h
U include/llvm/CodeGen/FunctionLoweringInfo.h
U include/llvm/CodeGen/CallingConvLower.h
U include/llvm/CodeGen/FastISel.h
U include/llvm/CodeGen/SelectionDAGISel.h
U lib/CodeGen/LLVMTargetMachine.cpp
U lib/CodeGen/CallingConvLower.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U lib/CodeGen/SelectionDAG/FastISel.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U lib/CodeGen/SelectionDAG/TargetLowering.cpp
U lib/Target/XCore/XCoreISelLowering.cpp
U lib/Target/XCore/XCoreISelLowering.h
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86ISelLowering.h
llvm-svn: 107987
2010-07-09 16:37:18 +00:00
52617fc462
cache result of operator*
...
llvm-svn: 107980
2010-07-09 16:08:33 +00:00
0b5aa1cdd3
Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
...
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.
llvm-svn: 107943
2010-07-09 00:39:23 +00:00
21eed476e8
Reenable DAG combining for vector shuffles. It looks like it was temporarily
...
disabled and then never turned back on again. Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.
llvm-svn: 107941
2010-07-09 00:38:12 +00:00
a992445ff2
Extension of r107506. Make sure that we don't mark a function as having a call
...
if the inline ASM doesn't need a stack frame.
llvm-svn: 107922
2010-07-08 22:38:02 +00:00
00264624a9
Convert EXTRACT_SUBREG to COPY when emitting machine instrs.
...
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.
Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.
llvm-svn: 107879
2010-07-08 16:40:22 +00:00
0ae3f08c0d
Merge the duplicated iabs optimization in DAGCombiner and let it detected a few more idioms.
...
llvm-svn: 107868
2010-07-08 12:09:56 +00:00
e75704369d
Revert 107840 107839 107813 107804 107800 107797 107791.
...
Debug info intrinsics win for now.
llvm-svn: 107850
2010-07-08 01:00:56 +00:00
eb9164dc50
Don't forward-declare registers for static allocas, which we'll
...
prefer to materialize as local constants. This fixes the clang
bootstrap abort.
llvm-svn: 107840
2010-07-07 23:52:58 +00:00
1adc499dda
Fix -fast-isel-abort to check the right instruction.
...
llvm-svn: 107839
2010-07-07 23:47:25 +00:00
1c349f18f8
Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake.
...
llvm-svn: 107820
2010-07-07 22:15:37 +00:00
25d5c1b4f8
Not all custom inserters create new basic blocks. If the inserter
...
didn't create a new block, don't reset the insert position.
llvm-svn: 107813
2010-07-07 21:18:22 +00:00
e7ccc51cc1
Implement bottom-up fast-isel. This has the advantage of not requiring
...
a separate DCE pass over MachineInstrs.
llvm-svn: 107804
2010-07-07 19:20:32 +00:00
2d4d01d0de
Add X86FastISel support for return statements. This entails refactoring
...
a bunch of stuff, to allow the target-independent calling convention
logic to be employed.
llvm-svn: 107800
2010-07-07 18:32:53 +00:00
b792f844ad
Update the insert position after scheduling, which may change the
...
position when emitting multiple blocks when executing a custom
inserter.
llvm-svn: 107797
2010-07-07 18:22:13 +00:00
637ee5f149
Update comment.
...
llvm-svn: 107796
2010-07-07 18:18:18 +00:00
ffe64b1ee5
Give FunctionLoweringInfo an MBB member, avoiding the need to pass it
...
around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.
llvm-svn: 107791
2010-07-07 16:47:08 +00:00
87fb4e8fcd
Simplify FastISel's constructor by giving it a FunctionLoweringInfo
...
instance, rather than pointers to all of FunctionLoweringInfo's
members.
This eliminates an NDEBUG ABI sensitivity.
llvm-svn: 107789
2010-07-07 16:29:44 +00:00
e784616fbb
Move FunctionLoweringInfo.h out into include/llvm/CodeGen. This will
...
allow target-specific fast-isel code to make use of it directly.
llvm-svn: 107787
2010-07-07 16:01:37 +00:00
fe7532a308
Split the SDValue out of OutputArg so that SelectionDAG-independent
...
code can do calling-convention queries. This obviates OutputArgReg.
llvm-svn: 107786
2010-07-07 15:54:55 +00:00
498e5f899d
Move CallingConvLower.cpp out of the SelectionDAG directory.
...
llvm-svn: 107781
2010-07-07 15:15:27 +00:00
dc0a0659be
By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather
...
than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.
llvm-svn: 107734
2010-07-06 23:44:52 +00:00
ee0cb70381
CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.
...
SelectBasicBlock doesn't needs its BasicBlock argument.
llvm-svn: 107712
2010-07-06 22:19:37 +00:00
a3ca21b228
Propagate debug loc.
...
llvm-svn: 107710
2010-07-06 22:08:15 +00:00
3439629239
Reapply r107655 with fixes; insert the pseudo instruction into
...
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
llvm-svn: 107691
2010-07-06 20:24:04 +00:00
4e49b59dad
Add versions of OutputArgReg, AnalyzeReturn, and AnalyzeCallOperands
...
which do not depend on SelectionDAG.
llvm-svn: 107666
2010-07-06 15:39:54 +00:00
c4a7073db3
more tidying.
...
llvm-svn: 107615
2010-07-05 05:53:14 +00:00
2c0315a0f3
random tidying
...
llvm-svn: 107612
2010-07-05 05:36:21 +00:00
f3aeb2c22c
Infer alignments of fixed frame objects when they are constructed. This ensures remat'ed loads from fixed slots have the right alignments.
...
llvm-svn: 107591
2010-07-04 18:52:05 +00:00
f844642350
Proper indentation.
...
llvm-svn: 107581
2010-07-04 08:58:43 +00:00
4d887f7ca7
Propagate the AlignStack bit in InlineAsm's to the
...
PrologEpilog code, and use it to determine whether
the asm forces stack alignment or not. gcc consistently
does not do this for GCC-style asms; Apple gcc inconsistently
sometimes does it for asm blocks. There is no
convenient place to put a bit in either the SDNode or
the MachineInstr form, so I've added an extra operand
to each; unlovely, but it does allow for expansion for
more bits, should we need it. PR 5125. Some
existing testcases are affected.
The operand lists of the SDNode and MachineInstr forms
are indexed with awesome mnemonics, like "2"; I may
fix this someday, but not now. I'm not making it any
worse. If anyone is inspired I think you can find all
the right places from this patch.
llvm-svn: 107506
2010-07-02 20:16:09 +00:00
9b7755fbc6
80-column and trailing whitespace cleanup.
...
llvm-svn: 107490
2010-07-02 17:41:59 +00:00
64a4f3f062
grammar tweaks
...
llvm-svn: 107489
2010-07-02 17:38:34 +00:00
93f5920914
Rename CreateReg to CreateRegs, and MakeReg to CreateReg.
...
llvm-svn: 107451
2010-07-02 00:10:16 +00:00
d2965c10a1
Temporarily disable on-demand fast-isel.
...
llvm-svn: 107393
2010-07-01 12:15:30 +00:00
42b7ee15f5
Use FuncInfo's isExportedInst accessor method instead of
...
doing the work manually.
llvm-svn: 107384
2010-07-01 03:57:05 +00:00
85e02e9340
Rename CreateRegForValue to CreateReg, and change its argument
...
from a Value to a Type, because it doesn't actually care about
the Value.
llvm-svn: 107383
2010-07-01 03:55:39 +00:00
aef3d140b7
Teach fast-isel to avoid loading a value from memory when it's already
...
available in a register. This is pretty primitive, but it reduces the
number of instructions in common testcases by 4%.
llvm-svn: 107380
2010-07-01 03:49:38 +00:00
722f5fc567
Enable on-demand fast-isel.
...
llvm-svn: 107377
2010-07-01 02:58:57 +00:00
d432223163
Reapply r106422, splitting the code for materializing a value out of
...
SelectionDAGBuilder::getValue into a helper function, with fixes to
use DenseMaps safely.
llvm-svn: 107371
2010-07-01 01:59:43 +00:00
9576645a84
Don't use operator[] here, because it's not desirable to insert a default
...
value if the search fails.
llvm-svn: 107368
2010-07-01 01:33:21 +00:00
caf9b3ab7d
grammar tweak in comment.
...
llvm-svn: 107321
2010-06-30 21:27:56 +00:00
945a347478
Remove an unused variable. The call to getRoot has side-effects, so
...
this could break something (but doesn't seem to).
llvm-svn: 107295
2010-06-30 17:22:28 +00:00
647d9c9797
use ArgOperand API
...
llvm-svn: 107282
2010-06-30 13:45:50 +00:00
f69acfe133
use ArgOperand API
...
llvm-svn: 107279
2010-06-30 12:55:46 +00:00
38a7d7cbc3
Add a VT argument to getMinimalPhysRegClass and replace the copy related uses
...
of getPhysicalRegisterRegClass with it.
If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.
llvm-svn: 107140
2010-06-29 14:02:34 +00:00
6d28e73acc
Remove initialized but otherwise unused variables.
...
llvm-svn: 107127
2010-06-29 11:22:26 +00:00
269a89fd3a
Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so they
...
can't be changed arbitrarily by the DAGCombiner without checking if it is
running after legalization.
llvm-svn: 107097
2010-06-28 23:40:25 +00:00
17feb07c53
In asm's, output operands with matching input constraints
...
have to be registers, per gcc documentation. This affects
the logic for determining what "g" should lower to. PR 7393.
A couple of existing testcases are affected.
llvm-svn: 107079
2010-06-28 22:09:45 +00:00
2041abd958
When splitting a VAARG, remember its alignment.
...
This produces terrible but correct code.
llvm-svn: 106952
2010-06-26 18:22:20 +00:00
02b184de5b
Change if-conversion block size limit checks to add some flexibility.
...
llvm-svn: 106901
2010-06-25 22:42:03 +00:00
ce97d55ad9
The hasMemory argument is irrelevant to how the argument
...
for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
llvm-svn: 106893
2010-06-25 21:55:36 +00:00
2dc70bea54
Remove variables which are assigned to but for which the value
...
is not used. Spotted by gcc-4.6.
llvm-svn: 106854
2010-06-25 14:48:39 +00:00
eba0be7dc9
use ArgOperand API
...
llvm-svn: 106836
2010-06-25 09:38:13 +00:00
e4eed709d4
use ArgOperand API
...
llvm-svn: 106828
2010-06-25 08:24:59 +00:00
f6207e0a80
prune an include
...
llvm-svn: 106827
2010-06-25 08:16:50 +00:00
2d3c490026
It's possible that a flag is added to the SDNode that points back to the
...
original SDNode. This is badness. Also, this function allows one SDNode to point
multiple flags to another SDNode. Badness as well.
llvm-svn: 106793
2010-06-24 22:00:37 +00:00
8a84cd57ae
Simplify this code; switch lowering shouldn't produce cases
...
which trivially fold away.
llvm-svn: 106765
2010-06-24 17:08:31 +00:00
463f26b4be
Eliminate the other half of the BRCOND optimization, and update
...
as many tests as possible.
llvm-svn: 106749
2010-06-24 15:24:03 +00:00
df6b33e778
Eliminate the first have of the optimization which eliminates BRCOND
...
when the condition is constant. This optimization shouldn't be
necessary, because codegen shouldn't be able to find dead control
paths that the IR-level optimizer can't find. And it's undesirable,
because it encourages bugpoint to leave "br i1 false" branches
in its output. And it wasn't updating the CFG.
I updated all the tests I could, but some tests are too reduced
and I wasn't able to meaningfully preserve them.
llvm-svn: 106748
2010-06-24 15:04:11 +00:00
600f62b3ba
Reapply r106634, now that the bug it exposed is fixed.
...
llvm-svn: 106746
2010-06-24 14:30:44 +00:00
0695e09b09
Optimize the "bit test" code path for switch lowering in the
...
case where the bit mask has exactly one bit.
llvm-svn: 106716
2010-06-24 02:06:24 +00:00
a136521a17
MorphNodeTo doesn't preserve the memory operands. Because we're morphing a node
...
into the same node, but with different non-memory operands, we need to replace
the memory operands after it's finished morphing.
llvm-svn: 106643
2010-06-23 18:16:24 +00:00
4df321b7ad
Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.
...
llvm-svn: 106634
2010-06-23 17:09:26 +00:00
b58c08b0ba
Some targets don't require the fencing MEMBARRIER instructions surrounding
...
atomic intrinsics, either because the use locking instructions for the
atomics, or because they perform the locking directly. Add support in the
DAG combiner to fold away the fences.
llvm-svn: 106630
2010-06-23 16:07:42 +00:00
dd41bba517
Use A.append(...) instead of A.insert(A.end(), ...) when A is a
...
SmallVector, and other SmallVector simplifications.
llvm-svn: 106452
2010-06-21 19:47:52 +00:00
bbc29ea821
Revert r106422, which is breaking the non-fast-isel path.
...
llvm-svn: 106423
2010-06-21 16:02:28 +00:00
f64fdd69d0
More changes for non-top-down fast-isel.
...
Split the code for materializing a value out of
SelectionDAGBuilder::getValue into a helper function, so that it can
be used in other ways. Add a new getNonRegisterValue function which
uses it, for use in code which doesn't want a CopyFromReg even
when FuncMap.ValueMap already has an entry for it.
llvm-svn: 106422
2010-06-21 15:13:54 +00:00
f91aff5f13
Do one lookup instead of two.
...
llvm-svn: 106415
2010-06-21 14:21:47 +00:00
7c58cf75fa
Generalize this to look in the regular ValueMap in addition to
...
the LocalValueMap, to make it more flexible when fast-isel isn't
proceding straight top-down.
llvm-svn: 106414
2010-06-21 14:17:46 +00:00
8693650422
Teach regular and fast isel to set dead flags on unused implicit defs
...
on calls and similar instructions.
llvm-svn: 106353
2010-06-18 23:28:01 +00:00
a57c2885cf
back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)
...
llvm-svn: 106342
2010-06-18 23:03:10 +00:00
f5d62535a5
Fix cross initialization compilation error.
...
llvm-svn: 106324
2010-06-18 22:01:37 +00:00
d64dfc1568
Add Expand-to-libcall support for additional atomics. This covers the usual
...
entries used by llvm-gcc. *_[U]MIN and such can be added later if needed.
This enables the front ends to simplify handling of the atomic intrinsics by
removing the target-specific decision about which targets can handle the
intrinsics.
llvm-svn: 106321
2010-06-18 21:43:38 +00:00
7edb39cc6b
Minor code simplifications.
...
llvm-svn: 106286
2010-06-18 16:00:29 +00:00
6e681a5fbe
Give NamedRegionTimer an Enabled flag, allowing all its clients to
...
switch from this:
if (TimePassesIsEnabled) {
NamedRegionTimer T(Name, GroupName);
do_something();
} else {
do_something(); // duplicate the code, this time without a timer!
}
to this:
{
NamedRegionTimer T(Name, GroupName, TimePassesIsEnabled);
do_something();
}
llvm-svn: 106285
2010-06-18 15:56:31 +00:00
96ca25eba5
Don't replace the old Ordering object with a new one; just clear()
...
the old one.
llvm-svn: 106284
2010-06-18 15:40:58 +00:00
a4f46b3ef8
Don't call clear() on DbgInfo when it's going to be deleted anyway.
...
Don't replace the old DbgInfo with a new one when clear() on the
old one is sufficient.
llvm-svn: 106283
2010-06-18 15:36:18 +00:00
92c11acdb8
Change UpdateNodeOperands' operand and return value from SDValue to
...
SDNode *, since it doesn't care about the ResNo value.
llvm-svn: 106282
2010-06-18 15:30:29 +00:00
f1d8304fe3
Eliminate unnecessary uses of getZExtValue().
...
llvm-svn: 106279
2010-06-18 14:22:04 +00:00
35b6f9a929
isValueValidForType can be a static member function.
...
llvm-svn: 106278
2010-06-18 14:01:07 +00:00
b92156d5e4
Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,
...
which is faster, simpler, and less surprising.
llvm-svn: 106263
2010-06-18 01:05:21 +00:00
0883789ec4
Handle ext(ext(x)) -> ext(x) immediately, since it's simple.
...
llvm-svn: 106256
2010-06-18 00:08:30 +00:00
0125b6410a
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
...
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.
This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.
llvm-svn: 106243
2010-06-17 22:43:56 +00:00
0ed5b460dc
add missing break. inconsequential as the code shouldn't be reached, but
...
for correctness' sake, it should be there.
llvm-svn: 106229
2010-06-17 17:58:54 +00:00
3aeae8aeeb
Add entries for Expanding atomic intrinsics to libcalls. Just a placeholder
...
for the moment. The implementation of the libcall will follow.
Currently, the llvm-gcc knows when the intrinsics can be correctly handled by
the back end and only generates them in those cases, issuing libcalls directly
otherwise. That's too much coupling. The intrinsics should always be
generated and the back end decide how to handle them, be it with a libcall,
inline code, or whatever. This patch is a step in that direction.
rdar://8097623
llvm-svn: 106227
2010-06-17 17:50:54 +00:00
ba451e80dc
ISD::MEMBARRIER should lower to a libcall (__sync_synchronize) if the target
...
sets the legalize action to Expand.
llvm-svn: 106203
2010-06-17 02:00:53 +00:00
7a84689cc5
Fixed vector widening of binary instructions that can trap. Patch by Visa Putkinen!
...
llvm-svn: 106038
2010-06-15 20:29:05 +00:00
38f6560461
Code refactoring, no functionality changes.
...
llvm-svn: 105775
2010-06-10 02:09:31 +00:00
8bc5eca331
Mark physregs defined by inline asm as implicit.
...
This is a bit of a hack to make inline asm look more like call instructions.
It would be better to produce correct dead flags during isel.
llvm-svn: 105749
2010-06-09 20:05:00 +00:00
a13b1c29b0
Add argument name comments.
...
llvm-svn: 105665
2010-06-09 00:40:31 +00:00
622cdd2297
Fixed a bug during widening where we would avoid legalizing a node. When we
...
replace an OpA with a widened OpB, it is possible to get new uses of OpA due to CSE
when recursively updating nodes. Since OpA has been processed, the new uses are
not examined again. The patch checks if this occurred and it it did, updates the
new uses of OpA to use OpB.
llvm-svn: 105453
2010-06-04 01:20:10 +00:00
d83e3e7750
Fix SimplifyDemandedBits' AssertZext logic to demand all the bits. It
...
needs to demand the high bits because it's asserting that they're zero.
llvm-svn: 105406
2010-06-03 20:21:33 +00:00
dbbbf73c96
Implement expansion in type legalization for add/sub with overflow. The
...
expansion is the same as that used by LegalizeDAG.
The resulting code sucks in terms of performance/codesize on x86-32 for a
64-bit operation; I haven't looked into whether different expansions might be
better in general.
llvm-svn: 105378
2010-06-03 03:49:50 +00:00
b0c76394a3
Keep track of incoming debug value of unused argument.
...
Radar 7927666.
llvm-svn: 105285
2010-06-01 19:59:01 +00:00
b782caa393
Fill in missing support for ISD::FEXP, ISD::FPOWI, and friends.
...
llvm-svn: 105283
2010-06-01 18:35:14 +00:00
14c46517b5
fix PR6623: when optimizing for size, don't inline memcpy/memsets
...
that are too large. This causes the freebsd bootloader to be too
large apparently.
It's unclear if this should be an -Os or -Oz thing. Thoughts welcome.
llvm-svn: 105228
2010-05-31 17:30:14 +00:00
b4a773b452
the 'limit' argument to FindOptimalMemOpLowering is unsigned, not uint64_t.
...
llvm-svn: 105226
2010-05-31 17:12:23 +00:00
a97311f152
Use `llvm::next' instead of `next' to make VC++ 2010 happy.
...
llvm-svn: 105168
2010-05-30 13:14:21 +00:00
4db93c9700
Reorder some code in SelectionDAGBuilder.
...
llvm-svn: 105105
2010-05-29 17:53:24 +00:00
d16aa541af
SelectionDAG shouldn't have a FunctionLoweringInfo member. RegsForValue
...
shouldn't have a TargetLoweringInfo member. And FunctionLoweringInfo::set
doesn't needs its EnableFastISel argument.
llvm-svn: 105101
2010-05-29 17:03:36 +00:00
cc2efe11db
Fix some latency computation bugs: if the use is not a machine opcode do not just return zero.
...
llvm-svn: 105061
2010-05-28 23:26:21 +00:00
2140a74979
Eliminate the restriction that the array size in an alloca must be i32.
...
This will help reduce the amount of casting required on 64-bit targets.
llvm-svn: 104911
2010-05-28 01:14:11 +00:00
faa3abbe39
Update the saved stack pointer in the sjlj function context following either
...
an alloca() or an llvm.stackrestore(). rdar://8031573
llvm-svn: 104900
2010-05-27 23:49:24 +00:00
c9f532dddc
back out 104862/104869. Can reuse stacksave after all. Very cool.
...
llvm-svn: 104897
2010-05-27 23:11:57 +00:00
b68dfb45f5
hook ISD::STACKADDR to an intrinsic
...
llvm-svn: 104869
2010-05-27 18:52:11 +00:00
ddee3cb163
Add FIXME comment to remove this.
...
llvm-svn: 104749
2010-05-26 21:53:50 +00:00
27311269cb
Add "setjmp_syscall", "savectx", "qsetjmp", "vfork", "getcontext" to the list of
...
usual suspects that could "return twice".
llvm-svn: 104737
2010-05-26 20:39:00 +00:00
c98892fdaa
Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in
...
ISD::. No functional change.
llvm-svn: 104734
2010-05-26 20:22:18 +00:00
1b08572a66
Update debug info when live-in reg is copied into a vreg.
...
llvm-svn: 104732
2010-05-26 20:18:50 +00:00
0c3bfd3fb0
Move the check for "calls setjmp" to SelectionDAGISel so that it can be used by
...
more than just the stack slot coloring algorithm.
llvm-svn: 104722
2010-05-26 19:46:12 +00:00
52c2738324
Eliminate the use of PriorityQueue and just use a std::vector,
...
implementing pop with a linear search for a "best" element. The priority
queue was a neat idea, but in practice the comparison functions depend
on dynamic information.
llvm-svn: 104718
2010-05-26 18:52:00 +00:00
1e5d0b0456
Delete an unused function.
...
llvm-svn: 104716
2010-05-26 18:34:12 +00:00
e805ea9e39
Temporarily revert r104655 as it's breaking the bots.
...
llvm-svn: 104664
2010-05-26 01:59:55 +00:00
7c00576a62
Change push_all to a non-virtual function and implement it in the
...
base class, since all the implementations are the same.
llvm-svn: 104659
2010-05-26 01:10:55 +00:00
3701b3928e
Trim #include.
...
llvm-svn: 104657
2010-05-26 00:55:59 +00:00
c5222d6c38
Dale and Evan suggested putting the "check for setjmp" much earlier in the
...
machine code generation. That's a good idea, so I made it so.
llvm-svn: 104655
2010-05-26 00:32:40 +00:00
ce3269b815
Do one map lookup instead of two.
...
llvm-svn: 104645
2010-05-25 21:59:42 +00:00
60fe2cdc4f
Fix another variant of PR 7191. Also add a testcase
...
Mon Ping provided; unfortunately bugpoint failed to
reduce it, but I think it's important to have a test for
this in the suite. 8023512.
llvm-svn: 104624
2010-05-25 18:47:23 +00:00
ff384ad981
Fix PR 7191. I have been unable to create a .ll file that fails, sorry.
...
(oye, a word which should be better known to people writing tree
traversals, means grandchild.)
llvm-svn: 104619
2010-05-25 17:50:03 +00:00
bd9485db63
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
...
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
llvm-svn: 104419
2010-05-22 01:06:18 +00:00
61438fe064
Clean up extra whitespace.
...
llvm-svn: 104410
2010-05-21 23:53:55 +00:00
51d9ee3ff6
Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements
...
so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.
llvm-svn: 104380
2010-05-21 21:05:32 +00:00
725211e948
Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.
...
llvm-svn: 104306
2010-05-21 00:42:32 +00:00
4401f8873c
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
...
llvm-svn: 104293
2010-05-20 23:26:43 +00:00
bdd062dae0
Add a hybrid bottom up scheduler that reduce register usage while avoiding
...
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.
llvm-svn: 104216
2010-05-20 06:13:19 +00:00
42603958fb
Optimize away insertelement of an undef value. This shows up in
...
test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up. Radar 7998853.
llvm-svn: 104185
2010-05-19 23:42:58 +00:00
70e506e18a
Code clean up.
...
llvm-svn: 104173
2010-05-19 22:42:23 +00:00
738e920edf
Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
...
llvm-svn: 104147
2010-05-19 20:19:50 +00:00
6a1bfd282b
When expanding a vector_shuffle, the element type may not be legal and may
...
need to be promoted. The BUILD_VECTOR and EXTRACT_VECTOR_ELT nodes generated
here already allow the promoted type to be used without further changes, so
just do the promotion. This fixes part of pr7167.
llvm-svn: 104141
2010-05-19 18:48:32 +00:00
abd0ad54a4
Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.
...
The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.
Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.
llvm-svn: 104094
2010-05-19 01:08:17 +00:00
f19384d54a
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
...
llvm-svn: 104060
2010-05-18 21:31:17 +00:00
45b3f702ab
Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices.
...
llvm-svn: 104051
2010-05-18 20:07:47 +00:00
e7fc64a5c9
Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE.
...
llvm-svn: 104050
2010-05-18 20:03:28 +00:00
48f0de96d6
FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)).
...
llvm-svn: 104004
2010-05-18 00:03:40 +00:00
02d3368831
- Set the "HasCalls" flag after instruction selection is finished.
...
- Change the logic DisableFramePointerElim() to check for the
-disable-non-leaf-fp-elim before -disable-fp-elim.
llvm-svn: 103990
2010-05-17 23:09:50 +00:00
3a366a88f2
Fix uint64->{float, double} conversion to do rounding correctly in 32-bit.
...
The implementation in LegalizeIntegerTypes to handle this as
sint64->float + appropriate power of 2 is subject to double rounding,
considered incorrect by numerics people. Use this implementation only
when it is safe. This leads to using library calls in some cases
that produced inline code before, but it's correct now.
(EVTToAPFloatSemantics belongs somewhere else, any suggestions?)
Add a correctly rounding (though not particularly fast) conversion
that uses X87 80-bit computations for x86-32.
7885399, 5901940. This shows up in gcc.c-torture/execute/ieee/rbug.c
in the gcc testsuite on some platforms.
llvm-svn: 103883
2010-05-15 18:51:12 +00:00
bb4656c05e
Improve assertion messages.
...
llvm-svn: 103882
2010-05-15 18:38:02 +00:00
88fb253562
Fast ISel trivially coalesces away no-op casts, so check for this when
...
setting kill flags.
llvm-svn: 103832
2010-05-14 22:53:18 +00:00
2f277c866d
Don't set kill flags for instructions which the scheduler has cloned.
...
llvm-svn: 103827
2010-05-14 22:01:14 +00:00
95f6ebcb37
Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what
...
the variable actually tracks.
N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.
llvm-svn: 103802
2010-05-14 21:14:32 +00:00
1ae94b9394
Implement a correct ui64->f32 conversion. The old
...
one was subject to double rounding in extreme cases.
llvm-svn: 103744
2010-05-13 23:50:42 +00:00
5b510c1474
An Instruction has a trivial kill only if its use is in the same
...
basic block.
llvm-svn: 103725
2010-05-13 19:19:32 +00:00
1a1b51ff59
Add initial kill flag support to FastISel.
...
llvm-svn: 103529
2010-05-11 23:54:07 +00:00
afd2b8bbb7
Don't set kill flags on uses of CopyFromReg nodes. InstrEmitter doesn't
...
create separate virtual registers for CopyFromReg values, so uses of
them don't necessarily kill the value.
llvm-svn: 103519
2010-05-11 21:59:14 +00:00
6c5e4355bb
I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it
...
to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.
llvm-svn: 103495
2010-05-11 20:16:09 +00:00
9132c59d43
Trim #includes and forward declarations.
...
llvm-svn: 103489
2010-05-11 19:11:43 +00:00
bb919dfb6b
Implement a bunch more TargetSelectionDAGInfo infrastructure.
...
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.
llvm-svn: 103481
2010-05-11 17:31:57 +00:00
6739a89117
Fixes for Microsoft Visual Studio 2010, from Steven Watanabe!
...
llvm-svn: 103457
2010-05-11 06:17:44 +00:00
ffb9f18dfe
Indentation.
...
llvm-svn: 103441
2010-05-10 23:08:19 +00:00
02947a4551
Be careful with operand promotion. For a binary operation, the source operands may be the same. PR7018. rdar://7939869.
...
llvm-svn: 103419
2010-05-10 19:03:57 +00:00
e4d6670f6b
Add an assertion to catch attempts to access off the end of the array.
...
Based on a patch by Javier Martinez.
llvm-svn: 103391
2010-05-10 04:54:28 +00:00
7de01ec2c9
SDDbgValues are apparently not being legalized. Fix a symptom of the problem,
...
and not the real problem itself, by dropping debug info for i128 values.
rdar://7958162.
llvm-svn: 103310
2010-05-07 22:19:08 +00:00
2ae3397536
Verify variable directly.
...
llvm-svn: 103305
2010-05-07 22:04:20 +00:00
51c1695a0a
Fix PR 7087, and probably other things, by extending
...
getConstantFP to accept the two supported long double
target types. This was not the original intent, but
there are other places that assume this works and it's
easy enough to do.
llvm-svn: 103299
2010-05-07 21:35:53 +00:00
e6d40166a8
Transfer debug location information from PHI nodes to resulting
...
lowered copies.
llvm-svn: 103228
2010-05-07 01:10:20 +00:00
e7dff14d5d
Print debug information for SDNodes.
...
llvm-svn: 103227
2010-05-07 01:09:21 +00:00
779c69bbc5
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
...
doesn't have to guess.
llvm-svn: 103194
2010-05-06 20:33:48 +00:00
a7c717d8d4
In bottom-up mode, defer the materialization of local constant values.
...
llvm-svn: 103139
2010-05-06 00:02:14 +00:00
ffcb590b0f
Add an "IsBottomUp" member function to FastISel, which will be used to
...
support a new bottom-up mode.
llvm-svn: 103138
2010-05-05 23:58:35 +00:00
92b21cad5d
Use getValue() for PHINodes when direct NodeMap access does not work.
...
llvm-svn: 103126
2010-05-05 22:29:00 +00:00
55869af998
Instruction selection optimizations may have moved the def of a function argument out of the entry block. rdar://7937489
...
llvm-svn: 102993
2010-05-04 00:58:39 +00:00
f869d9adf2
Teach scheduler about REG_SEQUENCE.
...
llvm-svn: 102984
2010-05-04 00:22:40 +00:00
0e79c864c3
Re-enable isel kill flags, now that the local allocator is ignoring them.
...
llvm-svn: 102981
2010-05-04 00:12:15 +00:00
626b5d8e0c
Factor out FastISel's code for materializing constants and other values
...
in registers into a separate function to de-couple it from the
top-down-specific logic in getRegForValue.
llvm-svn: 102975
2010-05-03 23:36:34 +00:00
737718d4f4
Insert ANY_EXTEND node instead of invalid truncate during DAG Combining (X & 1),
...
when needed. This fixes PR7001
llvm-svn: 102838
2010-05-01 12:52:34 +00:00
ec74444d3e
Remove the code for special-casing byval for fast-isel. SelectionDAG
...
handles argument lowering anyway, so there's no need for special
casing here.
llvm-svn: 102828
2010-05-01 02:44:23 +00:00
4959cf19b2
Re-disable kill flags, as there is more trouble.
...
llvm-svn: 102826
2010-05-01 01:57:56 +00:00
77ef6f6a17
Re-enable kill flags from SelectionDAGISel, with a fix: don't
...
try to put a kill flag on a DBG_INFO instruction.
llvm-svn: 102820
2010-05-01 00:50:53 +00:00
096619eb52
Fix whitespace.
...
llvm-svn: 102817
2010-05-01 00:33:28 +00:00
63f31115cd
Don't pass SDValues by non-const reference unless they may be
...
modified.
llvm-svn: 102816
2010-05-01 00:33:16 +00:00
5d059718c9
Reorgnaize more switch code lowering to clean up some tricky
...
code, and to eliminate the need for the SelectionDAGBuilder
state to be live during CodeGenAndEmitDAG calls.
Call SDB->clear() before CodeGenAndEmitDAG calls instead of
before it, and move the CurDAG->clear() out of SelectionDAGBuilder,
which doesn't own the DAG, and into CodeGenAndEmitDAG.
llvm-svn: 102814
2010-05-01 00:25:44 +00:00
f0514717cd
Delete the EdgeMapping variable itself.
...
llvm-svn: 102810
2010-05-01 00:02:20 +00:00
25c1653700
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
...
changes before doing phi lowering for switches.
llvm-svn: 102809
2010-05-01 00:01:06 +00:00
de4b225093
EXTRACT_VECTOR_ELT of an INSERT_VECTOR_ELT may have the same index, but the
...
indexes could be of a different value type. Or not even using the same SDNode
for the constant (weird, I know). Compare the actual values instead of the
pointers.
llvm-svn: 102791
2010-04-30 22:19:17 +00:00
09452cecd8
Remove this debug output. The MachineFunction will be printed once all of
...
instruction selection is done; it's confusing to see parts of it printed,
while other parts are omitted, along the way.
llvm-svn: 102771
2010-04-30 21:21:21 +00:00
8acc8f7dfd
EmitDbgValue doesn't need its EdgeMapping argument.
...
llvm-svn: 102742
2010-04-30 19:35:33 +00:00
e82c25e878
Apply a patch from Jan Sjodin to fix a compiler abort on vector
...
comparisons sign-extended to a different bitwidth than the
comparison operands.
llvm-svn: 102721
2010-04-30 17:19:19 +00:00
587e0800e5
Temporarily disable SelectionDAG kill flags, which are causing trouble.
...
llvm-svn: 102680
2010-04-30 00:32:51 +00:00
ac55510c4e
Set register kill flags on the SelectionDAG path, at least in the
...
easy cases.
llvm-svn: 102678
2010-04-30 00:08:21 +00:00
0395553e35
Refactor.
...
llvm-svn: 102661
2010-04-29 20:40:36 +00:00
a46953d281
DO not push DBG_VALUE machine instructions for inlined fuction arguments in entry block.
...
llvm-svn: 102653
2010-04-29 18:50:36 +00:00
5c864b42b2
Add comment.
...
llvm-svn: 102606
2010-04-29 06:58:53 +00:00
923679f929
Re-enable 102565 with fixes.
...
llvm-svn: 102602
2010-04-29 06:33:38 +00:00
d65a1e782b
Temporarily disable my changes to unbreak the build.
...
llvm-svn: 102590
2010-04-29 03:34:19 +00:00
5fb45a2b85
Do not generate duplicate dbg_value instructions for function arguments.
...
llvm-svn: 102585
2010-04-29 01:40:30 +00:00
d9e7322c9a
Fix missing #include.
...
llvm-svn: 102584
2010-04-29 01:39:13 +00:00
70a0145d7c
Avoid emitting a dbg_value machineinstr that's not going to be inserted into entry block.
...
llvm-svn: 102581
2010-04-29 01:23:55 +00:00
f4336ebb2a
Check Reg against zero.
...
llvm-svn: 102573
2010-04-29 00:59:34 +00:00
bb728e17d3
tidy up.
...
llvm-svn: 102558
2010-04-28 23:24:13 +00:00
6e822459ed
Replace r102368 with code that's less fragile. This creates DBG_VALUE instructions for function arguments early and insert them after instruction selection is done.
...
llvm-svn: 102554
2010-04-28 23:08:54 +00:00
888c17073a
While lowering dbg_declare, emit DBG_VALUE machine instruction if alloca matching llvm.dbg.declare intrinsic is missing.
...
llvm-svn: 102513
2010-04-28 19:27:33 +00:00
f100557c9a
Try operation promotion only if regular dag combine and target-specific ones failed to do anything.
...
llvm-svn: 102492
2010-04-28 07:10:39 +00:00
1a0bbe25e3
Ignore DBG_VALUE instructions that points to undef values.
...
llvm-svn: 102463
2010-04-27 20:54:45 +00:00
e813690b7a
- When legal, promote a load to zextload rather than ext load.
...
- Catch more further dag combine opportunities as result of operand promotion, e.g. (i32 anyext (i16 trunc (i32 x))) -> (i32 x)
llvm-svn: 102455
2010-04-27 19:48:13 +00:00
eb61a7d616
Revert a small part of 102372; this fixes at least one
...
of the dbg testsuite regressions. I don't think this is
really the right fix; this change exposed an existing problem
upstream somewhere.
llvm-svn: 102410
2010-04-27 02:10:05 +00:00
a1e343095f
Avoid adding a null MD node operand, which crashes with "-debug" when trying
...
to print the operand.
llvm-svn: 102395
2010-04-26 22:56:56 +00:00
59a438560c
Remove crufty comments.
...
llvm-svn: 102380
2010-04-26 20:48:54 +00:00
e098352ed1
Add DBG_VALUE handling for byval parameters; this
...
produces a comment on targets that support it, but
the Dwarf writer is not hooked up yet.
llvm-svn: 102372
2010-04-26 20:06:49 +00:00
ed69b382ea
- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
...
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.
llvm-svn: 102323
2010-04-26 07:38:55 +00:00
582565e991
Stop abusing EmitInstrWithCustomInserter for target-dependent
...
form of DEBUG_VALUE, as it doesn't have reasonable default
behavior for unsupported targets. Add a new hook instead.
No functional change.
llvm-svn: 102320
2010-04-25 21:33:54 +00:00
1fc01985a3
Add comment re byval args. Doesn't actually work this way yet.
...
xs
llvm-svn: 102316
2010-04-25 21:03:54 +00:00
0abb54d631
When a load operand is promoted to an extload, replace other uses with uses of extload result truncated.
...
llvm-svn: 102236
2010-04-24 04:43:44 +00:00
5544b0c588
Apply a fix for a vector setcc dagcombine from Jan Sjodin. No
...
testcase yet, as the testcase now fails downstream.
llvm-svn: 102228
2010-04-24 01:17:30 +00:00
b9ff130d47
Code refactoring.
...
llvm-svn: 102202
2010-04-23 19:10:30 +00:00
6e9a8fcc28
Move FastISel's HandlePHINodesInSuccessorBlocks call down into FastISel
...
itself too.
llvm-svn: 102176
2010-04-23 15:29:50 +00:00
5b43aa0ddd
Sink SelectionDAGBuilder's HandlePHINodesInSuccessorBlocks down
...
into SelectionDAGBuilder itself.
llvm-svn: 102128
2010-04-22 20:55:53 +00:00
c594eab10f
Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel
...
and into SelectionDAGBuilder and FastISel.
llvm-svn: 102123
2010-04-22 20:46:50 +00:00
f1223bdec0
- It's not safe to promote rotates (at least not trivially).
...
- Some code refactoring.
llvm-svn: 102111
2010-04-22 20:19:46 +00:00
e149e9896c
Fix a comment.
...
llvm-svn: 102110
2010-04-22 20:06:42 +00:00
fd81254190
Move PHINodesToUpdate out of SelectionDAGBuilder and into
...
FunctionLoweringInfo, as it isn't SelectionDAG-specific. This isn't
completely natural, as PHI node state is not per-function but rather
per-basic-block, however there's currently no other convenient
per-basic-block state to group it with.
llvm-svn: 102109
2010-04-22 19:55:20 +00:00
57c732b032
Add more const qualifiers on TargetMachine and friends.
...
llvm-svn: 101977
2010-04-21 01:34:56 +00:00
450aa64fc1
Move several SelectionDAG-independent utility functions out of the
...
SelectionDAG directory and into a new Analysis.cpp file.
llvm-svn: 101975
2010-04-21 01:22:34 +00:00
ad33d33719
Add another variant of this test which found a place where
...
CodeGen's ComputeMaskedBits was being over-conservative when computing
bits for an ADD.
llvm-svn: 101963
2010-04-21 00:19:28 +00:00
0522b90cdb
Because of the EMMS problem, right now we have to support
...
user-defined operations that use MMX register types, but
the compiler shouldn't generate them on its own. This adds
a Synthesizable abstraction to represent this, and changes
the vector widening computation so it won't produce MMX types.
(The motivation is to remove noise from the ABI compatibility
part of the gcc test suite, which has some breakage right now.)
llvm-svn: 101951
2010-04-20 22:34:09 +00:00
950fe784be
Sink the CopyToExportRegsIfNeeded calls out of SelectionDAGISel
...
into SelectionDAGBuilder. This avoids a separate pass over the
instructions, and has the side effect of providing debug location
information to the copy.
llvm-svn: 101906
2010-04-20 15:03:56 +00:00
f41ad478ca
Don't send PHI nodes down to SelectionDAGBuilder of FastISel, since
...
they end up doing nothing.
llvm-svn: 101904
2010-04-20 15:00:41 +00:00
7c845e4ea4
Sink this use_empty() check into isUsedOutsideOfDefiningBlock.
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llvm-svn: 101902
2010-04-20 14:50:13 +00:00
7b7f0883fe
If a PHI node somehow has debug info, propogate it to the MachineInstr PHI.
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llvm-svn: 101901
2010-04-20 14:48:02 +00:00
0f055d3f56
Don't iterate through the whole block just to find the PHI nodes.
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llvm-svn: 101900
2010-04-20 14:46:25 +00:00
0c862a86fa
Delete a redundant return statement.
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llvm-svn: 101860
2010-04-20 01:58:20 +00:00
467e6c2deb
The visitXOR method can return the same SDNode. If so, we don't want to delete
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it as it's not dead.
llvm-svn: 101855
2010-04-20 01:25:01 +00:00
eadc04badc
Remove this debug output; it isn't that useful, and it's incomplete
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in the case where a basic block is split.
llvm-svn: 101850
2010-04-20 00:56:44 +00:00
e450d7444d
Sink DebugLoc handling out of SelectionDAGISel into FastISel and
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SelectionDAGBuilder, where it doesn't have to be as complicated.
llvm-svn: 101848
2010-04-20 00:48:35 +00:00
3df671a81c
Remove MachineFunction's DefaultDebugLoc member, and make DwarfDebug.cpp
...
responsible for figuring out what that's supposed to be on its own.
llvm-svn: 101844
2010-04-20 00:37:27 +00:00
ca35aa1122
Reapply the removal of SelectionDAGISel's BB, with a fix for the case
...
where multiple blocks are emitted; functions which do this need to return
the new BB so that their callers can stay current.
llvm-svn: 101843
2010-04-20 00:29:35 +00:00
be2e727a38
Revert 101825, which is causing trouble.
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llvm-svn: 101832
2010-04-19 23:34:15 +00:00
8cccc542f6
Eliminate SelectionDAGISel's "current block" member. Just pass it as
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an argument to things that need it.
llvm-svn: 101825
2010-04-19 22:51:14 +00:00
7c0303a059
Eliminate the CurMBB member from SelectionDAGBuilder. For places that
...
need it, just pass around the parent block of the current instruction
explicitly.
llvm-svn: 101822
2010-04-19 22:41:47 +00:00
e19aa5cc52
More progress on promoting i16 operations to i32 for x86. Work in progress.
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llvm-svn: 101808
2010-04-19 19:29:22 +00:00
1e95790fd4
Give SelectionDAG a TargetMachine too, rather than having it
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fetch one from the MachineFunction.
llvm-svn: 101807
2010-04-19 19:22:07 +00:00
e7c21a4242
More 80 col violation.
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llvm-svn: 101806
2010-04-19 19:17:44 +00:00
c334960f16
Code that needs a TargetMachine should have access to one directly, rather
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than just getting one through a TargetLowering.
llvm-svn: 101802
2010-04-19 19:05:59 +00:00
a91754da67
Move isInTailCallPosition out of SelectionDAGBuilder, as it isn't
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SelectionDAG-specific.
llvm-svn: 101801
2010-04-19 18:41:46 +00:00
1f0f2142cc
Fix -Wcast-qual warnings.
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llvm-svn: 101655
2010-04-17 17:42:52 +00:00
8422e57baa
Delete now-unnecessary const_casts.
...
llvm-svn: 101637
2010-04-17 15:32:28 +00:00
21cea8ac2e
Use const qualifiers with TargetLowering. This eliminates several
...
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
llvm-svn: 101635
2010-04-17 15:26:15 +00:00
f1bd5fcdb4
More work to allow dag combiner to promote 16-bit ops to 32-bit.
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llvm-svn: 101621
2010-04-17 06:13:15 +00:00
829c300ce0
Another 80 col violation.
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llvm-svn: 101620
2010-04-17 06:12:32 +00:00
7258dcd77f
Revert 101465, it broke internal OpenGL testing.
...
Probably the best way to know that all getOperand() calls have been handled
is to replace that API instead of updating.
llvm-svn: 101579
2010-04-16 23:37:20 +00:00
f037f87bde
(i32 sext_in_reg (i32 aext (i16 x)), i16) -> (i32 sext x). No known test case until -promote-16bit is enabled.
...
llvm-svn: 101551
2010-04-16 22:26:19 +00:00
c4759a5b97
Create a new TargetSelectionDAGInfo class. This will eventually acquire
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SelectionDAG-specific parts of TargetLowering.
llvm-svn: 101537
2010-04-16 21:12:11 +00:00
4d273f4519
Commit this, which should have accompanied 101531.
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llvm-svn: 101532
2010-04-16 20:22:43 +00:00
954bd598dd
80 col.
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llvm-svn: 101501
2010-04-16 17:58:41 +00:00
d6b0a7c075
80 col.
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llvm-svn: 101500
2010-04-16 17:57:59 +00:00
3a7ee8eead
Avoid creating virtual registers for unused values.
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llvm-svn: 101480
2010-04-16 17:15:02 +00:00
5664b9f1a9
Fix an assertion string.
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llvm-svn: 101478
2010-04-16 16:55:18 +00:00
4572a9f479
Fix a comment.
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llvm-svn: 101477
2010-04-16 16:52:37 +00:00
f375520f7b
reapply r101434
...
with a fix for self-hosting
rotate CallInst operands, i.e. move callee to the back
of the operand array
the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary
llvm-svn: 101465
2010-04-16 15:33:14 +00:00
af56facacd
Adding support for dag combiner to promote operations for profit. This requires target specific queries. For example, x86 should promote i16 to i32 when it does not impact load folding.
...
x86 support is off by default. It can be enabled with -promote-16bit.
Work in progress.
llvm-svn: 101448
2010-04-16 06:14:10 +00:00
5563473062
Refine further the scope where the global DebugLoc value is active.
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llvm-svn: 101443
2010-04-16 05:06:56 +00:00
403e9694f9
back out r101423 and r101397, they break llvm-gcc self-host on darwin10
...
llvm-svn: 101434
2010-04-16 01:16:20 +00:00
33ae80bff7
reapply r101364, which has been backed out in r101368
...
with a fix
rotate CallInst operands, i.e. move callee to the back
of the operand array
the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary
llvm-svn: 101397
2010-04-15 20:51:13 +00:00
b29cda9b3c
Fix a bunch of namespace polution.
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llvm-svn: 101376
2010-04-15 17:08:50 +00:00
9fd00c7d25
back out r101364, as it trips the linux nightlybot on some clang C++ tests
...
llvm-svn: 101368
2010-04-15 12:46:56 +00:00
aafd209632
rotate CallInst operands, i.e. move callee to the back
...
of the operand array
the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary
llvm-svn: 101364
2010-04-15 10:49:53 +00:00
3245afdf05
enhance the load/store narrowing optimization to handle a
...
tokenfactor in between the load/store. This allows us to
optimize test7 into:
_test7: ## @test7
## BB#0: ## %entry
movl (%rdx), %eax
## kill: SIL<def> ESI<kill>
movb %sil, 5(%rdi)
ret
instead of:
_test7: ## @test7
## BB#0: ## %entry
movl 4(%esp), %ecx
movl $-65281, %eax ## imm = 0xFFFFFFFFFFFF00FF
andl 4(%ecx), %eax
movzbl 8(%esp), %edx
shll $8, %edx
addl %eax, %edx
movl 12(%esp), %eax
movl (%eax), %eax
movl %edx, 4(%ecx)
ret
llvm-svn: 101355
2010-04-15 06:10:49 +00:00
6ebd8674eb
teach codegen to turn trunc(zextload) into load when possible.
...
This doesn't occur much at all, it only seems to formed in the case
when the trunc optimization kicks in due to phase ordering. In that
case it is saves a few bytes on x86-32.
llvm-svn: 101350
2010-04-15 05:40:59 +00:00
f9b2e3c68a
add a simple dag combine to replace trivial shl+lshr with
...
and. This happens with the store->load narrowing stuff.
llvm-svn: 101348
2010-04-15 05:28:43 +00:00
4041ab6e00
Implement rdar://7860110 (also in target/readme.txt) narrowing
...
a load/or/and/store sequence into a narrower store when it is
safe. Daniel tells me that clang will start producing this sort
of thing with bitfields, and this does trigger a few dozen times
on 176.gcc produced by llvm-gcc even now.
This compiles code like CodeGen/X86/2009-05-28-DAGCombineCrash.ll
into:
movl %eax, 36(%rdi)
instead of:
movl $4294967295, %eax ## imm = 0xFFFFFFFF
andq 32(%rdi), %rax
shlq $32, %rcx
addq %rax, %rcx
movq %rcx, 32(%rdi)
and each of the testcases into a single store. Each of them used
to compile into craziness like this:
_test4:
movl $65535, %eax ## imm = 0xFFFF
andl (%rdi), %eax
shll $16, %esi
addl %eax, %esi
movl %esi, (%rdi)
ret
llvm-svn: 101343
2010-04-15 04:48:01 +00:00
913c998703
Add more const qualifiers for LLVM IR pointers in CodeGen.
...
llvm-svn: 101342
2010-04-15 04:33:49 +00:00
bcaf681cde
Add const qualifiers to CodeGen's use of LLVM IR constructs.
...
llvm-svn: 101334
2010-04-15 01:51:59 +00:00
87b4f7c1aa
More 80 violations.
...
llvm-svn: 101330
2010-04-15 01:25:27 +00:00
8442ef6f89
80 col violations.
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llvm-svn: 101325
2010-04-15 01:01:55 +00:00
c87b74d913
Delete unneeeded arguments.
...
llvm-svn: 101276
2010-04-14 20:17:22 +00:00
a3918ecdf5
Delete unused arguments.
...
llvm-svn: 101275
2010-04-14 20:05:00 +00:00
7deb447781
Factor out EH landing pad code into a separate function, and constify
...
a bunch of stuff to support it.
llvm-svn: 101273
2010-04-14 19:53:31 +00:00
c2c08d19b8
Reset the debug location even if the instruction was a terminator.
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llvm-svn: 101272
2010-04-14 19:30:02 +00:00
cacd4f2401
Refine #includes.
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llvm-svn: 101269
2010-04-14 18:49:17 +00:00
8ebcbe949a
Pull utility routines with no SelectionDAG dependence out of
...
SelectionDAGBuilder. FunctionLoweringInfo isn't an ideal place for
them to live, but it's better than SelectionDAGBuilder for now.
llvm-svn: 101267
2010-04-14 18:31:02 +00:00
f5cca35750
Fix typos in comments.
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llvm-svn: 101266
2010-04-14 18:24:06 +00:00
fea9ba18ff
Delete an obsolete comment.
...
llvm-svn: 101264
2010-04-14 17:40:25 +00:00
3215eae4a3
Delete an unused function.
...
llvm-svn: 101263
2010-04-14 17:22:02 +00:00
094fc7b09e
Clear the FunctionLoweringInfo object before doing other things that
...
don't need it.
llvm-svn: 101262
2010-04-14 17:13:16 +00:00
ad0b3ea3cc
Move this assert out of SelectionDAGISel into FunctionLoweringInfo, and
...
drop the redundant #ifndef NDEBUG.
llvm-svn: 101261
2010-04-14 17:11:23 +00:00
0f405c8d73
Add a comment.
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llvm-svn: 101260
2010-04-14 17:09:37 +00:00
2ca8fb229c
Move the code for initialing the entry block livein set out of
...
SelectionDAGISel.
llvm-svn: 101258
2010-04-14 17:05:00 +00:00
4bfb437ec9
Reorgnaize this code to be more tidy and readable.
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llvm-svn: 101256
2010-04-14 17:02:07 +00:00
1939b5f130
Trim #includes.
...
llvm-svn: 101255
2010-04-14 16:54:39 +00:00
2b79ee8bc8
Move the code for emitting livein copies out of SelectionDAGISel.
...
llvm-svn: 101254
2010-04-14 16:51:49 +00:00
69e8e322d9
Sink landing-pad marking code out of
...
SelectionDAGISel::runOnMachineFunction into FunctionLowering.
llvm-svn: 101252
2010-04-14 16:32:56 +00:00
f57117d166
It's not necessary to recompute EB here.
...
llvm-svn: 101251
2010-04-14 16:30:40 +00:00
5f40d34958
Generalize this code to handle Instructions in addition to ConstantExprs.
...
llvm-svn: 101210
2010-04-14 02:33:23 +00:00
9162fb07be
Reorder the methods of this class to be a little more organized.
...
llvm-svn: 101206
2010-04-14 02:09:45 +00:00
8a2dae57e2
Add a few comments.
...
llvm-svn: 101148
2010-04-13 17:07:06 +00:00
ecd40a34e2
Remove unnecessary parens.
...
llvm-svn: 101010
2010-04-12 02:24:01 +00:00
4ce1fb1448
Add variants of ult, ule, etc. which take a uint64_t RHS, for convenience.
...
llvm-svn: 100824
2010-04-08 23:03:40 +00:00
d87bd77586
Fix -Wsign-compare warning (issued by clang++).
...
llvm-svn: 100799
2010-04-08 18:49:30 +00:00
a6769269f3
Use twines to simplify calls to report_fatal_error. For code size and readability.
...
llvm-svn: 100756
2010-04-08 10:44:28 +00:00
ebe47c872f
Avoid using f64 to lower memcpy from constant string. It's cheaper to use i32 store of immediates.
...
llvm-svn: 100751
2010-04-08 07:37:57 +00:00
3c65a8324d
convert a report_fatal_error that I was able to trigger into a nice error
...
so the user at least knows what inline asm is a problem. For example:
error: inline asm not supported yet: don't know how to handle tied indirect register inputs
pr8788-1.c:14:10: note: generated from here
asm ("\n" : "+r" (stack->regs)
^
Instead of:
fatal error: error in backend: Don't know how to handle tied indirect register inputs yet!
llvm-svn: 100731
2010-04-08 00:09:16 +00:00
94ef52824b
minor tidying.
...
llvm-svn: 100725
2010-04-07 23:50:38 +00:00
cd92718a0f
use assertions instead of unreachable for logic errors.
...
llvm-svn: 100724
2010-04-07 23:47:51 +00:00
2104b8d36e
rename llvm::llvm_report_error -> llvm::report_fatal_error
...
llvm-svn: 100709
2010-04-07 22:58:41 +00:00
Jakob Stoklund Olesen