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66 Commits

Author SHA1 Message Date
Owen Anderson 9a4d42855d Revert r121721, which broke buildbots. 
llvm-svn: 121726
 2010-12-13 22:51:08 +00:00
Owen Anderson 4efa445f3c Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR, 
which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.

llvm-svn: 121721
 2010-12-13 22:29:52 +00:00
Bob Wilson 9b3546d877 Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns. 
Jakob Olesen suggested that we can avoid the need for separate pseudo
instructions here by using COPY_TO_REGCLASS in the patterns.  The pattern
gets pretty ugly but it seems to work well.  Partial fix for Radar 8711675.

llvm-svn: 121718
 2010-12-13 21:58:05 +00:00
Bob Wilson 157fec42c9 Use pseudo instructions for 2-register Neon instructions for scalar FP. 
Partial fix for Radar 8711675.

llvm-svn: 121716
 2010-12-13 21:05:52 +00:00
Matt Beaumont-Gay eb369f84ec Remove unused variables 
llvm-svn: 121343
 2010-12-09 01:04:43 +00:00
Bill Wendling f75412dec7 Remove extraneous semicolon. 
llvm-svn: 121338
 2010-12-09 00:51:54 +00:00
Jason W Kim e296ee830a Style nit and whitespace cleanup 
llvm-svn: 121317
 2010-12-08 23:35:25 +00:00
Jason W Kim ba8b6d9a1c Removed dead comment. 
llvm-svn: 121313
 2010-12-08 23:19:44 +00:00
Jason W Kim c79c5f6e8c ARM/MC/ELF TPsoft is now a proper pseudo inst. 
Added test to check bl __aeabi_read_tp gets emitted properly for ELF/ASM
as well as ELF/OBJ (including fixup)

Also added support for ELF::R_ARM_TLS_IE32

llvm-svn: 121312
 2010-12-08 23:14:44 +00:00
Owen Anderson 99ea8a3510 Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it. 
llvm-svn: 121082
 2010-12-07 00:45:21 +00:00
Owen Anderson c1ee8e35d2 Revert r121021, which broke the buildbots. 
llvm-svn: 121026
 2010-12-06 18:57:40 +00:00
Jim Grosbach 67f13b19b5 Trailing whitespace. 
llvm-svn: 121024
 2010-12-06 18:47:44 +00:00
Owen Anderson bb4a76fc95 Improve handling of Thumb2 PC-relative loads by converting LDRpci (and friends) to Pseudos. 
llvm-svn: 121021
 2010-12-06 18:35:51 +00:00
Jim Grosbach cdae9242fa When expanding the MOVCCi32imm, make sure to use the ARM movt/movw opcodes, 
not thumb2.

llvm-svn: 120711
 2010-12-02 16:42:25 +00:00
Bob Wilson 431ac4ef50 Add support for NEON VLD3-dup instructions. 
The encoding for alignment in VLD4-dup instructions is still a work in progress.

llvm-svn: 120356
 2010-11-30 00:00:35 +00:00
Bob Wilson 77ab165afe Add support for NEON VLD3-dup instructions. 
llvm-svn: 120312
 2010-11-29 19:35:29 +00:00
Bob Wilson 2d790df105 Add support for NEON VLD2-dup instructions. 
llvm-svn: 120236
 2010-11-28 06:51:26 +00:00
Bob Wilson c92eea0175 Add NEON VLD1-dup instructions (load 1 element to all lanes). 
llvm-svn: 120194
 2010-11-27 06:35:16 +00:00
Benjamin Kramer 2e49eaa92f Avoid release build warnings. 
llvm-svn: 119804
 2010-11-19 16:36:02 +00:00
Anton Korobeynikov 0eecf5d201 Move hasFP() and few related hooks to TargetFrameInfo. 
llvm-svn: 119740
 2010-11-18 21:19:35 +00:00
Bill Wendling a68e3a5397 Encode the multi-load/store instructions with their respective modes ('ia', 
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>

llvm-svn: 119310
 2010-11-16 01:16:36 +00:00
Evan Cheng 2bcb8daa44 Add conditional move of large immediate. 
llvm-svn: 118968
 2010-11-13 02:25:14 +00:00
Evan Cheng f478cf9685 Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget. 
llvm-svn: 118938
 2010-11-12 23:03:38 +00:00
Bob Wilson d80b29d6f7 Add NEON VST1-lane instructions. Partial fix for Radar 8599955. 
llvm-svn: 118069
 2010-11-02 21:18:25 +00:00
Bob Wilson dc44990c7d Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. 
llvm-svn: 117964
 2010-11-01 22:04:05 +00:00
Jim Grosbach 4a0c2d73c3 Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in 
the ARMExpandPseudos pass rather than during the asm lowering.

llvm-svn: 117714
 2010-10-29 21:35:25 +00:00
Chandler Carruth 88c54b82c1 Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names 
until other LLVM projects using these are cleaned up.

llvm-svn: 117200
 2010-10-23 08:10:43 +00:00
Duncan Sands b014abf3ef The return value of this call is not used, so no point 
in assigning it to a variable (gcc-4.6 warning).

llvm-svn: 117024
 2010-10-21 16:06:28 +00:00
Jim Grosbach 723159ef77 Fix backwards conditional. 
llvm-svn: 116897
 2010-10-20 01:10:01 +00:00
Jim Grosbach cb6fc2b2de Add dynamic realignment when rematerializing the base register. 
llvm-svn: 116886
 2010-10-20 00:02:50 +00:00
Jim Grosbach bbdc5d2ef9 Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any 
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268

llvm-svn: 116879
 2010-10-19 23:27:08 +00:00
Bob Wilson f1b3681ed0 Use simple RegState::Define flag instead of getDefRegState(true). 
llvm-svn: 116601
 2010-10-15 18:25:59 +00:00
Jim Grosbach d15723c22a When expanding the MOVsr[la]_flag pseudos, the CPSR implicit def becomes 
an explicit def. Make sure to capture that properly. rdar://8556556

llvm-svn: 116591
 2010-10-15 17:35:17 +00:00
Jim Grosbach 8b6a9c1574 Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos 
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.

llvm-svn: 116534
 2010-10-14 22:57:13 +00:00
Jim Grosbach 2e3e2a006b Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be 
pseudo instructions.

llvm-svn: 115840
 2010-10-06 21:16:16 +00:00
Bob Wilson 450c6cfaff When expanding ARM pseudo registers, copy the existing predicate operands 
instead of using default predicates on the expanded instructions.

llvm-svn: 114066
 2010-09-16 04:25:37 +00:00
Bob Wilson 62c454847d Add missing break. 
llvm-svn: 114048
 2010-09-16 00:31:32 +00:00
Bob Wilson 6b853c3ce3 Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded after 
register allocation to VLDMD and VSTMD respectively.  This avoids using the
dregpair operand modifier.

llvm-svn: 114047
 2010-09-16 00:31:02 +00:00
Bob Wilson 62e9a052b9 Avoid warnings. 
llvm-svn: 113857
 2010-09-14 21:12:05 +00:00
Bob Wilson c597fd3b4a Convert some VTBL and VTBX instructions to use pseudo instructions prior to 
register allocation.  Remove the NEONPreAllocPass, which is no longer needed.
Yeah!!

llvm-svn: 113818
 2010-09-13 23:55:10 +00:00
Bob Wilson d5c57a5ed4 Switch all the NEON vld-lane and vst-lane instructions over to the new 
pseudo-instruction approach.  Change ARMExpandPseudoInsts to use a table
to record all the NEON load/store information.

llvm-svn: 113812
 2010-09-13 23:01:35 +00:00
Bob Wilson 84971c850a For double-spaced VLD3/VLD4 instructions, copy the explicit super-register use 
operand from the pseudo instruction to the new instruction as an implicit use.
This will preserve any other flags (e.g., kill) on the operand.

llvm-svn: 113456
 2010-09-09 00:38:32 +00:00
Bob Wilson 4ccd5ce6ea Simplify copying over operands from pseudo NEON load/store instructions. 
For VLD3/VLD4 with double-spaced registers, add the implicit use of the
super register for both the instruction loading the even registers and the
instruction loading the odd registers.

llvm-svn: 113452
 2010-09-09 00:15:32 +00:00
Bob Wilson 359f8ba337 Clean up a comment. 
llvm-svn: 113442
 2010-09-08 23:39:54 +00:00
Bob Wilson 35fafca587 Finish converting the rest of the NEON VLD instructions to use pseudo- 
instructions prior to regalloc.  Since it's getting a little close to
the 2.8 branch deadline, I'll have to leave the rest of the instructions
handled by the NEONPreAllocPass for now, but I didn't want to leave half
of the VLD instructions converted and the other half not.

llvm-svn: 112983
 2010-09-03 18:16:02 +00:00
Bob Wilson 5a1df805e5 Fill in a missing comment. 
llvm-svn: 112826
 2010-09-02 16:17:29 +00:00
Bob Wilson 75a6408f88 Convert VLD1 and VLD2 instructions to use pseudo-instructions until 
after regalloc.

llvm-svn: 112825
 2010-09-02 16:00:54 +00:00
Anton Korobeynikov 48043d0173 Expand MOVi32imm in ARM mode after regalloc. This provides 
scheduling opportunities (extra instruction can go in between
MOVT / MOVW pair removing the stall).

llvm-svn: 112546
 2010-08-30 22:50:36 +00:00
Bob Wilson e2f8bdac14 When expanding NEON VST pseudo instructions, if the original super-register 
operand is killed, add it to the expanded instruction as an implicit kill
operand instead of marking the individual subregs with kill flags.  This
should work better in general and also handles the case for VST3 where one
of the subregs was not referenced in the expanded instruction and so was
not marked killed.

llvm-svn: 112494
 2010-08-30 18:10:48 +00:00
Bob Wilson 950882be07 Use pseudo instructions for VST1 and VST2. 
llvm-svn: 112357
 2010-08-28 05:12:57 +00:00