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124 Commits

Author SHA1 Message Date
Daniel Dunbar 0c9d9fdd81 MC: Move target specific fixup info descriptors to TargetAsmBackend instead of 
the MCCodeEmitter, which seems like a better organization.
 - Also, cleaned up some magic constants while in the area.

llvm-svn: 121953
 2010-12-16 03:20:06 +00:00
Matt Beaumont-Gay e9afc740a8 Delete an extra "Imm5 = ", caught by GCC's -Wsequence-point but not by Clang 
(see PR4579).

llvm-svn: 121939
 2010-12-16 01:34:26 +00:00
Bill Wendling 9613a09e5c Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff for 
it. I.e., it was always an immediate value.

llvm-svn: 121932
 2010-12-16 00:50:33 +00:00
Bill Wendling 7d3bde98f1 If we're changing the frame register to a physical register other than SP, we 
need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively.

llvm-svn: 121915
 2010-12-15 23:32:27 +00:00
Owen Anderson 622ad5170b Implement cleanups suggested by Daniel. 
llvm-svn: 121875
 2010-12-15 18:48:27 +00:00
Bill Wendling 03e7576dee Add fixups for Thumb LDR/STR instructions. 
llvm-svn: 121858
 2010-12-15 08:51:02 +00:00
Jim Grosbach eda5177ca6 thumb adr fixup needs alignment just like the t2 version. 
llvm-svn: 121812
 2010-12-14 23:47:35 +00:00
Jim Grosbach 509dc2a700 Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755 
llvm-svn: 121798
 2010-12-14 22:28:03 +00:00
Daniel Dunbar a9b9300bb8 MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup. 
llvm-svn: 121772
 2010-12-14 17:37:16 +00:00
Bill Wendling 092a7bdf9f The tLDR et al instructions were emitting either a reg/reg or reg/imm 
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.

llvm-svn: 121747
 2010-12-14 03:36:38 +00:00
Owen Anderson 6d375e5637 Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire 
process cleaner.

llvm-svn: 121735
 2010-12-14 00:36:49 +00:00
Owen Anderson 9a4d42855d Revert r121721, which broke buildbots. 
llvm-svn: 121726
 2010-12-13 22:51:08 +00:00
Owen Anderson 4efa445f3c Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR, 
which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.

llvm-svn: 121721
 2010-12-13 22:29:52 +00:00
Owen Anderson 578074b2f3 In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or 
as a "long" direct branch.  While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches.  Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.

llvm-svn: 121710
 2010-12-13 19:31:11 +00:00
Jim Grosbach aecdd871da Add FIXME 
llvm-svn: 121598
 2010-12-10 23:41:10 +00:00
Owen Anderson 235c276442 Attempt to get Thumb2 branch fixups working properly. 
llvm-svn: 121593
 2010-12-10 23:02:28 +00:00
Owen Anderson 7cdd232895 Fix merge error in my last fix to Thumb2 vldr fixups. 
llvm-svn: 121588
 2010-12-10 22:53:48 +00:00
Owen Anderson 4743d75640 Fixups for Thumb2 vldr's need to have the effective PC aligned as well. 
llvm-svn: 121587
 2010-12-10 22:46:47 +00:00
Bill Wendling 006ab13b59 The MCFixupKindInfo table needs to be in the order that the enums were 
declared. Add a note specifying this and spruce up the list a bit.

llvm-svn: 121586
 2010-12-10 22:37:19 +00:00
Owen Anderson b0fa127f60 Fix encoding of Thumb1 LDRB and STRB. 
llvm-svn: 121581
 2010-12-10 22:11:13 +00:00
Jim Grosbach c4a0c29edb Trailing whitespace. 
llvm-svn: 121580
 2010-12-10 21:57:34 +00:00
Jim Grosbach e69f724935 Fix encoding of 'U' bit for Thumb2 STRD/LDRD instructions. rdar://8755726 
llvm-svn: 121524
 2010-12-10 21:05:07 +00:00
Jim Grosbach e119da1146 Thumb unconditional branch binary encoding. rdar://8754994 
llvm-svn: 121496
 2010-12-10 18:21:33 +00:00
Jim Grosbach 78485ad65e Thumb conditional branch binary encodings. rdar://8745367 
llvm-svn: 121493
 2010-12-10 17:13:40 +00:00
Bill Wendling 0c4838bab7 Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of the 
t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>

llvm-svn: 121417
 2010-12-09 21:49:07 +00:00
Owen Anderson cb4d8f2e74 Use the new IsAligned fixup flag to improve fixup encodings for Thumb2 branches. This is still not perfect, 
but it gets many more of them correct than it did previously.

llvm-svn: 121414
 2010-12-09 21:34:47 +00:00
Owen Anderson 3ef19d9d48 Fix an issue in some Thumb fixups, where the effective PC address needs to be 4-byte aligned when calculating 
the offset.  Add a new fixup flag to represent this, and use it for the one fixups that I have a testcase for needing
this.  It's quite likely that the other Thumb fixups will need this too, and to have their fixup encoding logic
adjusted accordingly.

llvm-svn: 121408
 2010-12-09 20:27:52 +00:00
Jim Grosbach 68b27eb9d1 Rename CB/CBZ specific fixup accordingly. 
llvm-svn: 121404
 2010-12-09 19:50:12 +00:00
Jim Grosbach 62b68112da Rename the encoder method for t_cbtarget to match. 
llvm-svn: 121399
 2010-12-09 19:04:53 +00:00
Owen Anderson 3e6ee1db3e Fix Thumb2 fixups for ldr. 
llvm-svn: 121350
 2010-12-09 01:51:07 +00:00
Bill Wendling 3392bfc8f3 The BLX instruction is encoded differently than the BL, because why not? In 
particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.

Attempt to get the encoding at slightly more correct with this.

llvm-svn: 121336
 2010-12-09 00:39:08 +00:00
Owen Anderson 302d5fd0d8 Fix Thumb2 BCC encoding and fixups. 
llvm-svn: 121329
 2010-12-09 00:27:41 +00:00
Bill Wendling a7d6aa902a Support the "target" encodings for the CB[N]Z instructions. 
llvm-svn: 121308
 2010-12-08 23:01:43 +00:00
Bill Wendling 8a6449c46e Add support for loading from a constant pool. 
llvm-svn: 121226
 2010-12-08 01:57:09 +00:00
Owen Anderson 0f7142d808 VLDR fixups need special handling under Thumb. While the encoding is the same, 
the order of the bytes in the data stream is flipped around.

llvm-svn: 121215
 2010-12-08 00:18:36 +00:00
Matt Beaumont-Gay 56de7c2773 Fix a warning about a variable which is only used in an assertion. 
llvm-svn: 121206
 2010-12-07 23:26:21 +00:00
Jim Grosbach 49bcd6ff85 Binary encoding for ARM tLDRspi and tSTRspi. 
llvm-svn: 121186
 2010-12-07 21:50:47 +00:00
Owen Anderson 99ea8a3510 Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it. 
llvm-svn: 121082
 2010-12-07 00:45:21 +00:00
Jim Grosbach 9e1994698d Add fixup for Thumb1 BL/BLX instructions. 
llvm-svn: 121072
 2010-12-06 23:57:07 +00:00
Jim Grosbach 567ebd0cb5 Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order 
halfword being emitted to the stream first. rdar://8728174

llvm-svn: 120848
 2010-12-03 22:31:40 +00:00
Bill Wendling f0b36a3cfd The tLDR instruction wasn't encoded properly: 
<MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>>

Notice that the "reg" here is 0, which is an invalid register. Put a check in
the code for this to prevent crashing.

llvm-svn: 120766
 2010-12-03 00:53:22 +00:00
Jim Grosbach ce2bd8d05f Add support for binary encoding of ARM 'adr' instructions referencing constant 
pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.

llvm-svn: 120635
 2010-12-02 00:28:45 +00:00
Bill Wendling 87240d4b9c Add a post encoder method to the VFP instructions to convert them to the Thumb2 
encoding if we're in that mode.

llvm-svn: 120608
 2010-12-01 21:54:50 +00:00
Jim Grosbach 30eb6c7e71 Use the correct fixup type for ARM VLDR* 
llvm-svn: 120604
 2010-12-01 21:09:40 +00:00
Jim Grosbach dc35e067c1 Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR 
instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.

llvm-svn: 120594
 2010-12-01 19:47:31 +00:00
Owen Anderson 943fb60b1f Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax. 
llvm-svn: 120589
 2010-12-01 19:18:46 +00:00
Jim Grosbach 7f5b475852 10 bits, not 12. 
llvm-svn: 120584
 2010-12-01 18:51:32 +00:00
Jim Grosbach ee48d2daaa Fix typo. 
llvm-svn: 120499
 2010-11-30 23:51:41 +00:00
Jason W Kim c440e79126 Thanks to JimG for catching this! 
llvm-svn: 120494
 2010-11-30 23:27:18 +00:00
Bill Wendling a9e3df7aa0 * Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as 
t_addrmode_s4, but with a different scaling factor.

* Encode the Thumb1 load and store instructions. This involved a bit of
  refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
  were removed.

llvm-svn: 120482
 2010-11-30 22:57:21 +00:00