Commit Graph

111 Commits

Author SHA1 Message Date
Jim Grosbach ffaea0f017 Use a StringSwitch<> instead of a manually constructed string matcher.
llvm-svn: 122530
2010-12-24 00:03:39 +00:00
Jim Grosbach bcfa4a945a Recognize a few more documented register name aliases for ARM in the asm lexer.
llvm-svn: 122523
2010-12-23 23:19:54 +00:00
Jim Grosbach 8c48503baa Trailing whitespace.
llvm-svn: 122456
2010-12-22 23:26:02 +00:00
Bill Wendling 092a7bdf9f The tLDR et al instructions were emitting either a reg/reg or reg/imm
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.

llvm-svn: 121747
2010-12-14 03:36:38 +00:00
Kevin Enderby c92136ffb6 Fix the leak from r121401 of the Operands erased in the list but not deleted.
llvm-svn: 121450
2010-12-10 01:41:56 +00:00
Kevin Enderby 3164a346e6 Add support for parsing ARM arithmetic instructions that update or don't update
the condition codes.  Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix.  The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present.  Four simple test cases added for now, lots more to come.

llvm-svn: 121401
2010-12-09 19:19:43 +00:00
Benjamin Kramer cfa9a893df Add parens to pacify gcc.
llvm-svn: 121142
2010-12-07 15:50:35 +00:00
Jim Grosbach 968c927201 Encode the register operand of ARM CondCode operands correctly. ARM::CPSR if
the instruction is predicated, reg0 otherwise.

llvm-svn: 121020
2010-12-06 18:30:57 +00:00
Jim Grosbach 0bfb4d5043 The ARM AsmMatcher needs to know that the CCOut operand is a register value,
not an immediate. It stores either ARM::CPSR or reg0.

llvm-svn: 121018
2010-12-06 18:21:12 +00:00
Bill Wendling a9e3df7aa0 * Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as
t_addrmode_s4, but with a different scaling factor.

* Encode the Thumb1 load and store instructions. This involved a bit of
  refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
  were removed.

llvm-svn: 120482
2010-11-30 22:57:21 +00:00
Bill Wendling 811c936ed5 Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost
certainly be made more generic. But it does allow us to parse something like:

          ldr     r3, [r2, r4]

correctly in Thumb mode.

llvm-svn: 120408
2010-11-30 07:44:32 +00:00
Jim Grosbach cb803b043b Add a few missing initializers.
llvm-svn: 120350
2010-11-29 23:41:10 +00:00
Jim Grosbach 32ff5586fc Nuke trailing whitespace.
llvm-svn: 120344
2010-11-29 23:18:01 +00:00
Bill Wendling 219dabdf68 The "trap" instruction is one of this which doesn't have a condition code. Hack
the code to not add a "condition code" if it's trap.

llvm-svn: 119937
2010-11-21 10:56:05 +00:00
Bill Wendling 20b5ea9858 Use array_pod_sort because the list is contiguous.
llvm-svn: 119769
2010-11-19 00:38:19 +00:00
Bill Wendling 2063b84297 Add support for parsing the writeback ("!") token.
llvm-svn: 119761
2010-11-18 23:43:05 +00:00
Bill Wendling 0ab0f67925 Don't allocate the SmallVector of Registers. It gets messy figuring out who
should delete what when the object gets copied around. It's also making valgrind
upset.

llvm-svn: 119747
2010-11-18 21:50:54 +00:00
Bill Wendling 9898ac97fd Proper encoding for VLDM and VSTM instructions. The register lists for these
instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.

llvm-svn: 119460
2010-11-17 04:32:08 +00:00
Bill Wendling 91607f878c Emit a '!' if this is a "writeback" register or memory address.
llvm-svn: 118662
2010-11-10 01:07:54 +00:00
Matt Beaumont-Gay 55c4cc76ce Rename a parameter to avoid confusion with a local variable
llvm-svn: 118656
2010-11-10 00:08:58 +00:00
Bill Wendling e9a9c6da04 Emit the warning about the register list not being in ascending order only once.
llvm-svn: 118653
2010-11-09 23:45:59 +00:00
Bill Wendling bed9465a96 s/std::vector/SmallVector/
llvm-svn: 118648
2010-11-09 23:28:44 +00:00
Bill Wendling da3c0fbc64 Delete the allocated vector.
llvm-svn: 118644
2010-11-09 22:51:42 +00:00
Bill Wendling 2cae3277a5 Two types of instructions have register lists:
* LDM, et al, uses a bit mask to indicate the register list.
* VLDM, et al, uses a base register plus number.

The LDM instructions may be non-contiguous, but the VLDM ones must be
contiguous. Those are semantic checks that should be done later in the
compiler. Also postpone the creation of the bit mask until it's needed.

llvm-svn: 118640
2010-11-09 22:44:22 +00:00
Bill Wendling 8d2aa03ce1 The "addRegListOperands()" function returns the start register and the total
number of registers in the list.

llvm-svn: 118456
2010-11-08 23:49:57 +00:00
Bill Wendling 2f9d17c44f Revert.
llvm-svn: 118389
2010-11-08 00:32:40 +00:00
Bill Wendling 68bac75190 In this context, a reglist is a reg.
llvm-svn: 118375
2010-11-07 13:08:28 +00:00
Bill Wendling e18980aeaa Add support for parsing register lists. We can't use a bitfield to keep track of
the registers, because the register numbers may be much greater than the number
of bits available in the machine's register.

I extracted the register list verification code out of the actual parsing of the
registers. This made checking for errors much easier. It also limits the number
of warnings that would be emitted for cascading infractions.

llvm-svn: 118363
2010-11-06 22:36:58 +00:00
Bill Wendling b884a8ee44 Return the base register of a register list for the "getReg()" method. This is
to satisfy the ClassifyOperand method of the Asm matcher without having to add a
RegList type to every back-end.

llvm-svn: 118360
2010-11-06 22:19:43 +00:00
Bill Wendling ee7f1f9914 General cleanup:
- Make ARMOperand a class so that some things are internal to the class.
- Reformatting.

llvm-svn: 118357
2010-11-06 21:42:12 +00:00
Bill Wendling 7cef447c14 Add a RegList (register list) object to ARMOperand. It will be used soon to hold
(surprise!) a list of registers. Register lists are consecutive, so we only need
to record the start register plus the number of registers.

llvm-svn: 118351
2010-11-06 19:56:04 +00:00
Bill Wendling 8300d834c9 Fix grammar.
llvm-svn: 118341
2010-11-06 10:51:53 +00:00
Bill Wendling 4f4bce0682 Fix grammar.
llvm-svn: 118340
2010-11-06 10:48:18 +00:00
Bill Wendling 518e43c453 MatchRegisterName() returns 0 if it can't match the register.
llvm-svn: 118339
2010-11-06 10:45:34 +00:00
Bill Wendling 6d2eb737af Use TryParseRegister() instead of MatchRegisterName(). The former returns -1
while the latter doesn't.

llvm-svn: 118338
2010-11-06 10:40:24 +00:00
Jim Grosbach 2db0ea03ba Hook up the '.code {16|32}' directive to the streamer.
llvm-svn: 118310
2010-11-05 22:40:53 +00:00
Jim Grosbach c6db8ce5da Hook up the '.thumb_func' directive to the streamer.
llvm-svn: 118307
2010-11-05 22:33:53 +00:00
Jim Grosbach 0fe92e3fea Fix past-o.
llvm-svn: 118304
2010-11-05 22:11:33 +00:00
Bill Wendling e84eb99cbb The MC code couldn't handle ARM LDR instructions with negative offsets:
vldr.64 d1, [r0, #-32]

The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.

llvm-svn: 118144
2010-11-03 01:49:29 +00:00
Jim Grosbach 7d45c101e5 Add FIXME.
llvm-svn: 117936
2010-11-01 18:11:14 +00:00
Jim Grosbach 0190a649e8 Mark ARM subtarget features that are available for the assembler.
llvm-svn: 117929
2010-11-01 16:59:54 +00:00
Jim Grosbach 99710a871c trailing whitespace
llvm-svn: 117927
2010-11-01 16:44:21 +00:00
Jim Grosbach a71c9e2ebf Tidy up.
llvm-svn: 117782
2010-10-30 12:59:16 +00:00
Chris Lattner 549a31cd34 simplify this code.
llvm-svn: 117771
2010-10-30 04:35:59 +00:00
Chris Lattner 44e5981c1b split MaybeParseRegister into its two logical uses, eliminating malloc+free traffic.
llvm-svn: 117769
2010-10-30 04:09:10 +00:00
Bill Wendling 193961bb1a Some instructions end with an "ls" prefix, but it doesn't indicate that they are
conditional. Check for those instructions explicitly.

llvm-svn: 117747
2010-10-29 23:50:21 +00:00
Jim Grosbach 31f23b48ba add FIXME
llvm-svn: 117718
2010-10-29 21:56:51 +00:00
Jim Grosbach 16bd9f1ab5 Handle ARM addrmode5 instructions with an offset.
llvm-svn: 117672
2010-10-29 17:41:25 +00:00
Jim Grosbach 305ec65927 Revert 117660. Apparently it's not as trivial as that...
llvm-svn: 117663
2010-10-29 16:50:53 +00:00
Jim Grosbach 8682b69b81 ARM addrmode5 instructions have neither writeback nor post-indexed modes.
llvm-svn: 117660
2010-10-29 16:38:59 +00:00