0eecf5d201
Move hasFP() and few related hooks to TargetFrameInfo.
...
llvm-svn: 119740
2010-11-18 21:19:35 +00:00
7d47133ff7
Split up ARM LowerShift function.
...
This function was being called from two different places for completely
unrelated reasons. During type legalization, it was called to expand 64-bit
shift operations. During operation legalization, it was called to handle
Neon vector shifts. The vector shift code was not written to check for
illegal types, since it was assumed to be only called after type legalization.
Fixed this by splitting off the 64-bit shift expansion into a separate
function. I don't have a particular testcase for this; I just noticed it
by inspection.
llvm-svn: 119738
2010-11-18 21:16:28 +00:00
3fec5ff14b
More Thumb2 encodings.
...
llvm-svn: 119737
2010-11-18 21:15:19 +00:00
3625098459
Fill out the set of Thumb2 multiplication operator encodings.
...
llvm-svn: 119733
2010-11-18 20:32:18 +00:00
b9bd594610
Missed the _RET versions of LDMIA.
...
llvm-svn: 119726
2010-11-18 19:44:29 +00:00
b006fc9c07
Rewrite stack callee saved spills and restores to use push/pop instructions.
...
Remove movePastCSLoadStoreOps and associated code for simple pointer
increments. Update routines that depended upon other opcodes for save/restore.
Adjust all testcases accordingly.
llvm-svn: 119725
2010-11-18 19:40:05 +00:00
51fdc47a11
ARMPseudoInst instructions should default to being considered a single 4-byte
...
instruction. Any that may be expanded otherwise by MC lowering should
override this value. rdar://8683274
llvm-svn: 119713
2010-11-18 18:01:40 +00:00
2d4e42fba6
Silence compiler warnings.
...
llvm-svn: 119610
2010-11-18 01:43:23 +00:00
9c335bf977
Remove trailing whitespace.
...
llvm-svn: 119608
2010-11-18 01:39:50 +00:00
a74c7ccd59
ARM PseudoInst instructions don't need or use an assembler string. Get rid of
...
the operand to the pattern.
llvm-svn: 119607
2010-11-18 01:38:26 +00:00
a2f30cc121
Code clean up.
...
llvm-svn: 119604
2010-11-18 01:28:51 +00:00
19be1fbca1
Add FIXME.
...
llvm-svn: 119603
2010-11-18 01:20:48 +00:00
cfb66204b7
Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not
...
just pretend to be.
llvm-svn: 119602
2010-11-18 01:15:56 +00:00
d127e7174b
Try again at providing Thumb2 encodings for basic multiplication operators.
...
llvm-svn: 119601
2010-11-18 01:08:42 +00:00
8e7f8df4a2
Refactor a few ARM load instructions to better parameterize things and re-use
...
common encoding information.
llvm-svn: 119598
2010-11-18 00:46:58 +00:00
28883834e1
Revert r119593 while I figure out my testing disagrees with the buildbot.
...
llvm-svn: 119597
2010-11-18 00:42:51 +00:00
64aaddcd64
Provide correct Thumb2 encodings for basic multiplication operators.
...
llvm-svn: 119593
2010-11-18 00:19:10 +00:00
56f471726c
Clean up LEApcrel instuction(s) a bit. It's not really a Pseudo, so don't mark
...
it as such. Add some encoding information.
llvm-svn: 119588
2010-11-17 23:33:14 +00:00
55425e7f78
Second attempt at correct encodings for Thumb2 bitfield instructions.
...
llvm-svn: 119575
2010-11-17 22:16:31 +00:00
4ded8f264a
Fix comment typo.
...
llvm-svn: 119573
2010-11-17 21:57:51 +00:00
881b45ccdf
Change ARMGlobalMerge to keep BSS globals in separate pools.
...
This completes the fixes for Radar 8673120.
llvm-svn: 119566
2010-11-17 21:25:39 +00:00
4c8ab19c22
Fix ARMGlobalMerge pass to check if globals are entirely within range.
...
It is generally not sufficient to check if the starting offset is in range
of the maximum offset that can be efficiently used for the target.
llvm-svn: 119565
2010-11-17 21:25:36 +00:00
59182fb4b5
Change the symbol for merged globals from "merged" to "_MergedGlobals".
...
This makes it more clear that the symbol is an internal, compiler-generated
name and gives a little more description about its contents.
llvm-svn: 119564
2010-11-17 21:25:33 +00:00
f796d4b469
Fix the ARMGlobalMerge pass to look at variable sizes instead of pointer sizes.
...
It was mistakenly looking at the pointer type when checking for the size of
global variables. This is a partial fix for Radar 8673120.
llvm-svn: 119563
2010-11-17 21:25:27 +00:00
08c562bba6
Make the ARM BR_JTadd instruction an explicit pseudo and lower it properly
...
in the MC lowering process.
llvm-svn: 119559
2010-11-17 21:05:55 +00:00
39c81c0a55
Avoid isel movcc of large immediates when the large immediate is available in a register. These immediates aren't free.
...
llvm-svn: 119558
2010-11-17 20:56:30 +00:00
6c37ceb182
Revert r119551, which broke buildbots.
...
llvm-svn: 119555
2010-11-17 20:48:51 +00:00
7464116bde
Provide Thumb2 encodings for bitfield instructions.
...
llvm-svn: 119551
2010-11-17 20:35:29 +00:00
7f8ab6ee8b
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
...
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.
Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.
Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.
2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.
rdar://8663787, rdar://8241368
llvm-svn: 119548
2010-11-17 20:13:28 +00:00
7a2cd8b540
make isVirtualSection a virtual method on MCSection. Chris' suggestion.
...
llvm-svn: 119547
2010-11-17 20:03:54 +00:00
bced7ae046
More miscellaneous Thumb2 encodings.
...
llvm-svn: 119546
2010-11-17 19:57:38 +00:00
11cc1761dd
Add missing opcodes now that this function's used in more than one place.
...
llvm-svn: 119539
2010-11-17 19:16:20 +00:00
8839775df6
More ARM encoding bits. LDRH now encodes properly.
...
llvm-svn: 119529
2010-11-17 18:11:11 +00:00
7c91bb855f
Revert r119109 for now. It's breaking 176.gcc.
...
llvm-svn: 119492
2010-11-17 09:31:04 +00:00
655364797e
Simplify code that toggle optional operand to ARM::CPSR.
...
llvm-svn: 119484
2010-11-17 08:06:50 +00:00
9fdd10dbce
tidy up
...
llvm-svn: 119462
2010-11-17 05:41:32 +00:00
b100f91754
The machine instruction no longer encodes the submode as a separate operand. We
...
should get the submode from the load/store multiple instruction's opcode.
llvm-svn: 119461
2010-11-17 05:31:09 +00:00
9898ac97fd
Proper encoding for VLDM and VSTM instructions. The register lists for these
...
instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.
llvm-svn: 119460
2010-11-17 04:32:08 +00:00
345b48fcbd
Add binary emission stuff for VLDM/VSTM. This reuses the
...
"getRegisterListOpValue" logic. If the registers are double or single precision,
the value returned is suitable for VLDM/VSTM.
llvm-svn: 119435
2010-11-17 00:45:23 +00:00
a8974af320
Use the correct variable names so that the encodings will be correct.
...
llvm-svn: 119403
2010-11-16 23:44:49 +00:00
e600aba989
ARM conditional mov encoding fix.
...
llvm-svn: 119354
2010-11-16 18:13:42 +00:00
5aa33ca29d
L_bit doesn't work here.
...
llvm-svn: 119325
2010-11-16 02:20:22 +00:00
3bd60eff26
- Remove dead patterns.
...
- Add encodings to the *LDMIA_RET instrs. Probably not needed...
llvm-svn: 119323
2010-11-16 02:08:45 +00:00
02089a39a0
vldm and vstm are mnemonics for vldmia and vstmia resp.
...
llvm-svn: 119321
2010-11-16 02:00:24 +00:00
a68e3a5397
Encode the multi-load/store instructions with their respective modes ('ia',
...
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
llvm-svn: 119310
2010-11-16 01:16:36 +00:00
05a8daee21
Add Thumb2 encodings for mov and friends.
...
llvm-svn: 119295
2010-11-16 00:29:56 +00:00
ea96321781
Attempt to provide encodings for some miscellaneous Thumb2 encodings.
...
llvm-svn: 119187
2010-11-15 21:30:39 +00:00
2ce016c7f8
Code clean up. The peephole pass should be the one updating the instruction
...
iterator, not TII->OptimizeCompareInstr.
llvm-svn: 119186
2010-11-15 21:20:45 +00:00
7d97a99f4c
Provide Thumb2 encodings for sxtb and friends.
...
llvm-svn: 119185
2010-11-15 21:12:05 +00:00
964943780b
Recommit this change and remove the failing part of the test - it didn't
...
pass in the first place and was masked by earlier failures not warning
and aborting the block.
llvm-svn: 119184
2010-11-15 21:11:06 +00:00
38b469effd
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.
...
llvm-svn: 119180
2010-11-15 20:47:07 +00:00
2a3c22efba
Add Thumb2 encodings for comparison and shift operators.
...
llvm-svn: 119176
2010-11-15 19:58:36 +00:00
0e7d728327
Add correct Thumb2 encodings for mvn and friends.
...
llvm-svn: 119170
2010-11-15 18:45:17 +00:00
5cf10ea1d1
Add FIXMEs.
...
llvm-svn: 119167
2010-11-15 18:36:48 +00:00
40a7f57d0d
Nuke redundant encoding bit set.
...
llvm-svn: 119164
2010-11-15 18:17:24 +00:00
63274cbc5d
add fields to the .td files unconditionally, simplifying tblgen a bit.
...
Switch the ARM backend to use 'let' instead of 'set' with this change.
llvm-svn: 119120
2010-11-15 05:19:05 +00:00
dd96e97317
Make sure ARM multi load / store pass copies memoperands when forming ldrd / strd. pr8113.
...
llvm-svn: 119109
2010-11-15 03:30:30 +00:00
3ddef1ac36
silence a ton of warnings from clang.
...
llvm-svn: 119102
2010-11-15 01:45:44 +00:00
51d2e9ca29
Attempt to unbreak cmake-based builds
...
llvm-svn: 119098
2010-11-15 00:48:12 +00:00
f7183edb59
First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place
...
llvm-svn: 119097
2010-11-15 00:06:54 +00:00
2aa8becf33
trim #includes.
...
llvm-svn: 119075
2010-11-14 21:16:04 +00:00
de16ca8ecc
rename LowerToMCInst -> LowerARMMachineInstrToMCInst.
...
llvm-svn: 119071
2010-11-14 21:00:02 +00:00
c5afd12557
even more simplifications. ARM MCInstLowering is now just
...
a single function instead of a class. It doesn't need the
complexity that X86 does.
llvm-svn: 119070
2010-11-14 20:58:38 +00:00
18442f5543
more shrinkification
...
llvm-svn: 119068
2010-11-14 20:41:53 +00:00
3040e8c69b
more simplifications.
...
llvm-svn: 119067
2010-11-14 20:40:08 +00:00
b28e691657
simplify and tidy up
...
llvm-svn: 119066
2010-11-14 20:31:06 +00:00
a76eab433a
stub out a powerpc MCInstPrinter implementation.
...
llvm-svn: 119059
2010-11-14 19:40:38 +00:00
e0f6b41618
Second attempt at providing correct encodings for Thumb2 binary operators.
...
llvm-svn: 119029
2010-11-14 05:37:38 +00:00
9430eb489c
Comment out the defms until they're activated.
...
llvm-svn: 119000
2010-11-13 11:20:05 +00:00
705ec77ab5
Add uses of the *_ldst_multi multiclasses. These aren't used yet.
...
llvm-svn: 118999
2010-11-13 10:57:02 +00:00
c4c642832d
Convert the modes to lower case.
...
llvm-svn: 118998
2010-11-13 10:43:34 +00:00
f2fa04acfc
Minor cleanups:
...
- Get the opcode once.
- Add a ParserMatchClass to reglist.
llvm-svn: 118997
2010-11-13 10:40:19 +00:00
e69afc6bb7
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
...
future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.
llvm-svn: 118995
2010-11-13 09:09:38 +00:00
fe0c28f4db
MC: Simplify Mach-O and ELF object writer implementations.
...
- What was I thinking?????
llvm-svn: 118992
2010-11-13 07:33:40 +00:00
79ff5238e9
Conditional moves are slightly more expensive than moves.
...
llvm-svn: 118985
2010-11-13 05:14:20 +00:00
2bcb8daa44
Add conditional move of large immediate.
...
llvm-svn: 118968
2010-11-13 02:25:14 +00:00
1aa5863a3e
Swap multiclass operand order for consistency with other patterns.
...
llvm-svn: 118965
2010-11-13 01:28:30 +00:00
69fd90e661
Continue ARM indexed load refactoring. Multiclass for LDR{B} pre/post indexed
...
instructions.
llvm-svn: 118963
2010-11-13 01:07:20 +00:00
2f790749e8
More ARM load/store indexed refactoring. Also fix an incorrect IndexMode
...
flag for the LDRT/STRT family instructions as a side effect.
llvm-svn: 118955
2010-11-13 00:35:48 +00:00
8ce967e393
Fix an obvious typo which inverted an immediate.
...
llvm-svn: 118951
2010-11-13 00:27:47 +00:00
1293c6a23a
Temporarily revert this.
...
llvm-svn: 118946
2010-11-12 23:50:48 +00:00
9c40af415f
For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled with movi + orr.
...
llvm-svn: 118945
2010-11-12 23:46:13 +00:00
7cd724ae7d
Revert r118939 while I work out why it broke some buildbots.
...
llvm-svn: 118942
2010-11-12 23:36:03 +00:00
0003a296ad
Attemt to provide correct encodings for Thumb2 binary operators.
...
llvm-svn: 118939
2010-11-12 23:18:11 +00:00
f478cf9685
Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.
...
llvm-svn: 118938
2010-11-12 23:03:38 +00:00
49a66f7d71
Make this happen for ARM like x86. Don't entirely bail out when
...
an address is in a different block, get it into a register and go
from there.
llvm-svn: 118936
2010-11-12 22:52:32 +00:00
0fc8084a64
Add conditional mvn instructions.
...
llvm-svn: 118935
2010-11-12 22:42:47 +00:00
e09122b46b
Zap a copy/paste-o bit of dead code.
...
llvm-svn: 118926
2010-11-12 21:29:10 +00:00
31a7234a47
Refactor to parameterize some ARM load/store encoding patterns. Preparatory
...
to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.
llvm-svn: 118925
2010-11-12 21:28:15 +00:00
8fdd172502
First stab at providing correct Thumb2 encodings, start with adc.
...
llvm-svn: 118924
2010-11-12 21:12:40 +00:00
2d59ee34f1
Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next.
...
llvm-svn: 118922
2010-11-12 20:32:20 +00:00
6bb1ae9d45
Kill more unused stuff.
...
llvm-svn: 118921
2010-11-12 19:27:45 +00:00
984ff7d17e
Remove unused class.
...
llvm-svn: 118919
2010-11-12 19:24:53 +00:00
3fd741191d
Fill in the default predication bits for ARM unconditional branch.
...
llvm-svn: 118907
2010-11-12 18:13:26 +00:00
0deb9c20c0
Encoding for ARM LDRSB instructions.
...
llvm-svn: 118905
2010-11-12 17:52:59 +00:00
22d0492f34
Fix up a few more spots of addrmode2 (or not) changes that were
...
missed. Update some comments accordingly.
Fixes rdar://8652289
llvm-svn: 118888
2010-11-12 09:48:30 +00:00
20b6fd7d5d
Start of support for binary emit of 16-it Thumb instructions.
...
llvm-svn: 118859
2010-11-11 23:41:09 +00:00
ce2250fba4
Fill out support for Thumb2 encodings of NEON instructions.
...
llvm-svn: 118854
2010-11-11 23:12:55 +00:00
99a8cb4875
Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].
...
llvm-svn: 118843
2010-11-11 21:36:43 +00:00
7ae11c6962
Revert the accidental commit I made reverting the previous commit.
...
llvm-svn: 118835
2010-11-11 20:50:14 +00:00
c33f28bf90
ARM fixup encoding for direct call instructions (BL).
...
llvm-svn: 118829
2010-11-11 20:05:40 +00:00
b90f7004cf
Revert this temporarily.
...
llvm-svn: 118827
2010-11-11 19:47:02 +00:00
e6283f950d
Change the prologue and epilogue to use push/pop for the low ARM registers.
...
llvm-svn: 118823
2010-11-11 19:26:03 +00:00
7ffe3b35ac
Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
...
More tests to come.
llvm-svn: 118819
2010-11-11 19:07:48 +00:00
9d6d77a9f4
Encoding of destination fixup for ARM branch and conditional branch
...
instructions.
llvm-svn: 118801
2010-11-11 18:04:49 +00:00
68685e644f
Encoding for ARM LDRSH_POST.
...
llvm-svn: 118794
2010-11-11 16:55:29 +00:00
f18b951e18
Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.
...
llvm-svn: 118767
2010-11-11 01:55:59 +00:00
e967c0a795
Fix encoding of Ra register for ARM smla* instructions.
...
llvm-svn: 118761
2010-11-11 01:27:41 +00:00
607efcbc3e
ARM STRH encoding information.
...
llvm-svn: 118757
2010-11-11 01:09:40 +00:00
c4dd2349c7
Move LDM predicate operand encoding into base clase. Add STM missing STM
...
encoding bits.
llvm-svn: 118738
2010-11-10 23:44:32 +00:00
cc4a491557
ARM LDM encoding for the mode (ia, ib, da, db) operand.
...
llvm-svn: 118736
2010-11-10 23:38:36 +00:00
58ef598cd1
Fix ARM encoding of non-return LDM instructions.
...
llvm-svn: 118732
2010-11-10 23:18:49 +00:00
e39a9fcc0e
Fix ARM encoding of LDM+Return instruction.
...
llvm-svn: 118730
2010-11-10 23:12:48 +00:00
ca52411955
Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build vector with 2 elts
...
llvm-svn: 118720
2010-11-10 21:35:41 +00:00
ca21cd749e
Simplify and clean up MC symbol lookup for ARM constant pool values. This fixes
...
double quoting of ObjC symbol names in constant pool entries.
rdar://8652107
llvm-svn: 118688
2010-11-10 17:59:10 +00:00
f23b2d9d8d
Update ARMConstantPoolValue to not use a modifier string. Use an explicit
...
VariantKind marker to indicate the additional information necessary. Update
MC to handle the new Kinds. rdar://8647623
llvm-svn: 118671
2010-11-10 03:26:07 +00:00
91607f878c
Emit a '!' if this is a "writeback" register or memory address.
...
llvm-svn: 118662
2010-11-10 01:07:54 +00:00
55c4cc76ce
Rename a parameter to avoid confusion with a local variable
...
llvm-svn: 118656
2010-11-10 00:08:58 +00:00
e9a9c6da04
Emit the warning about the register list not being in ascending order only once.
...
llvm-svn: 118653
2010-11-09 23:45:59 +00:00
bed9465a96
s/std::vector/SmallVector/
...
llvm-svn: 118648
2010-11-09 23:28:44 +00:00
da3c0fbc64
Delete the allocated vector.
...
llvm-svn: 118644
2010-11-09 22:51:42 +00:00
d0046ca62d
Define the subtarget feature for the architecture version,
...
as derived from the target triple. This is important for enabling
features that are implied based on the architecture version.
llvm-svn: 118643
2010-11-09 22:50:47 +00:00
193722ebc8
Do not use MEMBARRIER_MCR for any Thumb code.
...
It is only supported for ARM code. Normally Thumb2 code would use DMB instead,
but depending on how the compiler is invoked (e.g., -mattr=-db) that might be
disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that
situation. Radar 8644195
llvm-svn: 118642
2010-11-09 22:50:44 +00:00
2cae3277a5
Two types of instructions have register lists:
...
* LDM, et al, uses a bit mask to indicate the register list.
* VLDM, et al, uses a base register plus number.
The LDM instructions may be non-contiguous, but the VLDM ones must be
contiguous. Those are semantic checks that should be done later in the
compiler. Also postpone the creation of the bit mask until it's needed.
llvm-svn: 118640
2010-11-09 22:44:22 +00:00
a942ad4222
Change the ARMConstantPoolValue modifier string to an enumeration. This will
...
help in MC'izing the references that use them.
llvm-svn: 118633
2010-11-09 21:36:17 +00:00
2fd4c37d8b
Handle ARM constant pool values that need an explicit reference to the '.'
...
pseudo-label. (TLS stuff).
llvm-svn: 118609
2010-11-09 19:40:22 +00:00
68147ee320
Trailing whitespace.
...
llvm-svn: 118606
2010-11-09 19:22:26 +00:00
38f8e76e51
Further MCize ARM constant pool values. This allows basic PIC references for
...
object file emission.
llvm-svn: 118601
2010-11-09 18:45:04 +00:00
7e51095c23
Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding.
...
llvm-svn: 118600
2010-11-09 18:43:54 +00:00
59002dc973
For ARM load/store instructions, encode [reg+reg] with no shifter immediate as
...
a left shift by zero.
llvm-svn: 118587
2010-11-09 17:38:15 +00:00
9b973490c9
ARM .word data fixups don't need an adjustment.
...
llvm-svn: 118586
2010-11-09 17:36:59 +00:00
dbfb5edbdb
Add encoder method for ARM load/store shifted register offset operands.
...
llvm-svn: 118513
2010-11-09 17:20:53 +00:00
9098714f8b
Add support for a few simple fixups to the ARM Darwin asm backend. This allows
...
constant pool references and global variable refernces to resolve properly
for object file generation. For example,
int x;
void foo(unsigned a, unsigned *p) {
p[a] = x;
}
can now be successfully compiled directly to an (ARM mode) object file.
llvm-svn: 118469
2010-11-09 01:37:15 +00:00
1b83ed5f7c
Revert r118457 and r118458. These won't hold for GPRs.
...
llvm-svn: 118462
2010-11-09 00:30:18 +00:00
31b850be15
Get the register and count from the register list operands.
...
llvm-svn: 118458
2010-11-08 23:51:20 +00:00
aeead4d1e1
reglist has two operands.
...
llvm-svn: 118457
2010-11-08 23:50:20 +00:00
8d2aa03ce1
The "addRegListOperands()" function returns the start register and the total
...
number of registers in the list.
llvm-svn: 118456
2010-11-08 23:49:57 +00:00
c7baee31ad
Add support for ARM's specialized vector-compare-against-zero instructions.
...
llvm-svn: 118453
2010-11-08 23:21:22 +00:00
a91d02bc61
Add "write back" bit encoding.
...
llvm-svn: 118446
2010-11-08 21:28:03 +00:00
0ef474730f
Revert 118422 in search of bot verdancy.
...
llvm-svn: 118429
2010-11-08 19:17:22 +00:00
f3e224f830
Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.
...
llvm-svn: 118422
2010-11-08 17:58:07 +00:00
fc6b6bd5a6
Complete listing of ARM/MC/ELF relocation enums
...
llvm-svn: 118413
2010-11-08 16:47:27 +00:00
424601a9b3
Make RegList an ASM operand so that TableGen will generate code for it. This is
...
an initial implementation and may change once reglists are fully fleshed out.
llvm-svn: 118390
2010-11-08 00:39:58 +00:00
2f9d17c44f
Revert.
...
llvm-svn: 118389
2010-11-08 00:32:40 +00:00
68bac75190
In this context, a reglist is a reg.
...
llvm-svn: 118375
2010-11-07 13:08:28 +00:00
e18980aeaa
Add support for parsing register lists. We can't use a bitfield to keep track of
...
the registers, because the register numbers may be much greater than the number
of bits available in the machine's register.
I extracted the register list verification code out of the actual parsing of the
registers. This made checking for errors much easier. It also limits the number
of warnings that would be emitted for cascading infractions.
llvm-svn: 118363
2010-11-06 22:36:58 +00:00
b884a8ee44
Return the base register of a register list for the "getReg()" method. This is
...
to satisfy the ClassifyOperand method of the Asm matcher without having to add a
RegList type to every back-end.
llvm-svn: 118360
2010-11-06 22:19:43 +00:00
ee7f1f9914
General cleanup:
...
- Make ARMOperand a class so that some things are internal to the class.
- Reformatting.
llvm-svn: 118357
2010-11-06 21:42:12 +00:00
7cef447c14
Add a RegList (register list) object to ARMOperand. It will be used soon to hold
...
(surprise!) a list of registers. Register lists are consecutive, so we only need
to record the start register plus the number of registers.
llvm-svn: 118351
2010-11-06 19:56:04 +00:00
8300d834c9
Fix grammar.
...
llvm-svn: 118341
2010-11-06 10:51:53 +00:00
4f4bce0682
Fix grammar.
...
llvm-svn: 118340
2010-11-06 10:48:18 +00:00
518e43c453
MatchRegisterName() returns 0 if it can't match the register.
...
llvm-svn: 118339
2010-11-06 10:45:34 +00:00
6d2eb737af
Use TryParseRegister() instead of MatchRegisterName(). The former returns -1
...
while the latter doesn't.
llvm-svn: 118338
2010-11-06 10:40:24 +00:00
89965d7091
Make sure we have movw on the target before using it.
...
Fixes 8559.
llvm-svn: 118333
2010-11-06 07:53:11 +00:00
2db0ea03ba
Hook up the '.code {16|32}' directive to the streamer.
...
llvm-svn: 118310
2010-11-05 22:40:53 +00:00
c6db8ce5da
Hook up the '.thumb_func' directive to the streamer.
...
llvm-svn: 118307
2010-11-05 22:33:53 +00:00
0fe92e3fea
Fix past-o.
...
llvm-svn: 118304
2010-11-05 22:11:33 +00:00
5a2c68d308
MC'ize the '.code 16' and '.thumb_func' ARM directives.
...
llvm-svn: 118301
2010-11-05 22:08:08 +00:00
a4076924d1
Disallow the certain NEON modified-immediate forms when generating vorr or vbic.
...
llvm-svn: 118300
2010-11-05 21:57:54 +00:00
ff9e507d8e
MC'ize simple ARMConstantValue entry emission (with a FIXME).
...
llvm-svn: 118295
2010-11-05 20:34:24 +00:00
30c4892ea5
Add codegen and encoding support for the immediate form of vbic.
...
llvm-svn: 118291
2010-11-05 19:27:46 +00:00
2bab7570f5
Enable MachO writing for ARM/Darwin. Lots of stuff still doesn't work
...
(relocations, e.g.), but this will allow simple things to flow through.
llvm-svn: 118289
2010-11-05 18:50:35 +00:00
46c2acbcb4
Allow targets to specify the MachO CPUType/CPUSubtype information.
...
llvm-svn: 118288
2010-11-05 18:48:58 +00:00
1df82e67d1
Add FIXME.
...
llvm-svn: 118280
2010-11-05 17:37:13 +00:00
71049f78ed
In the calling convention logic, ValVT is always a legal type,
...
and as such can be represented by an MVT - the more complicated
EVT is not needed. Use MVT for ValVT everywhere.
llvm-svn: 118245
2010-11-04 10:49:57 +00:00
21acf9fb38
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.
...
llvm-svn: 118237
2010-11-04 05:19:35 +00:00
0fb841fd19
Add ARM fixup info for load/store label references. Probably will need a bit of
...
tweaking when we start using it for object file emission or JIT, but it's a
start.
llvm-svn: 118221
2010-11-04 01:12:30 +00:00
c002463ac4
Add encoding for VSTR.
...
llvm-svn: 118220
2010-11-04 00:59:42 +00:00
2eed7a1310
Teach ARM Target to use the tblgen support for generating an MC'ized
...
CodeEmitter.
llvm-svn: 118209
2010-11-03 23:52:49 +00:00
bc9b31c493
Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization.
...
This is both the conceptually correct place for it, as well as allowing it to be more aggressive.
llvm-svn: 118204
2010-11-03 23:15:26 +00:00
0747307049
Add support for code generation of the one register with immediate form of vorr.
...
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.
llvm-svn: 118201
2010-11-03 22:44:51 +00:00
49b0c45ecf
trailing whitespace
...
llvm-svn: 118199
2010-11-03 22:03:20 +00:00
e4dd7378d0
Optimize generated code for integer materialization a bit.
...
llvm-svn: 118192
2010-11-03 20:21:17 +00:00
bb81f80af6
Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead,
...
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.
llvm-svn: 118183
2010-11-03 18:16:27 +00:00
7d0ac84abd
Add codegen patterns for VST1-lane instructions. Radar 8599955.
...
llvm-svn: 118176
2010-11-03 16:24:53 +00:00
ceb49296ef
Check for extractelement with a variable operand for the element number.
...
For NEON we had been assuming this was always an immediate constant.
llvm-svn: 118175
2010-11-03 16:24:50 +00:00
1462777017
Simplify uses of MVT and EVT. An MVT can be compared directly
...
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.
llvm-svn: 118169
2010-11-03 12:17:33 +00:00
f5dda01f33
Inside the calling convention logic LocVT is always a simple
...
value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
llvm-svn: 118167
2010-11-03 11:35:31 +00:00
8740ee3637
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
...
llvm-svn: 118160
2010-11-03 06:34:55 +00:00
6f36042557
Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
...
llvm-svn: 118152
2010-11-03 05:14:24 +00:00
6552a109bb
Put the PC encoding in the correct bit position.
...
llvm-svn: 118151
2010-11-03 04:57:44 +00:00
c63d846ad6
Invert these branches by default, it makes assembly comparisons a little
...
easier to read.
llvm-svn: 118148
2010-11-03 04:29:11 +00:00
e84eb99cbb
The MC code couldn't handle ARM LDR instructions with negative offsets:
...
vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
llvm-svn: 118144
2010-11-03 01:49:29 +00:00
fd96701456
Remove unused function.
...
llvm-svn: 118141
2010-11-03 01:35:15 +00:00
e7f7de95e0
Remove the no longer used 'Modifier' optional operand to the ARM
...
printOperand() asm printer helper functions. rdar://8425198
llvm-svn: 118140
2010-11-03 01:11:15 +00:00
50ba3c09bf
Remove unused function.
...
llvm-svn: 118139
2010-11-03 01:07:48 +00:00
c6af2b4066
Break ARM addrmode4 (load/store multiple base address) into its constituent
...
parts. Represent the operation mode as an optional operand instead.
rdar://8614429
llvm-svn: 118137
2010-11-03 01:01:43 +00:00
debf9c502a
Two sets of changes. Sorry they are intermingled.
...
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
"optimize for latency". Call instructions don't have the right latency and
this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
not # of micro-ops since multi-latency instructions is completely executed
even when the predicate is false. Also, some instruction will be "slower"
when they are predicated due to the register def becoming implicit input.
rdar://8598427
llvm-svn: 118135
2010-11-03 00:45:17 +00:00
634ab6c2b7
Modify scheduling itineraries to correct instruction latencies (not operand
...
latencies) of loads.
llvm-svn: 118134
2010-11-03 00:40:22 +00:00
1e43892e4b
Make sure we're only storing a single bit here.
...
llvm-svn: 118126
2010-11-02 23:59:09 +00:00
0ebd1fd594
Revert r118097 to fix buildbots.
...
llvm-svn: 118121
2010-11-02 23:47:29 +00:00
cc5dce89d4
Completely reject instructions that have an operand in their
...
ins/outs list that isn't specified by their asmstring. Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right. Mark a bunch of ARM instructions that use this as
isCodeGenOnly. Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).
llvm-svn: 118119
2010-11-02 23:40:41 +00:00
f9eebb58b9
Obsessive formatting changes. No functionality impact.
...
llvm-svn: 118103
2010-11-02 22:53:11 +00:00
23436b6530
Omit unused parameter name.
...
llvm-svn: 118099
2010-11-02 22:46:04 +00:00
91da9abbee
Simplify the EncodeInstruction method now that a lot of the special case stuff
...
is handled with the MC encoder.
llvm-svn: 118098
2010-11-02 22:44:12 +00:00
7c30390277
Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning.
...
llvm-svn: 118097
2010-11-02 22:41:42 +00:00
603bd8f54c
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
...
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.
llvm-svn: 118094
2010-11-02 22:31:46 +00:00
a4b63e19d2
Rename encoder methods to match naming convention.
...
llvm-svn: 118093
2010-11-02 22:28:01 +00:00
dec87e10fd
Provide correct encodings for the remaining vst variants that we currently generate.
...
llvm-svn: 118087
2010-11-02 22:18:18 +00:00
adf88d4c5f
Tentative encodings for the "single element from one lane" variant of vst1.
...
llvm-svn: 118084
2010-11-02 21:54:45 +00:00
b95618cfe0
Add correct encodings for basic variants for vst3 and vst4.
...
llvm-svn: 118082
2010-11-02 21:47:03 +00:00
d80b29d6f7
Add NEON VST1-lane instructions. Partial fix for Radar 8599955.
...
llvm-svn: 118069
2010-11-02 21:18:25 +00:00
fa08e1e277
Add correct encodings for the basic variants for vst2.
...
llvm-svn: 118068
2010-11-02 21:16:58 +00:00
87c62e54e6
Add correct encodings for the basic form of vst1.
...
llvm-svn: 118067
2010-11-02 21:06:06 +00:00
9f20daf3b4
Factor out a common encoding class for loads and stores with a lane parameter.
...
llvm-svn: 118055
2010-11-02 20:47:39 +00:00
a83859539f
Add correct encodings for the rest of the vld instructions that we generate.
...
llvm-svn: 118053
2010-11-02 20:40:59 +00:00
93a4d44ee6
Sort bit assignments. Cosmetic change only.
...
llvm-svn: 118029
2010-11-02 17:59:04 +00:00
0b7fda23cc
Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke
...
assumptions about stack layout. Specifically, LR must be saved next to FP.
llvm-svn: 118026
2010-11-02 17:35:25 +00:00
526ffd57d2
Add correct NEON encodings for vld2, vld3, and vld4 basic variants.
...
llvm-svn: 117997
2010-11-02 01:24:55 +00:00
b2abb508ae
Remove an assert - it's possible to be hit, and we just want to avoid
...
handling those cases for now.
llvm-svn: 117996
2010-11-02 01:24:49 +00:00
ac746e1b38
Whitespeace
...
llvm-svn: 117995
2010-11-02 01:22:45 +00:00
e8fccc82e4
No really, no thumb1 for arm fast isel. Also add an informative comment as
...
to what someone would need to do to support thumb1.
llvm-svn: 117994
2010-11-02 01:21:28 +00:00
b3ca2060c0
Attempt to provide correct encodings for a number of other vld1 variants, which we can't test
...
since we can neither generate nor parse them at the moment.
llvm-svn: 117988
2010-11-02 00:24:52 +00:00
f1610f7910
Add aesthetic break.
...
llvm-svn: 117986
2010-11-02 00:14:00 +00:00
ad40234eff
Add correct NEON encodings for the "multiple single elements" form of vld.
...
llvm-svn: 117984
2010-11-02 00:05:05 +00:00
2ba03aa618
Explicitly check for non-consant reference in an LDRi12 instruction. Add FIXME
...
for handling the fixup necessary.
llvm-svn: 117978
2010-11-01 23:45:50 +00:00
a3efae35f5
Remove unused function.
...
llvm-svn: 117977
2010-11-01 23:40:56 +00:00
dd9fbaa9c0
Add support for alignment operands on VLD1-lane instructions.
...
This is another part of the fix for Radar 8599955.
llvm-svn: 117976
2010-11-01 23:40:51 +00:00
3f37ade36e
Missed reverting this bit.
...
llvm-svn: 117971
2010-11-01 23:17:54 +00:00
f7e176a3ec
Minor cleanup.
...
llvm-svn: 117969
2010-11-01 23:11:22 +00:00
dc44990c7d
Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.
...
llvm-svn: 117964
2010-11-01 22:04:05 +00:00
418bd53008
Move the machine operand MC encoding patterns to the parent classes.
...
llvm-svn: 117956
2010-11-01 21:17:06 +00:00
c6627eec13
When we look at instructions to convert to setting the 's' flag, we need to look
...
at more than those which define CPSR. You can have this situation:
(1) subs ...
(2) sub r6, r5, r4
(3) movge ...
(4) cmp r6, 0
(5) movge ...
We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:
(1) sub r1, r2, r3
(2) sub r4, r5, r6
(3) cmp r4, ...
(5) movge ...
(6) cmp r1, ...
(7) movge ...
We cannot convert (1) to "subs" because of the intervening use of CPSR.
llvm-svn: 117950
2010-11-01 20:41:43 +00:00
44be217af1
NEON does not support truncating vector stores. Radar 8598391.
...
llvm-svn: 117940
2010-11-01 18:31:39 +00:00
7d45c101e5
Add FIXME.
...
llvm-svn: 117936
2010-11-01 18:11:14 +00:00
fddf36d254
Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates
...
codegen using the patterns; the latter gates the assembler recognizing the
instruction.
llvm-svn: 117931
2010-11-01 17:08:58 +00:00
0190a649e8
Mark ARM subtarget features that are available for the assembler.
...
llvm-svn: 117929
2010-11-01 16:59:54 +00:00
99710a871c
trailing whitespace
...
llvm-svn: 117927
2010-11-01 16:44:21 +00:00
5b373341fc
The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the
...
patterns as such
llvm-svn: 117923
2010-11-01 15:59:52 +00:00
2623343625
Move instruction encoding bits into the parent class and remove the temporary
...
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.
llvm-svn: 117906
2010-11-01 06:00:39 +00:00
941c19b7ba
reject instructions that contain a \n in their asmstring. Mark
...
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.
llvm-svn: 117884
2010-11-01 00:46:16 +00:00
7ff334687d
fix the !eq operator in tblgen to return a bit instead of an int.
...
Use this to make the X86 and ARM targets set isCodeGenOnly=1
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.
llvm-svn: 117862
2010-10-31 19:22:57 +00:00
9492c17baf
two changes: make the asmmatcher generator ignore ARM pseudos properly,
...
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.
llvm-svn: 117861
2010-10-31 19:15:18 +00:00
33fc3e095b
reapply r117858 with apparent editor malfunction fixed (somehow I
...
got a dulicated line).
llvm-svn: 117860
2010-10-31 19:10:56 +00:00
e59eef3dd1
revert r117858 while I check out a failure I missed.
...
llvm-svn: 117859
2010-10-31 19:05:32 +00:00
9293008e90
the asm matcher can't handle operands with modifiers (like ${foo:bar}).
...
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the
instruction 'isCodeGenOnly'.
Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are
doing this.
llvm-svn: 117858
2010-10-31 18:48:12 +00:00
04b0a3e651
Make sure we have a legal type (and simple) before continuing.
...
llvm-svn: 117848
2010-10-30 21:25:26 +00:00
bbe2bbd7f7
Add FIXME.
...
llvm-svn: 117787
2010-10-30 14:54:23 +00:00
a71c9e2ebf
Tidy up.
...
llvm-svn: 117782
2010-10-30 12:59:16 +00:00
549a31cd34
simplify this code.
...
llvm-svn: 117771
2010-10-30 04:35:59 +00:00
44e5981c1b
split MaybeParseRegister into its two logical uses, eliminating malloc+free traffic.
...
llvm-svn: 117769
2010-10-30 04:09:10 +00:00
7b275105d6
Avoid re-evaluating MI.getNumOperands() every iteration of the loop.
...
llvm-svn: 117766
2010-10-30 01:40:16 +00:00
7ed597149b
Overhaul memory barriers in the ARM backend. Radar 8601999.
...
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain. It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions. Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions. Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.
llvm-svn: 117756
2010-10-30 00:54:37 +00:00
74ef9e184e
Encode the register list operands for ARM mode LDM/STM instructions.
...
llvm-svn: 117753
2010-10-30 00:37:59 +00:00
193961bb1a
Some instructions end with an "ls" prefix, but it doesn't indicate that they are
...
conditional. Check for those instructions explicitly.
llvm-svn: 117747
2010-10-29 23:50:21 +00:00
069f38d1bf
Remove hard tab characters.
...
llvm-svn: 117742
2010-10-29 23:23:15 +00:00
5f0d616ae5
80 column fix.
...
llvm-svn: 117741
2010-10-29 23:21:57 +00:00
96d828448f
trailing whitespace
...
llvm-svn: 117740
2010-10-29 23:21:03 +00:00
58018e62a8
s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand
...
encoder functions.
llvm-svn: 117738
2010-10-29 23:19:55 +00:00
99cce36cf5
Fix fpscr <-> GPR latency info.
...
llvm-svn: 117737
2010-10-29 23:16:55 +00:00
31f23b48ba
add FIXME
...
llvm-svn: 117718
2010-10-29 21:56:51 +00:00
4a0c2d73c3
Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in
...
the ARMExpandPseudos pass rather than during the asm lowering.
llvm-svn: 117714
2010-10-29 21:35:25 +00:00
5c308f8452
Handle comparison values we already have - this fixes the consumer-typeset
...
failure for llvm-gcc on arm fast isel.
llvm-svn: 117710
2010-10-29 21:08:19 +00:00
e477b1ad30
ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to
...
handle it in the asm lowering.
llvm-svn: 117707
2010-10-29 20:37:06 +00:00
cb8aec8ec9
Fix typo.
...
llvm-svn: 117703
2010-10-29 20:21:49 +00:00
3b7e05bb97
ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS.
...
llvm-svn: 117702
2010-10-29 20:21:36 +00:00
4e57b52394
ARM mode LDREX*/STREX* binary encodings.
...
llvm-svn: 117695
2010-10-29 19:58:57 +00:00
6ae3fba7c8
Encoding information for ARM conditional move instructions.
...
llvm-svn: 117687
2010-10-29 19:28:17 +00:00
6c1414f9c2
Avoiding overly aggressive latency scheduling. If the two nodes share an
...
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.
BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB
=>
BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB
This fixed the recent 256.bzip2 regression.
llvm-svn: 117675
2010-10-29 18:09:28 +00:00
0c4c5ca6e1
- Don't schedule nodes with only MVT::Flag and MVT::Other values for latency.
...
- Compute CopyToReg use operand latency correctly.
llvm-svn: 117674
2010-10-29 18:07:31 +00:00
16bd9f1ab5
Handle ARM addrmode5 instructions with an offset.
...
llvm-svn: 117672
2010-10-29 17:41:25 +00:00
e8360b7182
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
...
llvm-svn: 117667
2010-10-29 17:29:13 +00:00
305ec65927
Revert 117660. Apparently it's not as trivial as that...
...
llvm-svn: 117663
2010-10-29 16:50:53 +00:00
8682b69b81
ARM addrmode5 instructions have neither writeback nor post-indexed modes.
...
llvm-svn: 117660
2010-10-29 16:38:59 +00:00
624bcc7371
Trailing whitespace.
...
llvm-svn: 117651
2010-10-29 14:46:02 +00:00
08b8c534f7
ARMAsmParser: Plug a memory leak.
...
llvm-svn: 117648
2010-10-29 09:43:39 +00:00
91d7b90185
Add an unreachable to silence warning - the switch is actually
...
fully enumerated.
llvm-svn: 117647
2010-10-29 09:26:59 +00:00
5d6f6a061b
add simple support for addrmode5 operands, allowing
...
vldr.64 to work. I have no idea if this is fully right, but
it is in the right direction.
llvm-svn: 117626
2010-10-29 00:27:31 +00:00
d27b05e54a
give better error diagnostics, for example:
...
t.s:1:14: error: invalid operand for instruction
vldr.64 d17, [r0]
^
instead of:
t.s:1:1: error: unrecognized instruction
vldr.64 d17, [r0]
^
llvm-svn: 117611
2010-10-28 21:41:58 +00:00
f20f79808e
hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes
...
the opcode string in the inst dump, e.g.:
vmov r2, r3, d17 @ encoding: [0x31,0x2b,0x53,0xec]
@ <MCInst #989 VMOVRRD
@ <MCOperand Reg:68>
@ <MCOperand Reg:69>
@ <MCOperand Reg:19>
@ <MCOperand Imm:14>
@ <MCOperand Reg:0>>
The "VMOVRRD" is new.
llvm-svn: 117609
2010-10-28 21:37:33 +00:00
9487de6160
move a method out of line.
...
llvm-svn: 117605
2010-10-28 21:28:01 +00:00
9f9f4ebf0c
remove the rest of hte owningptr's, no functionality change.
...
llvm-svn: 117603
2010-10-28 20:52:15 +00:00
505607e4c6
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.
...
llvm-svn: 117571
2010-10-28 18:34:10 +00:00
b24ba7be49
rearrange ParseRegisterList.
...
llvm-svn: 117560
2010-10-28 17:23:41 +00:00
bd7c9fa36b
refactor some code to simplify it, eliminating some owningptr's.
...
llvm-svn: 117559
2010-10-28 17:20:03 +00:00
ff310737e5
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
...
llvm-svn: 117531
2010-10-28 06:47:08 +00:00
e2c211c1b9
Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
...
llvm-svn: 117520
2010-10-28 02:00:25 +00:00
ff1c862f8e
- Assign load / store with shifter op address modes the right itinerary classes.
...
- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
llvm-svn: 117519
2010-10-28 01:49:06 +00:00
2ef668840a
Add correct NEON encodings for vtbl and vtbx.
...
llvm-svn: 117513
2010-10-28 00:18:46 +00:00
14be930317
Add correct NEON encodings for vext, vtrn, vuzp, and vzip.
...
llvm-svn: 117512
2010-10-27 23:56:39 +00:00
6c55007edb
Fix compiler warnings about signed/unsigned comparisons.
...
llvm-svn: 117511
2010-10-27 23:49:00 +00:00
59bbc545e0
Shifter ops are not always free. Do not fold them (especially to form
...
complex load / store addressing mode) when they have higher cost and
when they have more than one use.
llvm-svn: 117509
2010-10-27 23:41:30 +00:00
338de3ee56
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
...
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
llvm-svn: 117505
2010-10-27 23:12:14 +00:00
fadb951e5b
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
...
for specifying fractional bits for fixed point conversions.
llvm-svn: 117501
2010-10-27 22:49:00 +00:00
055de2c789
Trailing whitespace
...
llvm-svn: 117496
2010-10-27 21:39:08 +00:00
ed9652f959
Provide correct encodings for the get_lane and set_lane variants of vmov.
...
llvm-svn: 117495
2010-10-27 21:28:09 +00:00
f4ea7084c5
JIT imm12 encoding for constant pool entry references.
...
llvm-svn: 117483
2010-10-27 20:39:40 +00:00
c7334a146e
SelectionDAG shuffle nodes do not allow operands with different numbers of
...
elements than the result vector type. So, when an instruction like:
%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is:
shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]
That's probably the right thing for x86 but for NEON, we'd much rather have:
shuffle [a,b,c,d], undef
Teach the DAG combiner how to do that transformation for ARM. Radar 8597007.
llvm-svn: 117482
2010-10-27 20:38:28 +00:00
333b0a9e74
ARM JIT fix for LDRi12 and company.
...
llvm-svn: 117478
2010-10-27 19:55:59 +00:00
40d24a4abf
Provide correct NEON encodings for vdup.
...
llvm-svn: 117475
2010-10-27 19:25:54 +00:00
ba1c6cd62f
The new LDR* instruction patterns should handle the necessary encoding of
...
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.
llvm-svn: 117461
2010-10-27 17:52:51 +00:00
8576a42cf3
Add correct NEON encodings for vsli and vsri.
...
llvm-svn: 117459
2010-10-27 17:40:08 +00:00
d7e8135e1e
Add correct NEON encodings for vsra and vrsra.
...
llvm-svn: 117458
2010-10-27 17:29:29 +00:00
8bf1483a3d
The immediate operands of an LDRi12 instruction doesn't need the addrmode2
...
encoding tricks. Handle the 'imm doesn't fit in the insn' case.
llvm-svn: 117454
2010-10-27 16:50:31 +00:00
9d2d1f0f00
LDRi12 machine instructions handle negative offset operands normally (simple
...
integer values), not with the addrmode2 encoding.
llvm-svn: 117429
2010-10-27 01:19:41 +00:00
2577b2e8b1
One more spot where the new arm mode LDR instruction representation
...
doesn't need the additional addrmode2 register operand. Missed it the first
time around.
llvm-svn: 117421
2010-10-27 00:38:16 +00:00
5a7c715470
Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
...
rdar://8477752.
llvm-svn: 117419
2010-10-27 00:19:44 +00:00
a92801b695
Since I parameterized this bit, I should probably actually use said parameter.
...
llvm-svn: 117418
2010-10-26 23:58:04 +00:00
825b2d1946
Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun.
...
llvm-svn: 117411
2010-10-26 22:50:46 +00:00
1e4d9a17c2
First part of refactoring ARM addrmode2 (load/store) instructions to be more
...
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
llvm-svn: 117409
2010-10-26 22:37:02 +00:00
2888e2c7f9
Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.
...
llvm-svn: 117402
2010-10-26 21:58:41 +00:00
e18579976f
Simplify classes for shift instructions, which are never commutable.
...
llvm-svn: 117398
2010-10-26 21:13:59 +00:00
3665fee8de
Provide correct NEON encodings for vshl, register and immediate forms.
...
llvm-svn: 117394
2010-10-26 20:56:57 +00:00
9302bfdd5a
Grammar.
...
llvm-svn: 117388
2010-10-26 19:34:41 +00:00
79b3bf4d81
Nuke extraneous comment. It's applicable elsewhere, but not in this func.
...
llvm-svn: 117387
2010-10-26 19:22:23 +00:00
691ce68d3c
Add correct NEON encoding for vpadal.
...
llvm-svn: 117380
2010-10-26 18:18:03 +00:00
284cb361d1
Add NEON encodings for vmov and vmvn of immediates.
...
llvm-svn: 117374
2010-10-26 17:40:54 +00:00
e96b8d7ab6
Use instruction itinerary to determine what instructions are 'cheap'.
...
llvm-svn: 117348
2010-10-26 02:08:50 +00:00
b45591979b
NEON vmov's are in Neon domain.
...
llvm-svn: 117347
2010-10-26 02:03:05 +00:00
59f7cdaf98
Tidy up redundant check.
...
llvm-svn: 117331
2010-10-26 00:02:19 +00:00
d9d0c348df
Produce the headers directly in the Finish method. This allows us to use
...
the existing streamer methods that are endian safe.
llvm-svn: 117323
2010-10-25 22:26:55 +00:00
1f6aad053d
Add correct encodings for NEON vabal.
...
llvm-svn: 117315
2010-10-25 21:29:04 +00:00
b9c91679aa
Add correct NEON encodings for vaba.
...
llvm-svn: 117309
2010-10-25 20:52:57 +00:00
dd001b89d7
Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment.
...
llvm-svn: 117294
2010-10-25 20:17:22 +00:00
dea09c7564
Provide correct NEON encodings for vbsl.
...
llvm-svn: 117293
2010-10-25 20:13:13 +00:00
e6fe1a03c7
imm12 operands aren't Thumb2 only, so rename the printer helper function.
...
llvm-svn: 117291
2010-10-25 20:00:01 +00:00
2477446ee5
Add correct instruction encodings for vbic, vorn, and vmvn.
...
llvm-svn: 117282
2010-10-25 18:43:52 +00:00
752913d6ba
Add a virtual destructor.
...
llvm-svn: 117280
2010-10-25 18:38:32 +00:00
dff239c5f9
Provide correct NEON encodings for vand, veor, and vorr.
...
llvm-svn: 117279
2010-10-25 18:28:30 +00:00
feb3ee0c93
Add NEON encoding tests for vcgt and vacgt.
...
llvm-svn: 117276
2010-10-25 18:03:59 +00:00
0ed1543d4e
Add support for emitting ARM file attributes.
...
llvm-svn: 117275
2010-10-25 17:50:35 +00:00
e5d0677173
Add tests for NEON encodings of vcge and vacge.
...
llvm-svn: 117274
2010-10-25 17:49:32 +00:00
c178b80f65
Add a warning about our inability to test the encoding of vceq with immediate zero.
...
llvm-svn: 117273
2010-10-25 17:33:02 +00:00
c9616f26bd
Move rejection of NEON parameters earlier in fast isel call processing,
...
note that we can actually handle some f64 arguments.
llvm-svn: 117209
2010-10-23 09:37:17 +00:00
82058c05f8
Move the remaining attribute macros to systematic names based on the attribute
...
name and prefixed with 'LLVM_'.
llvm-svn: 117203
2010-10-23 08:40:19 +00:00
88c54b82c1
Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names
...
until other LLVM projects using these are cleaned up.
llvm-svn: 117200
2010-10-23 08:10:43 +00:00
817bbac4f7
Enable ARM fastcc.
...
llvm-svn: 117194
2010-10-23 02:19:37 +00:00
ad79526471
Latency between CPSR def and branch is zero.
...
llvm-svn: 117192
2010-10-23 02:04:38 +00:00
696fe9d36c
Trailing whitespace.
...
llvm-svn: 117188
2010-10-22 23:48:29 +00:00
b171ca0a47
fix memory-layout assumption which only holds on little-endian systems
...
llvm-svn: 117176
2010-10-22 23:16:11 +00:00
2c9ae05c67
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.
...
llvm-svn: 117165
2010-10-22 22:12:16 +00:00
77a38320c7
Transfer implicit ops when forming load multiple and return instructions.
...
llvm-svn: 117151
2010-10-22 21:29:58 +00:00
9d0122af7d
Add correct NEON encodings for vqdmlal.
...
llvm-svn: 117134
2010-10-22 19:35:48 +00:00
2b80543fc2
Add the encoding information for the rest of the ARM mode multiply instructions.
...
llvm-svn: 117133
2010-10-22 19:15:30 +00:00
3d0264667f
Provide correct encodings for NEON vmlal.
...
llvm-svn: 117131
2010-10-22 19:05:25 +00:00
21abfc9450
Silence compiler warnings.
...
llvm-svn: 117128
2010-10-22 18:57:05 +00:00
f48719f1b5
Provide correct NEON encodings for vmla.
...
llvm-svn: 117126
2010-10-22 18:54:37 +00:00
6956a60563
More ARM multiply instuction binary encodings.
...
llvm-svn: 117121
2010-10-22 18:35:16 +00:00
08dd8c8295
Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by -arm-fastcc for now.
...
llvm-svn: 117119
2010-10-22 18:23:05 +00:00
f98df0849f
Parameterize a bit of ARM encoding information, simplifying some instruction
...
definitions.
llvm-svn: 117114
2010-10-22 17:42:06 +00:00
22261600a8
More ARM multiply instruction encoding information.
...
llvm-svn: 117108
2010-10-22 17:16:17 +00:00
1851090515
Making the e_machine configurable by the target backend in ELFObjectWriter.
...
llvm-svn: 117099
2010-10-22 15:52:49 +00:00
93bbe6599f
Add some basic ret instruction support to arm fast-isel.
...
llvm-svn: 117085
2010-10-22 01:28:00 +00:00
e2ec62e252
ARM binary encoding for some of the multiply instructions.
...
llvm-svn: 117080
2010-10-21 22:52:30 +00:00
a97becfaac
ARM binary encodings for MVN variants.
...
llvm-svn: 117076
2010-10-21 22:19:32 +00:00
5edb03ee57
ARM Binary encoding information for BFC/BFI instructions.
...
llvm-svn: 117072
2010-10-21 22:03:21 +00:00
2f8637d393
These don't need to be virtual.
...
llvm-svn: 117068
2010-10-21 21:47:51 +00:00
2bfa8ed045
Move the encoding logic for Q registers into getMachineOpValue().
...
llvm-svn: 117060
2010-10-21 20:49:13 +00:00
9e44cf2bb2
ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower
...
half of the Q register), rather than with just regno. This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.
llvm-svn: 117056
2010-10-21 20:21:49 +00:00
b353e4f579
Handle storing args to the stack for calls.
...
llvm-svn: 117055
2010-10-21 20:09:54 +00:00
73bc5b0f86
More load/store refactoring, call reg+offset simplification from within
...
the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.
llvm-svn: 117051
2010-10-21 19:40:30 +00:00
d37f0715b1
trailing whitespace
...
llvm-svn: 117050
2010-10-21 19:38:40 +00:00
6b7e401049
Add correct NEON encodings for vhadd and vrhadd.
...
llvm-svn: 117047
2010-10-21 18:55:04 +00:00
9561084188
Add correct encodings for NEON vaddw.s* and vaddw.u*.
...
llvm-svn: 117040
2010-10-21 18:20:25 +00:00
15c97706e8
Provide correct NEON encodings for vaddl.u* and vaddl.s*.
...
llvm-svn: 117039
2010-10-21 18:09:17 +00:00
b014abf3ef
The return value of this call is not used, so no point
...
in assigning it to a variable (gcc-4.6 warning).
llvm-svn: 117024
2010-10-21 16:06:28 +00:00
f4ebec03e0
putback r116983 and fix simple-fp-encoding.ll tests
...
llvm-svn: 116992
2010-10-21 03:40:16 +00:00
9e00f27e14
Revert r116983, which is breaking all the buildbots.
...
llvm-svn: 116987
2010-10-21 03:11:16 +00:00
15c2ac90ec
Add missing scheduling itineraries for transfers between core registers and VFP registers.
...
llvm-svn: 116983
2010-10-21 01:12:00 +00:00
6083502848
Implement correct encodings for NEON vadd, both integer and floating point.
...
llvm-svn: 116981
2010-10-21 00:48:00 +00:00
4ac3ed0219
Custom lower f64 args passed in integer registers.
...
llvm-svn: 116977
2010-10-21 00:01:47 +00:00
a65f914bb0
Add encoding for moving a value between two ARM core registers and a doublework
...
extension register.
llvm-svn: 116970
2010-10-20 23:37:40 +00:00
058190507b
Add encodings for movement between ARM core registers and single-precision
...
registers.
llvm-svn: 116961
2010-10-20 22:44:54 +00:00
ff37675c72
Fix crash introduced in 116852. 8573915.
...
llvm-svn: 116955
2010-10-20 22:03:37 +00:00
1898262a33
Remove remaining uses of ATTRIBUTE_UNUSED on variables, and delete three
...
#includes in the process.
llvm-svn: 116919
2010-10-20 08:27:02 +00:00
af719ef86b
Fix a TODO by removing some unnecesary copies.
...
llvm-svn: 116915
2010-10-20 08:02:24 +00:00
723159ef77
Fix backwards conditional.
...
llvm-svn: 116897
2010-10-20 01:10:01 +00:00
cb6fc2b2de
Add dynamic realignment when rematerializing the base register.
...
llvm-svn: 116886
2010-10-20 00:02:50 +00:00
f99ee7cd91
Nuke a commented out bit that got missed a while back.
...
llvm-svn: 116883
2010-10-19 23:48:47 +00:00
bbdc5d2ef9
Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any
...
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268
llvm-svn: 116879
2010-10-19 23:27:08 +00:00
3ed6338ff2
Update comments to remove obsolete references.
...
llvm-svn: 116863
2010-10-19 21:34:47 +00:00
710a2d9d46
Enable using vdup for vector constants which are splat of
...
integers by default, and remove the controlling flag, now
that LICM will hoist such vdup's. 8003375.
llvm-svn: 116852
2010-10-19 20:00:17 +00:00
63c7608c34
Re-enable register pressure aware machine licm with fixes. Hoist() may have
...
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.
llvm-svn: 116845
2010-10-19 18:58:51 +00:00
418204e523
Revert r116781 "- Add a hook for target to determine whether an instruction def
...
is", which breaks some nightly tests.
llvm-svn: 116816
2010-10-19 17:14:24 +00:00
8249dfe6ce
- Add a hook for target to determine whether an instruction def is
...
"long latency" enough to hoist even if it may increase spilling. Reloading
a value from spill slot is often cheaper than performing an expensive
computation in the loop. For X86, that means machine LICM will hoist
SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
instructions.
- Enable register pressure aware machine LICM by default.
llvm-svn: 116781
2010-10-19 00:55:07 +00:00
b6d61dc291
Support alignment for NEON vld-lane and vst-lane instructions.
...
llvm-svn: 116776
2010-10-19 00:16:32 +00:00
1c6fd774f7
ARM encoding information for [SU]SAT* instructions.
...
llvm-svn: 116768
2010-10-18 23:35:38 +00:00
7b92c2a9a0
Revert r116220 - thus turning arm fast isel back on by default.
...
llvm-svn: 116762
2010-10-18 22:53:53 +00:00
337a31133b
Don't recompute MachineRegisterInfo in the Optimize* method.
...
llvm-svn: 116750
2010-10-18 21:22:31 +00:00
6706f3c4b4
For Thumb2, try to use frame pointer references for stack slots even when a
...
base register is available. rdar://8525298
llvm-svn: 116729
2010-10-18 18:39:46 +00:00
00fe92da6b
ARM addrmode4 instructions (ldm, stm and friends) can't encode an immediate
...
offset for stack references. Make sure we take that into account when
deciding whether to reserver an emergency spill slot for the register
scavenger. rdar://8559625
llvm-svn: 116714
2010-10-18 16:48:59 +00:00
e8a0eaafe6
Grammar tweak.
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llvm-svn: 116712
2010-10-18 16:38:50 +00:00
167a700229
Remove the check for invalid calling conventions. Testing shows that they're
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working just fine.
llvm-svn: 116698
2010-10-18 06:49:12 +00:00
c103c668ce
Lift arg promotion from the X86 backend. This should be unified at some point.
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llvm-svn: 116694
2010-10-18 02:17:53 +00:00
a8a9f3c52b
Now that we handle all allocas via a non-SP reg offset remove all of the
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special case handling for ARM::SP.
llvm-svn: 116688
2010-10-17 11:08:44 +00:00
730764da62
Allow more load types to be materialized through the allocas.
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llvm-svn: 116683
2010-10-17 06:07:26 +00:00
d265b3fcfe
Optimize GEP off of intermediate allocas.
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llvm-svn: 116681
2010-10-17 01:51:42 +00:00
a0b9c2e9c0
Fix comment.
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llvm-svn: 116680
2010-10-17 01:42:53 +00:00
abc3a9d34b
Turn on AddOperator folding in GEP.
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llvm-svn: 116679
2010-10-17 01:41:46 +00:00
947e422c46
Use the i12 immediate versions of the load instructions - they're handled
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more in the post-passes.
llvm-svn: 116678
2010-10-17 01:40:27 +00:00
4262a22225
Add a MCObjectFormat class so that code common to all targets that use a
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single object format can be shared.
This also adds support for
mov zed+(bar-foo), %eax
on ELF and COFF targets.
llvm-svn: 116675
2010-10-16 18:23:53 +00:00
c918d550b6
Fix some funky formatting that got through.
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llvm-svn: 116653
2010-10-16 01:10:35 +00:00
5f5b922ec6
ARMCodeEmitter::emitMiscInstruction is dead. Long live
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ARMCodeEmitter::emitMiscInstruction!
llvm-svn: 116644
2010-10-15 23:35:12 +00:00
f410acbbd5
Make sure offset is 0 for load/store register to the stack call.
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llvm-svn: 116640
2010-10-15 23:07:10 +00:00
d2466687bf
Formatting.
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llvm-svn: 116635
2010-10-15 22:49:28 +00:00
a3e64c1791
Fix else if -> if in store machinery.
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llvm-svn: 116628
2010-10-15 22:32:37 +00:00
399add01d4
Reformatting. No functionalogicality changes.
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llvm-svn: 116625
2010-10-15 21:50:45 +00:00
a9b3901b47
Refactor ARM fast-isel reg + offset to be a base + offset.
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llvm-svn: 116622
2010-10-15 21:32:12 +00:00
90f74fe16a
Encoding information for the various ARM saturating add/sub instructions.
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llvm-svn: 116612
2010-10-15 19:49:46 +00:00
00ce8deae6
ARM binary encoding information for RSB and RSC instructions.
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llvm-svn: 116604
2010-10-15 18:42:41 +00:00
Anton Korobeynikov