4472801765
Use by-name rather than by-order matching for NEON operands.
...
llvm-svn: 120507
2010-12-01 00:28:25 +00:00
781b76bd78
Comment typo.
...
llvm-svn: 120504
2010-11-30 23:59:50 +00:00
d4b0873c06
Enable sibling call optimization of libcalls which are expanded during
...
legalization time. Since at legalization time there is no mapping from
SDNode back to the corresponding LLVM instruction and the return
SDNode is target specific, this requires a target hook to check for
eligibility. Only x86 and ARM support this form of sibcall optimization
right now.
rdar://8707777
llvm-svn: 120501
2010-11-30 23:55:39 +00:00
05632cb5cc
Rename operands to match ARM documentation. No functionality change.
...
llvm-svn: 120500
2010-11-30 23:54:45 +00:00
ee48d2daaa
Fix typo.
...
llvm-svn: 120499
2010-11-30 23:51:41 +00:00
903add84d9
Enhance DSE to handle the variable index case in PR8657.
...
llvm-svn: 120498
2010-11-30 23:43:23 +00:00
38d90de7c3
Trailing whitespace.
...
llvm-svn: 120497
2010-11-30 23:29:24 +00:00
545cbdf063
Support/PathV2: Implement reverse iteration and parent_path.
...
llvm-svn: 120496
2010-11-30 23:28:07 +00:00
e1d3603dc6
Support/ADT/StringRef: Add find_last_of.
...
llvm-svn: 120495
2010-11-30 23:27:35 +00:00
c440e79126
Thanks to JimG for catching this!
...
llvm-svn: 120494
2010-11-30 23:27:18 +00:00
fce64c938a
Coding style. No significant functionality. Abandon linear scan style
...
in favor of the widespread llvm style. Capitalize variables and add
newlines for visual parsing. Rename variables for readability.
And other cleanup.
llvm-svn: 120490
2010-11-30 23:18:47 +00:00
5c51fcda81
Inline classes that were used in only one place.
...
llvm-svn: 120488
2010-11-30 23:16:25 +00:00
c0f3379ae0
teach DSE to use GetPointerBaseWithConstantOffset to analyze
...
may-aliasing stores that partially overlap with different base
pointers. This implements PR6043 and the non-variable part of
PR8657
llvm-svn: 120485
2010-11-30 23:05:20 +00:00
a9e3df7aa0
* Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as
...
t_addrmode_s4, but with a different scaling factor.
* Encode the Thumb1 load and store instructions. This involved a bit of
refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
were removed.
llvm-svn: 120482
2010-11-30 22:57:21 +00:00
8335e8fa63
Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the
...
Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.
llvm-svn: 120481
2010-11-30 22:45:47 +00:00
2d3e5c1aec
Fix handling of ARM negative pc-relative fixups for loads and stores.
...
llvm-svn: 120480
2010-11-30 22:40:36 +00:00
e28618de59
move GetPointerBaseWithConstantOffset out of GVN into ValueTracking.h
...
llvm-svn: 120476
2010-11-30 22:25:26 +00:00
50162e3c2a
remove a fixed fixme
...
llvm-svn: 120474
2010-11-30 22:18:11 +00:00
6712251f41
Make DeleteDeadInstruction be a static function, move some code around.
...
llvm-svn: 120471
2010-11-30 21:58:14 +00:00
a964f4de76
Move X86InstrFPStack.td over to PseudoI as well.
...
llvm-svn: 120470
2010-11-30 21:57:32 +00:00
51d67ce2ff
switch RemoveAccessedObjects to use AliasAnalysis::Location to simplify
...
the code. We now get accurate sizes on Loads, though it surely doesn't
matter in practice.
llvm-svn: 120469
2010-11-30 21:47:58 +00:00
f80b39986f
two improvements to RemoveAccessedObjects:
...
1. if the underlying pointer passed in can be resolved
to any argument or alloca, then we don't need to scan.
Previously we would only avoid the scan if the alloca
or byval was actually considered dead.
2. The dead store processing code is itself completely
dead and didn't handle volatile stores right anyway,
so delete it. This allows simplifying the interface
to RemoveAccessedObjects.
llvm-svn: 120467
2010-11-30 21:38:30 +00:00
a87065807f
Migrate X86InstrControl.td to use PseudoI and fix a couple of 80-col violations
...
while I'm in there.
llvm-svn: 120466
2010-11-30 21:37:36 +00:00
7fe08b67fa
remove the "undead" terminology, which is nonstandard and never
...
made sense to me. We now have a set of dead stack objects, and
they become live when loaded. Fix a theoretical problem where
we'd pass in the wrong pointer to the alias query.
llvm-svn: 120465
2010-11-30 21:32:12 +00:00
127818d746
move call handling in handleEndBlock up a bit, and simplify it.
...
If the call might read all the allocas, stop scanning early.
Convert a vector to smallvector, shrink SmallPtrSet to 16 instead
of 64 to avoid crazy linear scans.
llvm-svn: 120463
2010-11-30 21:18:46 +00:00
d3a58c8fa1
Avoid exponential growth of a table. It feels like
...
there should be a better way to do this. PR 8679.
llvm-svn: 120457
2010-11-30 20:23:21 +00:00
0dc6246fc0
Provide Thumb2 encodings for a few miscellaneous instructions.
...
llvm-svn: 120455
2010-11-30 20:00:01 +00:00
60a8b3dab8
various cleanups and code simplification
...
llvm-svn: 120454
2010-11-30 19:48:15 +00:00
51c28a93cc
make getPointerSize a static function. Add ivars to DSE for
...
AA and MD pass info instead of using getAnalysis<> all over.
llvm-svn: 120453
2010-11-30 19:34:42 +00:00
77d79fa25f
reduce indentation, clean up TD use a bit.
...
llvm-svn: 120452
2010-11-30 19:28:23 +00:00
233890547d
Add FIXME
...
llvm-svn: 120451
2010-11-30 19:25:56 +00:00
299382e8cb
Add encoding support for Thumb2 PLD and PLI instructions.
...
llvm-svn: 120449
2010-11-30 19:19:31 +00:00
78b4efb472
Noticed this on inspection, fix and update some comments.
...
llvm-svn: 120447
2010-11-30 19:14:07 +00:00
b63ba73b1b
enhance isRemovable to refuse to delete volatile mem transfers
...
now that DSE hacks on them. This fixes a regression I introduced,
by generalizing DSE to hack on transfers.
llvm-svn: 120445
2010-11-30 19:12:10 +00:00
3b4e2ab5f3
Pseudo-ize ARM MOVPCRX
...
llvm-svn: 120442
2010-11-30 18:56:36 +00:00
ebcd9c9258
Provide encodings for a few more load/store variants.
...
llvm-svn: 120439
2010-11-30 18:38:28 +00:00
cd5e30f6c6
Pseudo-ize BX_CALL and friends. Remove dead instruction format classes.
...
rdar://8685712
llvm-svn: 120438
2010-11-30 18:30:19 +00:00
ea41dfe385
add TLI support indicating that jumps are more expensive than logical operations
...
and use this to disable a specific optimization. Patch by Micah Villmow!
llvm-svn: 120435
2010-11-30 18:12:52 +00:00
e9baf13657
ptx: add command-line options for gpu target and ptx version
...
llvm-svn: 120423
2010-11-30 10:14:14 +00:00
3a8ae23313
Fix some grammar in comments I noticed.
...
llvm-svn: 120416
2010-11-30 09:11:54 +00:00
ed13239dc0
This defaults to GenericDomain.
...
llvm-svn: 120415
2010-11-30 09:11:07 +00:00
15084f085d
PR5207: Make APInt::set(), APInt::clear() and APInt::flip() return void.
...
llvm-svn: 120413
2010-11-30 09:02:01 +00:00
ef62f57d4f
Implement a PseudoI class and transfer the sse instructions over to use
...
it.
llvm-svn: 120412
2010-11-30 08:57:23 +00:00
2d1bcf4aea
Fix insertion point in pcmp expander.
...
While I'm there, clean up too many \n even for me.
llvm-svn: 120411
2010-11-30 08:20:21 +00:00
1a86e8461a
Fix some cleanups from my last patch.
...
llvm-svn: 120410
2010-11-30 08:10:28 +00:00
811c936ed5
Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost
...
certainly be made more generic. But it does allow us to parse something like:
ldr r3, [r2, r4]
correctly in Thumb mode.
llvm-svn: 120408
2010-11-30 07:44:32 +00:00
d816204056
ptx: add ld instruction
...
support register and register-immediate addressing mode
todo: immediate and register-register addressing mode
llvm-svn: 120407
2010-11-30 07:34:44 +00:00
58b779e9c2
Rewrite the main DSE loop to be written in terms of reasoning
...
about pairs of AA::Location's instead of looking for MemDep's
"Def" predicate. This is more powerful and general, handling
memset/memcpy/store all uniformly, and implementing PR8701 and
probably obsoleting parts of memcpyoptimizer.
This also fixes an obscure bug with init.trampoline and i8
stores, but I'm not surprised it hasn't been hit yet. Enhancing
init.trampoline to carry the size that it stores would allow
DSE to be much more aggressive about optimizing them.
llvm-svn: 120406
2010-11-30 07:23:21 +00:00
fa6657cec0
Rewrite mwait and monitor support and custom lower arguments.
...
Fixes PR8573.
llvm-svn: 120404
2010-11-30 07:20:12 +00:00
e3ea1cba79
Add a puts optimization that converts puts() to putchar('\n').
...
llvm-svn: 120398
2010-11-30 06:19:18 +00:00
3590ef817c
rename a function and reduce some indentation, no functionality change.
...
llvm-svn: 120391
2010-11-30 05:30:45 +00:00
d4900a644c
Stub out a new LiveDebugVariables pass.
...
This analysis is going to run immediately after LiveIntervals. It will stay
alive during register allocation and keep track of user variables mentioned in
DBG_VALUE instructions.
When the register allocator is moving values between registers and the stack, it
is very hard to keep track of DBG_VALUE instructions. We usually get it wrong.
This analysis maintains a data structure that makes it easy to update DBG_VALUE
instructions.
llvm-svn: 120385
2010-11-30 02:17:10 +00:00
b438ef236c
remove the pointless check of MemoryUseIntrinsic from
...
is trivially dead, since these have side effects. This makes the
(misnamed) MemoryUseIntrinsic class dead, so remove it.
llvm-svn: 120382
2010-11-30 02:03:47 +00:00
d540a5d842
strength reduce this.
...
llvm-svn: 120381
2010-11-30 01:56:13 +00:00
afbc0c2b8c
getLocationForDest should work for memset as well.
...
llvm-svn: 120380
2010-11-30 01:48:20 +00:00
2227a8a192
rename doesClobberMemory -> hasMemoryWrite to be more specific, and
...
remove an actively-wrong comment.
llvm-svn: 120378
2010-11-30 01:37:52 +00:00
9d179d911d
clean up handling of 'free', detangling it from everything else.
...
It can be seriously improved, but at least now it isn't intertwined
with the other logic.
llvm-svn: 120377
2010-11-30 01:28:33 +00:00
ddce9f3757
Minor cleanups. No functional change.
...
llvm-svn: 120372
2010-11-30 00:50:22 +00:00
8294a30d54
s/ARM::BRIND/ARM::BX/g to coincide with r120366.
...
llvm-svn: 120371
2010-11-30 00:48:15 +00:00
90c4947df7
enhance basicaa to return "Mod" for a memcpy call when the
...
queried location doesn't overlap the source, and add a testcase.
llvm-svn: 120370
2010-11-30 00:43:16 +00:00
62718de2b9
Add correct encoding for "bl __aeabi_read_tp". However, the asm matcher isn't
...
able to match this yet.
llvm-svn: 120369
2010-11-30 00:34:08 +00:00
9a146372b5
Teach basicaa that memset's modref set is at worst "mod" and never
...
contains "ref".
Enhance DSE to use a modref query instead of a store-specific hack
to generalize the "ignore may-alias stores" optimization to handle
memset and memcpy.
llvm-svn: 120368
2010-11-30 00:28:45 +00:00
027bd47e3e
Rename BX/BRIND/etc patterns to clarify which is actually the BX instruction
...
and which are pseudos.
llvm-svn: 120366
2010-11-30 00:24:05 +00:00
85a8a72d85
Add some encoding for the adr instruction. Labels still need to be finished.
...
llvm-svn: 120365
2010-11-30 00:18:30 +00:00
e22c7322b8
Correct Thumb2 encodings for a much wider range of loads and stores.
...
llvm-svn: 120364
2010-11-30 00:14:31 +00:00
c3c754f750
my previous patch would cause us to start deleting some volatile
...
stores, fix and add a testcase.
llvm-svn: 120363
2010-11-30 00:12:39 +00:00
49408cef39
Make a few more ARM pseudo instructions actually use the PseudoInst base class.
...
llvm-svn: 120362
2010-11-30 00:09:06 +00:00
ce3d6ca564
Predicate encoding should be withing {}s. And general cleanup.
...
llvm-svn: 120361
2010-11-30 00:08:20 +00:00
795f211418
Predicate encoding should be withing {}s.
...
llvm-svn: 120360
2010-11-30 00:05:25 +00:00
d4f1090948
two changes to DSE that shouldn't affect anything:
...
1. Don't bother trying to optimize:
lifetime.end(ptr)
store(ptr)
as it is undefined, and therefore shouldn't exist.
2. Move the 'storing a loaded pointer' xform up, simplifying
the may-aliased store code.
llvm-svn: 120359
2010-11-30 00:01:19 +00:00
318ce7cb3f
Fix the encoding of VLD4-dup alignment.
...
The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function. Use it
for all the VLD-dup instructions for the sake of consistency.
llvm-svn: 120358
2010-11-30 00:00:42 +00:00
0b27b68164
Rename VLDnDUP instructions with double-spaced registers
...
in an attempt to make things a little more consistent.
llvm-svn: 120357
2010-11-30 00:00:38 +00:00
431ac4ef50
Add support for NEON VLD3-dup instructions.
...
The encoding for alignment in VLD4-dup instructions is still a work in progress.
llvm-svn: 120356
2010-11-30 00:00:35 +00:00
9de9a73433
Simplify definitions of the ARM eh.sjlj.*jmp pseudo instructions.
...
llvm-svn: 120354
2010-11-29 23:51:31 +00:00
0c51bb4b25
Parameterize ARMPseudoInst size property.
...
llvm-svn: 120353
2010-11-29 23:48:41 +00:00
cb803b043b
Add a few missing initializers.
...
llvm-svn: 120350
2010-11-29 23:41:10 +00:00
b4df1d5a3e
prune an llvmcontext include and simplify some code.
...
llvm-svn: 120347
2010-11-29 23:35:33 +00:00
6f3a90b549
Generalize the darwin wrapper hack to work with generic macho triples as well as darwin ones.
...
llvm-svn: 120346
2010-11-29 23:29:54 +00:00
32ff5586fc
Nuke trailing whitespace.
...
llvm-svn: 120344
2010-11-29 23:18:01 +00:00
9f0356b3cc
Nuke a FIXME. No need to be fancier here, as ARM handles constant pools
...
locations and formatting specially. rdar://7353441
llvm-svn: 120343
2010-11-29 23:09:20 +00:00
50d662b6cb
Provide Thumb2 encodings for basic loads and stores.
...
llvm-svn: 120340
2010-11-29 22:44:32 +00:00
9a133f623c
Mark Darwin call instructions as using "r7" to prevent the frame-register
...
assignment instructions from being moved below / above calls.
rdar://8690640
llvm-svn: 120339
2010-11-29 22:43:27 +00:00
d5cfca1e3d
Nuke dead isCodeGenOnly annotation and extraneous comment.
...
llvm-svn: 120338
2010-11-29 22:40:58 +00:00
1883d94630
tidy up.
...
llvm-svn: 120335
2010-11-29 22:38:48 +00:00
ee7c5659d7
Thumb encodings for conditional moves.
...
llvm-svn: 120334
2010-11-29 22:37:46 +00:00
7ec3d34553
Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw
...
instructions. This simplifies instruction printing and disassembly.
llvm-svn: 120333
2010-11-29 22:37:40 +00:00
ebad2f9d36
Support: Add PathV2 implementation.
...
llvm-svn: 120329
2010-11-29 22:28:51 +00:00
5da8cae9ec
Refactor some of the "disassembly-only" instructions into a base class. This
...
reduces some code duplication.
llvm-svn: 120326
2010-11-29 22:15:03 +00:00
2e8793482c
fix PR8677, patch by Jakub Staszak!
...
llvm-svn: 120325
2010-11-29 21:59:31 +00:00
43b0c6d94f
Update fastisel for the changes in r120272.
...
llvm-svn: 120324
2010-11-29 21:56:23 +00:00
28218aa8f1
Transform (extractvalue (load P), ...) to (load (gep P, 0, ...)) if the load has no other uses, shrinking the load.
...
llvm-svn: 120323
2010-11-29 21:56:20 +00:00
81af4f9eb1
Rename t2 TBB and TBH instructions to reference that they encode the jump table
...
data. Next up, pseudo-izing them.
llvm-svn: 120320
2010-11-29 21:28:32 +00:00
ba3a8fa7ab
Improving the factoring of several instruction encodings.
...
llvm-svn: 120317
2010-11-29 20:38:48 +00:00
a98214de10
Teach ConstantFoldInstruction() how to fold insertvalue and extractvalue.
...
llvm-svn: 120316
2010-11-29 20:36:52 +00:00
54c9eb6fff
Now to chant the magical incantation that will exorcise the System library
...
from LLVM forever:
grep -lR "llvm/System" * | grep -v .svn | xargs sed -ie 's#llvm/System#llvm/Support#g'
llvm-svn: 120314
2010-11-29 19:44:50 +00:00
77ab165afe
Add support for NEON VLD3-dup instructions.
...
llvm-svn: 120312
2010-11-29 19:35:29 +00:00
8022367809
Fix copy-and-paste errors in VLD2-dup scheduling itineraries.
...
llvm-svn: 120311
2010-11-29 19:35:23 +00:00
58bc36a3a9
ARM Pseudo-ize tBR_JTr.
...
llvm-svn: 120310
2010-11-29 19:32:47 +00:00
e9608b3f01
Thumb2 encodings for MSR and MRS.
...
llvm-svn: 120309
2010-11-29 19:29:15 +00:00
2fdf32fa2c
Thumb2 encodings for system instructions.
...
llvm-svn: 120307
2010-11-29 19:22:08 +00:00
b044bc67f4
Thumb2 encodings for branches and IT blocks.
...
llvm-svn: 120306
2010-11-29 18:54:38 +00:00
0591656b13
The ARM BR_JT* pseudos don't need to use the printer jtblock_operand node to
...
get the pretty-printer. That's handled explicityly by the MC lowering now.
llvm-svn: 120305
2010-11-29 18:53:24 +00:00
ab425d8360
I swear I did a make clean and make before committing all this...
...
llvm-svn: 120304
2010-11-29 18:47:54 +00:00
150b1ad7f8
Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos.
...
llvm-svn: 120303
2010-11-29 18:37:44 +00:00
4d2e1501ad
Missed a spot.
...
llvm-svn: 120301
2010-11-29 18:29:55 +00:00
447762da85
Merge System into Support.
...
llvm-svn: 120298
2010-11-29 18:16:10 +00:00
1ff0bfa28f
Handle lshr for i128 correctly on SPU also when
...
shiftamount > 7.
llvm-svn: 120288
2010-11-29 14:44:28 +00:00
dc620afd1e
Enable PostRA scheduling for SPU.
...
This speeds up selected test cases with up to
5% - no slowdowns observed.
llvm-svn: 120286
2010-11-29 10:30:25 +00:00
1842ada3ad
Allow machine LICM to do its job on SPU.
...
-return a sensible value for register pressure
-add pattern to 'ila' instrucion
llvm-svn: 120285
2010-11-29 10:08:09 +00:00
427add8f24
Add missing i128 case.
...
llvm-svn: 120284
2010-11-29 09:36:26 +00:00
abcab28f9b
Add some dead stores to pacify my least favorite GCC warning: may be
...
uninitialized. The warning is terrible, has incorrect source locations, and has
a huge false positive rate such as *all* of these.
If anyone has a better solution, please let me know. Alternatively, I'll
happily add -Wno-uninitialized to the -Werror build mode. Maybe I can even do
it *only* when building with GCC instead of Clang.
llvm-svn: 120281
2010-11-29 01:41:13 +00:00
232e52cfb7
Add more Thumb encodings.
...
llvm-svn: 120279
2010-11-29 01:07:48 +00:00
ccba1a8d95
More Thumb encodings.
...
llvm-svn: 120278
2010-11-29 01:00:43 +00:00
9600e97c60
Add Thumb encodings for REV instructions.
...
llvm-svn: 120277
2010-11-29 00:42:50 +00:00
775899eb2e
Add more Thumb encodings.
...
llvm-svn: 120272
2010-11-29 00:18:15 +00:00
e5e1f9ad0f
Make EmitIntValue non virtual.
...
llvm-svn: 120271
2010-11-28 23:22:44 +00:00
0710e3771f
Forgot the MCPureStreamer::EmitValue in the previous commit.
...
llvm-svn: 120270
2010-11-28 23:13:47 +00:00
a084fd6e9d
Move EmitValue to MCObjectStreamer.
...
llvm-svn: 120269
2010-11-28 23:08:47 +00:00
c4774795ce
Move lowering of TLS_addr32 and TLS_addr64 to X86MCInstLower.
...
llvm-svn: 120263
2010-11-28 21:16:39 +00:00
3447fb01c0
PR5207: change APInt::doubleToBits() and APInt::floatToBits() to be
...
static methods that return a new APInt.
llvm-svn: 120261
2010-11-28 21:04:48 +00:00
7e8a99b1c3
fix PR8686, accepting a 'b' suffix at the end of all the setcc
...
instructions. I choose to handle this with an asmparser hack,
though it could be handled by changing all the instruction definitions
to allow be "setneb" instead of "setne". The asm parser hack is
better in this case, because we want the disassembler to produce
setne, not setneb.
llvm-svn: 120260
2010-11-28 20:23:50 +00:00
a7e04b04c5
add a function to the C api to get the context out of a module, patch
...
by Eric Dobson!
llvm-svn: 120259
2010-11-28 20:03:44 +00:00
235b66c40f
When emitting a single function with cppgen=function, you don't want to emit
...
initializers of global variables used in the function.
Also make sure to emit the operands of a constant.
llvm-svn: 120253
2010-11-28 18:00:53 +00:00
e5b7415b21
Fixed verson of r120245.
...
Factor some duplicated code into MCObjectStreamer::EmitLabel.
llvm-svn: 120248
2010-11-28 17:18:55 +00:00
1679580cc9
Revert previous patch while I debug the darwin bootstrap failure.
...
llvm-svn: 120246
2010-11-28 16:22:59 +00:00
d4b3feb3f7
Factor some duplicated code into MCObjectStreamer::EmitLabel.
...
llvm-svn: 120245
2010-11-28 15:54:36 +00:00
b746531c2c
Avoid code duplication in the many unsupported EmitGPRel32Value implementations.
...
llvm-svn: 120243
2010-11-28 15:09:24 +00:00
164c797676
Move the PTXMCAsmStreamer class to the .cpp file.
...
llvm-svn: 120241
2010-11-28 14:48:34 +00:00
8a3a7923eb
Define generic 1, 2 and 4 byte pc relative relocations. They are common
...
and at least the 4 byte one will be needed to implement the .cfi_* directives.
llvm-svn: 120240
2010-11-28 14:17:56 +00:00
2d790df105
Add support for NEON VLD2-dup instructions.
...
llvm-svn: 120236
2010-11-28 06:51:26 +00:00
f9b96c474f
Fix a comment typo.
...
llvm-svn: 120235
2010-11-28 06:51:19 +00:00
04b2c94205
Another minor refactoring for VLD1DUP instructions.
...
The op11_8 field is the same for all of them so put it in the instruction
classes instead of specifying it separately for each instruction.
llvm-svn: 120234
2010-11-28 06:51:15 +00:00
62a6f7eda6
Add entry in getTargetNodeName() for ARMISD::VBICIMM.
...
llvm-svn: 120233
2010-11-28 06:51:11 +00:00
7283b8d18c
Move more PEI-related hooks to TFI
...
llvm-svn: 120229
2010-11-27 23:05:25 +00:00
d08fbd19f5
Move callee-saved regs spills / reloads to TFI
...
llvm-svn: 120228
2010-11-27 23:05:03 +00:00
5d882894d8
Lower TLS_addr32 and TLS_addr64.
...
llvm-svn: 120225
2010-11-27 20:43:02 +00:00
eab0800695
Implement the data16 prefix.
...
llvm-svn: 120224
2010-11-27 20:29:45 +00:00
f2d08136bf
Remove PIC16 remnants.
...
llvm-svn: 120223
2010-11-27 18:20:30 +00:00
e308b8edab
macho-dump: Add support for --dump-section-data and tweak a few format strings.
...
llvm-svn: 120219
2010-11-27 13:58:16 +00:00
83224fc391
macho-dump: Add support for dumping symbol table entries.
...
llvm-svn: 120218
2010-11-27 13:52:53 +00:00
8680ce6ffc
macho-dump: Add support for dumping string table data.
...
llvm-svn: 120217
2010-11-27 13:46:11 +00:00
0ac77d526d
macho-dump: Add support for dumping relocation entries.
...
llvm-svn: 120216
2010-11-27 13:39:48 +00:00
5867690cfa
macho-dump: Add support for dumping sections.
...
llvm-svn: 120215
2010-11-27 13:33:15 +00:00
c983afc5a1
macho-dump: Add support for dumping dysymtab indirect symbol table.
...
llvm-svn: 120214
2010-11-27 13:26:12 +00:00
032f08b556
Unbreak build for newer GCCs.
...
llvm-svn: 120205
2010-11-27 09:08:25 +00:00
33dab2a6ee
macho-dump: Add support for dumping symtab and dysymtab commands.
...
llvm-svn: 120204
2010-11-27 08:33:44 +00:00
a8070e0284
macho-dump: Add support for dumping segment load commands.
...
llvm-svn: 120203
2010-11-27 08:22:29 +00:00
8ba5f39f70
Second attempt at fixing the performance regressions introduced
...
by my recent GVN improvement. Looking through a single layer of
PHI nodes when attempting to sink GEPs, we need to iteratively
look through arbitrary PHI nests.
llvm-svn: 120202
2010-11-27 08:15:55 +00:00
65dc891942
raw_ostream::write_escaped: Add a UseHexEscapes argument.
...
llvm-svn: 120200
2010-11-27 07:59:50 +00:00
768a5e8004
Fix a comment.
...
llvm-svn: 120199
2010-11-27 07:39:37 +00:00
3977e7d22c
Object/Mach-O: Add header and load command information.
...
llvm-svn: 120198
2010-11-27 07:19:41 +00:00
d74cf2c8f6
Refactor. Set alignment bit in VLD1-dup instruction classes.
...
llvm-svn: 120197
2010-11-27 07:12:02 +00:00
feb1c5d830
Object/Mach-O: Validate Mach-O magic and initialize format info.
...
llvm-svn: 120195
2010-11-27 06:39:22 +00:00
c92eea0175
Add NEON VLD1-dup instructions (load 1 element to all lanes).
...
llvm-svn: 120194
2010-11-27 06:35:16 +00:00
3a63f9d852
Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions.
...
I added these instructions recently but I have no idea where these "1"
values in the NextCycles field came from. As far as I can tell now,
these instruction stages are clearly intended to overlap.
llvm-svn: 120193
2010-11-27 06:35:09 +00:00
1df8d83a55
MC/Mach-O: Start stubbing out a Mach-O object file wrapper.
...
llvm-svn: 120190
2010-11-27 05:38:50 +00:00
4b128a5d4f
Reduce nesting.
...
llvm-svn: 120189
2010-11-27 05:18:48 +00:00
eab6e401fe
MC/Mach-O: Migrate more constants into MachOFormat.h.
...
llvm-svn: 120188
2010-11-27 04:59:14 +00:00
a5f50c16f7
MC/Mach-O: Switch to using MachOFormat.h.
...
- I'm leaving MachO.h, because I believe it has external consumers, but I would really like to eliminate it (we have stylistic disagreements with one another).
llvm-svn: 120187
2010-11-27 04:38:36 +00:00
2263ca4834
MC/Mach-O: Introduce Object/MachOFormat for describing purely platform / machine
...
independent information on the Mach object format, and move some stuff from
MachObjectWriter.cpp there.
llvm-svn: 120186
2010-11-27 04:19:38 +00:00
bf4a4e4ad9
Remove the unused TheTarget member.
...
llvm-svn: 120168
2010-11-26 04:24:21 +00:00
f13f442b1a
Fix Whitespace.
...
llvm-svn: 120166
2010-11-26 04:16:08 +00:00
a12095d26d
Move tree navigation to a new Path class that doesn't have to be a template.
...
The path also holds a reference to the root node, and that allows important
iterator accessors like start() and stop() to have no conditional code. (When
the compiler is clever enough to remove it.)
llvm-svn: 120165
2010-11-26 01:39:40 +00:00
7c2acd022e
Use multiple 0x66 prefixes so that all nops up to 15 bytes are a single instruction.
...
llvm-svn: 120147
2010-11-25 17:14:16 +00:00
aef5bd049f
Namespacify.
...
llvm-svn: 120146
2010-11-25 16:42:51 +00:00
f8e127eaf6
Factor some code to parseSectionFlags and fix the default type of a section.
...
llvm-svn: 120145
2010-11-25 15:32:56 +00:00
b8de00ee07
Treat a call of function pointer like a load of the pointer when considering
...
whether the pointer can be replaced with the global variable it is a copy of.
Fixes PR8680.
llvm-svn: 120126
2010-11-24 22:04:20 +00:00
9f75d5df0b
Behave a bit more like gnu as and use the symbol (instead of the section)
...
for any relocation to a symbol defined in a tls section.
llvm-svn: 120121
2010-11-24 21:57:39 +00:00
708ac4d6ad
Relocate with the symbol if the relocation is of kind NTPOFF.
...
Patch by David Meyer, I added the test.
llvm-svn: 120104
2010-11-24 19:23:50 +00:00
e98d483b71
Fix and add tests for all cases in x86 and x86_64 where gnu as implicitly
...
sets the type of a symbol to STT_TLS.
llvm-svn: 120100
2010-11-24 18:51:21 +00:00
8ad3b25633
Updating MBlaze .mask and .frame directives to match GCC's output and fixing regression introduced in 120095 by checking MCStreamer::hasRawTextSupport.
...
llvm-svn: 120097
2010-11-24 16:32:35 +00:00
51917b868d
1. Fixing error where basic block labels were not being printed out when they need to be for the MBlaze backend because AsmPrinter::isBlockOnlyReachableByFallthrough does not take into account delay slots.
...
2. Re-adding .mask and .frame directives in printed assembly.
3. Adding .ent and .end directives in printed assembly.
4. Minor cleanups to MBlaze backend.
llvm-svn: 120095
2010-11-24 15:39:32 +00:00
e0a1d2b32c
Use i8 as SETCC result type for i1 in SPU.
...
llvm-svn: 120092
2010-11-24 12:59:16 +00:00
97fc68774c
Allow for 'fcmp ogt' in SPU.
...
Fix by Visa Putkinen!
llvm-svn: 120090
2010-11-24 11:42:17 +00:00
4e70ac7b68
If a symbol is used as tls, mark it as tls even if not declare as so. Probably
...
fixes PR8659.
llvm-svn: 120076
2010-11-24 02:19:40 +00:00
6bf4e6d8b2
add a MemoryBuffer::getOpenFile method, which turns an open
...
file descriptor into a MemoryBuffer (and closes the FD).
llvm-svn: 120065
2010-11-23 22:20:27 +00:00
0488d564e1
Rename SimplifyDistributed to the more meaningfull name SimplifyByFactorizing.
...
llvm-svn: 120051
2010-11-23 20:42:39 +00:00
94a622af4c
The srem -> urem transform is not safe for any divisor that's not a power of two.
...
E.g. -5 % 5 is 0 with srem and 1 with urem.
Also addresses Frits van Bommel's comments.
llvm-svn: 120049
2010-11-23 20:33:57 +00:00
433c1679cf
Replace calls to ConstantFoldInstruction with calls to SimplifyInstruction
...
in two places that are really interested in simplified instructions, not
constants.
llvm-svn: 120044
2010-11-23 20:26:33 +00:00
bb2cd025a9
Constant folding here is pointless, because InstructionSimplify
...
(which does constant folding and more) is called a few lines
later.
llvm-svn: 120042
2010-11-23 20:24:21 +00:00
8e21bf84e8
Move the ARM reloc constants to Support/ELF.h
...
llvm-svn: 120035
2010-11-23 19:40:36 +00:00
d7d2cf7842
Recognize sign/zero-extended constant BUILD_VECTORs for VMULL operations.
...
We need to check if the individual vector elements are sign/zero-extended
values. For now this only handles constants values. Radar 8687140.
llvm-svn: 120034
2010-11-23 19:38:38 +00:00
b5afa65b0a
InstCombine: Reduce "X shift (A srem B)" to "X shift (A urem B)" iff B is positive.
...
This allows to transform the rem in "1 << ((int)x % 8);" to an and.
llvm-svn: 120028
2010-11-23 18:52:42 +00:00
60813f96e0
Propagate LeftDistributes and RightDistributes into their only uses.
...
Stylistic improvement suggested by Frits van Bommel.
llvm-svn: 120026
2010-11-23 15:28:14 +00:00
22df741687
Fix typo pointed out by Frits van Bommel and Marius Wachtler.
...
llvm-svn: 120025
2010-11-23 15:25:34 +00:00
adc7771f18
Exploit distributive laws (eg: And distributes over Or, Mul over Add, etc) in a
...
fairly systematic way in instcombine. Some of these cases were already dealt
with, in which case I removed the existing code. The case of Add has a bunch of
funky logic which covers some of this plus a few variants (considers shifts to be
a form of multiplication), which I didn't touch. The simplification performed is:
A*B+A*C -> A*(B+C). The improvement is to do this in cases that were not already
handled [such as A*B-A*C -> A*(B-C), which was reported on the mailing list], and
also to do it more often by not checking for "only one use" if "B+C" simplifies.
llvm-svn: 120024
2010-11-23 14:23:47 +00:00
e1b6c273b8
Division by pow-of-2 is not cheap on SPU, do it with
...
shifts.
llvm-svn: 120022
2010-11-23 13:27:59 +00:00
f6c05b1d01
Implement the rex64 prefix.
...
llvm-svn: 120017
2010-11-23 11:23:24 +00:00
a021988d64
Expand a little on the description of what InstructionSimplify does.
...
llvm-svn: 120016
2010-11-23 10:50:08 +00:00
763dec0ab8
Clarify that constant folding of instructions applies when all operands
...
are constant. There was in fact one exception to this (phi nodes) - so
remove that exception (InstructionSimplify handles this so there should
be no loss).
llvm-svn: 120015
2010-11-23 10:16:18 +00:00
5c1d4e3b1e
Invalidate the layout on any relaxation, not just Instructions. Bug found by David Meyer.
...
While here, remove unused argument and rename UpdateForSlide to Invalidate.
llvm-svn: 120009
2010-11-23 08:08:33 +00:00
3c7cab1402
Produce a relocation for pcrel absolute values. Based on a patch by David Meyer.
...
llvm-svn: 120006
2010-11-23 07:20:12 +00:00
2dd97d2d60
Revert functionality doug added in r98575 that was never
...
documented and only used by some clang stuff I just removed.
llvm-svn: 120002
2010-11-23 06:09:51 +00:00
6e13aa1d3b
Reuse data fragments while lowering. Patch by David Meyer.
...
llvm-svn: 119999
2010-11-23 05:49:35 +00:00
527da1b6e2
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
...
llvm-svn: 119990
2010-11-23 03:31:01 +00:00
4329e078ac
add a 'LLVMConstIntOfArbitraryPrecision' api to the C api,
...
patch by Greg Pfeil!
llvm-svn: 119989
2010-11-23 02:47:22 +00:00
e5afa15b77
duncan's spider sense was right, I completely reversed the condition
...
on this instcombine xform. This fixes a miscompilation of 403.gcc.
llvm-svn: 119988
2010-11-23 02:42:04 +00:00
767a1e9adc
Fixed some style issues (no _, no spc after !)
...
llvm-svn: 119986
2010-11-22 22:05:16 +00:00
6e39a50fd5
Remove duplicated constants. Thanks to Jason for noticing it.
...
llvm-svn: 119985
2010-11-22 21:49:05 +00:00
f1ebb63161
InstCombine: Implement X - A*-B -> X + A*B.
...
llvm-svn: 119984
2010-11-22 20:31:27 +00:00
16b75262c4
Make the <ARCH>ELFObjectWriter statics private
...
llvm-svn: 119982
2010-11-22 18:57:00 +00:00
84ffdd5cf1
Fix misplaced statics.
...
llvm-svn: 119981
2010-11-22 18:47:05 +00:00
a262546df7
Kill trailing whitespace
...
llvm-svn: 119979
2010-11-22 18:42:07 +00:00
7c7d0ef287
Refactor the ELFRelocationEntry (pull up) and move the arch-specific statics to inside the class where it belongs.
...
Next step is to rationally break apart the RecordRelocation()
Probably the step will be to have 1 member function for ech slot of the ELFRelocationEntry()
llvm-svn: 119978
2010-11-22 18:41:13 +00:00
eb56dca4fd
Fix epilogue codegen to avoid leaving the stack pointer in an invalid
...
state. Previously Thumb2 would restore sp from fp like this:
mov sp, r7
sub, sp, #4
If an interrupt is taken after the 'mov' but before the 'sub', callee-saved
registers might be clobbered by the interrupt handler. Instead, try
restoring directly from sp:
add sp, #4
Or, if necessary (with VLA, etc.) use a scratch register to compute sp and
then restore it:
sub.w r4, r7, #8
mov sp, r7
rdar://8465407
llvm-svn: 119977
2010-11-22 18:12:04 +00:00
c133c54426
If a GEP index simply advances by multiples of a type of zero size,
...
then replace the index with zero.
llvm-svn: 119974
2010-11-22 16:32:50 +00:00
77d11d054c
Fix a bug with extractelement on SPU.
...
In the attached testcase, the element was
never extracted (missing rotate).
llvm-svn: 119973
2010-11-22 16:28:26 +00:00
3c227b0b89
Add basic CFI methods to the streamer interface.
...
llvm-svn: 119972
2010-11-22 14:27:24 +00:00
8a0f486e36
Move the "gep undef" -> "undef" transform from instcombine to
...
InstructionSimplify.
llvm-svn: 119970
2010-11-22 13:42:49 +00:00
556f203d64
Remove some #includes.
...
llvm-svn: 119967
2010-11-22 11:53:17 +00:00
24656c9583
Implement the "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" optimization.
...
This currently only catches the most basic case, a two-case switch, but can be
extended later.
llvm-svn: 119964
2010-11-22 09:45:38 +00:00
c6648eb4c3
Don't keep track of inserted phis in PromoteMemoryToRegister: the information
...
is never used. Patch by Cameron Zwarich.
llvm-svn: 119963
2010-11-22 09:41:24 +00:00
5cadccc4ea
Fix a compiler warning about Kind being used uninitialized
...
when assertions are disabled.
llvm-svn: 119962
2010-11-22 09:38:00 +00:00
37b0736bdc
Pseudos default to 4byte size, let the instruction size field notice
...
that branch tables are special.
llvm-svn: 119954
2010-11-21 23:38:19 +00:00
7699d6cfe9
Implement ELF object file writing support for the MBlaze backend. Its not perfect yet, but it works for many tests.
...
llvm-svn: 119952
2010-11-21 22:06:28 +00:00
f1d3800e65
Implement branch analysis in the MBlaze backend.
...
llvm-svn: 119951
2010-11-21 21:53:36 +00:00
f4efd582ad
Make it a little bit more explicit that the MBlaze backend only supports upto
...
32-bit immediate values.
llvm-svn: 119950
2010-11-21 21:39:46 +00:00
7493e30d42
Fix an error in the MBlaze delay slot filler where instructions that already
...
fill a delay slot are moved to fill a different delay slot.
llvm-svn: 119949
2010-11-21 21:36:12 +00:00
fc9aead6fd
fix comment
...
llvm-svn: 119948
2010-11-21 19:05:34 +00:00
5d2262dc76
apparently tailcalls are better on darwin/x86-64 than on linux?
...
llvm-svn: 119947
2010-11-21 18:59:20 +00:00
585dfa2b3d
Initialize MemDep's TD member so buildbots don't trip over an uninitialized pointer (TD is passed to PHITransAddr).
...
I wonder why this didn't explode earlier.
llvm-svn: 119944
2010-11-21 15:21:46 +00:00
cf4bceba49
Add a rather pointless InstructionSimplify transform, inspired by recent constant
...
folding improvements: if P points to a type of size zero, turn "gep P, N" into "P".
More generally, if a gep index type has size zero, instcombine could replace the
index with zero, but that is not done here.
llvm-svn: 119942
2010-11-21 13:53:09 +00:00
1f86be9164
Fix spelling.
...
llvm-svn: 119941
2010-11-21 12:43:13 +00:00
22db31305f
More Thumb encodings.
...
llvm-svn: 119940
2010-11-21 11:49:36 +00:00
c01d679928
Add encoding for ARM "trap" instruction.
...
llvm-svn: 119938
2010-11-21 11:05:29 +00:00
219dabdf68
The "trap" instruction is one of this which doesn't have a condition code. Hack
...
the code to not add a "condition code" if it's trap.
llvm-svn: 119937
2010-11-21 10:56:05 +00:00
3acd02706a
- Give "trap" the correct encoding, at least according to Darwin's assembler.
...
- Add comments saying where the encodings for other instructions came from.
llvm-svn: 119936
2010-11-21 10:55:23 +00:00
6ce038082b
apply Dan's fix for PR8268 which allows constant folding to handle indexes over
...
zero sized elements. This allows us to compile:
#include <string>
void foo() { std::string s; }
into an empty function.
llvm-svn: 119933
2010-11-21 08:39:01 +00:00
b4cd1819fa
implement PR8524, apparently mainline gas accepts movq as an alias for movd
...
when transfering between i64 gprs and mmx regs.
llvm-svn: 119931
2010-11-21 08:18:57 +00:00
5957229659
rework some DSE paths to use the newly-public "getPointerDependencyFrom"
...
method in MemDep instead of inserting an instruction, doing a query,
then removing it. Neither operation is effectively cached.
llvm-svn: 119930
2010-11-21 08:06:10 +00:00
663ba91cc6
add "getLocation" method to AliasAnalysis for getting the source and
...
destination location of a memcpy/memmove. I'm not clear about whether
TBAA works on these, so I'm leaving it out for now. Dan, please revisit
this when convenient.
llvm-svn: 119928
2010-11-21 07:51:27 +00:00
e48c31ce33
implement PR8576, deleting dead stores with intervening may-alias stores.
...
llvm-svn: 119927
2010-11-21 07:34:32 +00:00
9165d9d2ac
add some random notes.
...
llvm-svn: 119925
2010-11-21 07:05:31 +00:00
7e484e0be7
Use by-name rather than by-order operand matching for some NEON encodings.
...
llvm-svn: 119923
2010-11-21 06:47:06 +00:00
f7e896138e
optimize:
...
void a(int x) { if (((1<<x)&8)==0) b(); }
into "x != 3", which occurs over 100 times in 403.gcc but in no
other program in llvm-test.
llvm-svn: 119922
2010-11-21 06:44:42 +00:00
9de0176ef8
tail calls on x86 are implemented.
...
llvm-svn: 119920
2010-11-21 06:10:27 +00:00
e040a46eb3
BR_JTadd is ARM-only, so use the proper pseudo class to get the predicate.
...
llvm-svn: 119918
2010-11-21 01:26:01 +00:00
26cb15a549
Handle PCRel relocations with absolute values. Fixes PR8656.
...
llvm-svn: 119917
2010-11-21 00:48:25 +00:00
58f9f58716
Implement PR8644: forwarding a memcpy value to a byval,
...
allowing the memcpy to be eliminated.
Unfortunately, the requirements on byval's without explicit
alignment are really weak and impossible to predict in the
mid-level optimizer, so this doesn't kick in much with current
frontends. The fix is to change clang to set alignment on all
byval arguments.
llvm-svn: 119916
2010-11-21 00:28:59 +00:00
c31de25137
A few more thumb instruction MC encodings.
...
llvm-svn: 119913
2010-11-20 22:52:33 +00:00
0a3c28bd6b
Rewrite address handling to use a structure with all the possible address
...
mode variables. Handle frame indexes in load/store and allocas again.
llvm-svn: 119912
2010-11-20 22:38:27 +00:00
d0aec3bf64
STRH only needs the additional operand, not t2STRH. Also invert conditional
...
to match the one from the load emitter above.
llvm-svn: 119911
2010-11-20 22:01:38 +00:00
ddd1b7b801
Simplify code. No change in functionality.
...
llvm-svn: 119908
2010-11-20 18:43:35 +00:00
36590fc72a
Make this compile on case-sensitive file systemsw
...
llvm-svn: 119905
2010-11-20 16:14:57 +00:00
4687778398
Move some more hooks to TargetFrameInfo
...
llvm-svn: 119904
2010-11-20 15:59:32 +00:00
f6fb58a216
Silence Release build warnings about unused functions.
...
llvm-svn: 119903
2010-11-20 15:53:24 +00:00
7c601ded34
On X86, MEMBARRIER, MFENCE, SFENCE, LFENCE are not target memory intrinsics,
...
so don't claim they are. They are allocated using DAG.getNode, so attempts
to access MemSDNode fields results in reading off the end of the allocated
memory. This fixes crashes with "llc -debug" due to debug code trying to
print MemSDNode fields for these barrier nodes (since the crashes are not
deterministic, use valgrind to see this). Add some nasty checking to try
to catch this kind of thing in the future.
llvm-svn: 119901
2010-11-20 11:25:00 +00:00
cf7fefb25c
Removing the useless test that I added recently. It was meant as an example, but not complicated enough to merit another test.
...
llvm-svn: 119898
2010-11-20 07:26:51 +00:00
ada75c5ad1
RABasic fix. Regalloc is responsible for updating block live ins.
...
llvm-svn: 119896
2010-11-20 02:57:05 +00:00
799ec1c4d6
Whitespace.
...
llvm-svn: 119895
2010-11-20 02:43:55 +00:00
284326bd69
Add more Thumb add instruction encodings.
...
llvm-svn: 119883
2010-11-20 01:18:47 +00:00
fe1de03629
Add Thumb encodings for some add instructions.
...
llvm-svn: 119882
2010-11-20 01:00:29 +00:00
e60fd5a9db
Add more encodings for Thumb instructions.
...
llvm-svn: 119881
2010-11-20 00:53:35 +00:00
0914d44fa4
Have the getAddrMode3OpValue() function in ARMCodeEmitter.cpp produce the same
...
value that the one in ARMMCCodeEmitter.cpp does.
llvm-svn: 119878
2010-11-20 00:26:37 +00:00
54df187f25
Check for _setjmp too, because it's also used.
...
llvm-svn: 119875
2010-11-20 00:03:09 +00:00
2aff392af9
Fix ARM LDR* post-indexed operand encoding.
...
llvm-svn: 119869
2010-11-19 23:14:43 +00:00
1825cc74f4
Encodings for the compare instructions.
...
llvm-svn: 119868
2010-11-19 23:14:32 +00:00
b4fd2c90e9
The Vm and Vn register fields must be the same for a register-register vmov.
...
llvm-svn: 119867
2010-11-19 23:12:43 +00:00
a5f048485f
Fix a cut-n-paste-error.
...
llvm-svn: 119866
2010-11-19 23:01:16 +00:00
ea326db47b
Document the new GVN number table structure.
...
llvm-svn: 119865
2010-11-19 22:48:40 +00:00
785952e5ac
Operand names
...
llvm-svn: 119864
2010-11-19 22:43:08 +00:00
5876e41c9f
trailing whitespace
...
llvm-svn: 119863
2010-11-19 22:42:55 +00:00
35e2d7f610
Don't need to save piecemeal now.
...
llvm-svn: 119862
2010-11-19 22:39:56 +00:00
cee83d6e6b
Update comment.
...
llvm-svn: 119861
2010-11-19 22:37:58 +00:00
a82fb71324
Add encodings for some of the thumb ADD instructions. Tests will come once the
...
asm parser can handle them.
llvm-svn: 119860
2010-11-19 22:37:33 +00:00
558b61e2d4
Update comment.
...
llvm-svn: 119859
2010-11-19 22:36:41 +00:00
7d8df3185f
Clarify operand names.
...
llvm-svn: 119858
2010-11-19 22:36:02 +00:00
fef5f315af
Refactor address mode handling into a single struct (ala x86), this
...
should give allow a wider range of addressing modes.
No functional change.
llvm-svn: 119856
2010-11-19 22:30:02 +00:00
48bf4f8e56
Fix encoding for ARM MLS instruction.
...
llvm-svn: 119855
2010-11-19 22:22:37 +00:00
dfb8c3bbfc
When folding addressing modes in CodeGenPrepare, attempt to look through PHI nodes
...
if all the operands of the PHI are equivalent. This allows CodeGenPrepare to undo
unprofitable PRE transforms.
llvm-svn: 119853
2010-11-19 22:15:03 +00:00
09d7bfd886
Add ARM encoding information for STRD.
...
llvm-svn: 119852
2010-11-19 22:14:31 +00:00
5a77b8b5c4
Shuffle things around a bit to keep like things together. Tidy up formatting.
...
llvm-svn: 119851
2010-11-19 22:06:57 +00:00
c92a5770df
Revert accidental commit.
...
llvm-svn: 119850
2010-11-19 22:06:18 +00:00
49a2e2384b
Change long binary encodings to use hex instead. It's more readable. Also
...
initialize missing bit.
llvm-svn: 119849
2010-11-19 22:02:18 +00:00
6e9aace4f3
Factor out operand encoding bits for ARM addressing mode 2 store instructions.
...
llvm-svn: 119846
2010-11-19 21:35:06 +00:00
09f6823eb6
Delete another dead class.
...
llvm-svn: 119844
2010-11-19 21:16:08 +00:00
e093e5f0dc
whitespace tweak.
...
llvm-svn: 119843
2010-11-19 21:14:37 +00:00
cf14a382ec
Fix a use after free. Patch by Frits van Bommel.
...
llvm-svn: 119842
2010-11-19 21:14:29 +00:00
d6e5c9f2fe
Refactor PICSTR* instructions to really be pseudos. Nuke dead classes.
...
llvm-svn: 119841
2010-11-19 21:14:02 +00:00
4a22eba616
Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes.
...
llvm-svn: 119840
2010-11-19 21:07:51 +00:00
003c6e700b
Add ARM binary encoding information for the rest of the indexed loads.
...
llvm-svn: 119821
2010-11-19 19:41:26 +00:00
88ff56caa3
Make isScalarToVector to return false if the node is a scalar. This will prevent
...
DAGCombine from making an illegal transformation of bitcast of a scalar to a
vector into a scalar_to_vector.
llvm-svn: 119819
2010-11-19 19:08:12 +00:00
8be14414f6
Added support for the Mach-O .symbol_resolver directive. rdar://8673046
...
llvm-svn: 119816
2010-11-19 18:39:33 +00:00
c6ac246671
Remove dead code.
...
llvm-svn: 119815
2010-11-19 18:18:37 +00:00
76aed40813
ARM LDRD binary encoding.
...
llvm-svn: 119812
2010-11-19 18:16:46 +00:00
d7a3550a5e
Remove hard tabs.
...
llvm-svn: 119810
2010-11-19 18:01:37 +00:00
2bb49e15a6
Remove trailing whitespace.
...
llvm-svn: 119806
2010-11-19 17:11:02 +00:00
2e49eaa92f
Avoid release build warnings.
...
llvm-svn: 119804
2010-11-19 16:36:02 +00:00
336021f758
Fix decoding ambiguities of stdrex and ldrex.
...
llvm-svn: 119801
2010-11-19 13:11:50 +00:00
c77ebcc9a5
Silence warning about an uninitialized variable.
...
llvm-svn: 119800
2010-11-19 11:37:26 +00:00
b238de0415
Remove threading of Xor over selects and phis, with an explanation
...
of why such threading is pointless.
llvm-svn: 119798
2010-11-19 09:20:39 +00:00
9900b4802e
Add a MCLineSectionOrder vector so that we produce the line tables in a
...
deterministic order.
llvm-svn: 119795
2010-11-19 07:41:23 +00:00
2debc86138
These instructions are thumb2 only.
...
llvm-svn: 119793
2010-11-19 06:28:11 +00:00
0eb2994626
Fix an obvious oversight.
...
llvm-svn: 119792
2010-11-19 06:15:10 +00:00
4031c5eb48
Don't attempt trivial coalescing for sub-register copies.
...
Patch by Krister Wombell!
llvm-svn: 119791
2010-11-19 05:45:24 +00:00
0b4c9aa9a9
Add an assert.
...
llvm-svn: 119788
2010-11-19 04:55:36 +00:00
345945e355
Add ADT/IntervalMap.
...
This is a sorted interval map data structure for small keys and values with
automatic coalescing and bidirectional iteration over coalesced intervals.
Except for coalescing intervals, it provides similar functionality to std::map.
It is however much more compact for small keys and values, and hopefully faster
too.
The container object itself can hold the first few intervals without any
allocations, then it switches to a cache conscious B+-tree representation. A
recycling allocator can be shared between many containers, even between
containers holding different types.
The IntervalMap is initially intended to be used with SlotIndex intervals for:
- Backing store for LiveIntervalUnion that is smaller and faster than std::set.
- Backing store for LiveInterval with less overhead than std::vector for typical
intervals and O(N log N) merging of large intervals. 99% of virtual registers
need 4 entries or less and would benefit from the small object optimization.
- Backing store for LiveDebugVariable which doesn't exist yet, but will track
debug variables during register allocation.
This is a work in progress. Missing items are:
- Performance metrics.
- erase().
- insert() shrinkage.
- clear().
- More performance metrics.
- Simplification and detemplatization.
llvm-svn: 119787
2010-11-19 04:47:19 +00:00
92ca933f6e
Fix llvm-gcc boostrap on OS X by avoiding printing sleb and uleb when
...
possible.
llvm-svn: 119785
2010-11-19 04:10:13 +00:00
b58867ccba
Change some methods in MCDwarf.cpp to be able to handle an arbitrary
...
MCStreamer instead of just MCObjectStreamer. Address changes cannot
be as efficient as we have to use DW_LNE_set_addres, but at least
most of the logic is shared.
This will be used so that, with CodeGen still using EmitDwarfLocDirective,
llvm-gcc is able to produce debug_line sections without needing an
assembler that supports .loc.
llvm-svn: 119777
2010-11-19 02:26:16 +00:00
945b776b6e
Add MC encodings for some Thumb instructions. Test for a few of them. The "bx
...
lr" instruction cannot be tested just yet. It requires matching a "condition
code", but adding one of those makes things go south quickly...
llvm-svn: 119774
2010-11-19 01:33:10 +00:00
09770251f6
Revert "Add ADT/IntervalMap.", GCC doesn't like it.
...
This reverts r119772.
llvm-svn: 119773
2010-11-19 01:21:03 +00:00
6d89171dcc
Add ADT/IntervalMap.
...
This is a sorted interval map data structure for small keys and values with
automatic coalescing and bidirectional iteration over coalesced intervals.
Except for coalescing intervals, it provides similar functionality to std::map.
It is however much more compact for small keys and values, and hopefully faster
too.
The container object itself can hold the first few intervals without any
allocations, then it switches to a cache conscious B+-tree representation. A
recycling allocator can be shared between many containers, even between
containers holding different types.
The IntervalMap is initially intended to be used with SlotIndex intervals for:
- Backing store for LiveIntervalUnion that is smaller and faster than std::set.
- Backing store for LiveInterval with less overhead than std::vector for typical
intervals and O(N log N) merging of large intervals. 99% of virtual registers
need 4 entries or less and would benefit from the small object optimization.
- Backing store for LiveDebugVariable which doesn't exist yet, but will track
debug variables during register allocation.
This is a work in progress. Missing items are:
- Performance metrics.
- erase().
- insert() shrinkage.
- clear().
- More performance metrics.
- Simplification and detemplatization.
llvm-svn: 119772
2010-11-19 01:14:40 +00:00
461e704a2c
Aligned and unaligned copies of the same string
...
were not hashing to the same value. Analysis
and patch by Frits van Bommel!
llvm-svn: 119770
2010-11-19 00:48:58 +00:00
20b5ea9858
Use array_pod_sort because the list is contiguous.
...
llvm-svn: 119769
2010-11-19 00:38:19 +00:00
f53e4d9fd1
Provide Thumb2 encodings for strex and ldrex.
...
llvm-svn: 119768
2010-11-19 00:28:38 +00:00
2aeb8b9361
Minor cleanups to a few llvm_unreachable() calls.
...
llvm-svn: 119767
2010-11-19 00:27:09 +00:00
2ecfcbd2aa
An 'unreachable' shouldn't have a '0 &&' prefix.
...
llvm-svn: 119762
2010-11-19 00:05:15 +00:00
2063b84297
Add support for parsing the writeback ("!") token.
...
llvm-svn: 119761
2010-11-18 23:43:05 +00:00
5a97bd873e
Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM.
...
Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.
llvm-svn: 119760
2010-11-18 23:37:15 +00:00
3517585249
Fix encodings for pkhbt, and fix some tests where I accidentally tested ARM mode instead of Thumb2.
...
llvm-svn: 119755
2010-11-18 23:29:56 +00:00
14ee344944
Move getInitialFrameState() to TargetFrameInfo
...
llvm-svn: 119754
2010-11-18 23:25:52 +00:00
a391c97bd0
ARM Encoding information for UXTAH and friends.
...
llvm-svn: 119753
2010-11-18 23:24:22 +00:00
cd68095650
Fix bug in DAGCombiner for ARM that was trying to do a ShiftCombine on illegal types (vector should be split first).
...
Added test case.
llvm-svn: 119749
2010-11-18 22:06:46 +00:00
0ab0f67925
Don't allocate the SmallVector of Registers. It gets messy figuring out who
...
should delete what when the object gets copied around. It's also making valgrind
upset.
llvm-svn: 119747
2010-11-18 21:50:54 +00:00
10839cb62c
Provide Thumb2 encodings for mov's that come from MOVCC SDNodes.
...
llvm-svn: 119744
2010-11-18 21:46:31 +00:00
1b91ae18ed
Add ARM encoding information for LDRH post-increment.
...
llvm-svn: 119743
2010-11-18 21:43:37 +00:00
0eecf5d201
Move hasFP() and few related hooks to TargetFrameInfo.
...
llvm-svn: 119740
2010-11-18 21:19:35 +00:00
c92331b984
Fix thinko: we must turn select(anyext, sext) into sext(select)
...
not anyext(select). Spotted by Frits van Bommel.
llvm-svn: 119739
2010-11-18 21:16:28 +00:00
7d47133ff7
Split up ARM LowerShift function.
...
This function was being called from two different places for completely
unrelated reasons. During type legalization, it was called to expand 64-bit
shift operations. During operation legalization, it was called to handle
Neon vector shifts. The vector shift code was not written to check for
illegal types, since it was assumed to be only called after type legalization.
Fixed this by splitting off the 64-bit shift expansion into a separate
function. I don't have a particular testcase for this; I just noticed it
by inspection.
llvm-svn: 119738
2010-11-18 21:16:28 +00:00
3fec5ff14b
More Thumb2 encodings.
...
llvm-svn: 119737
2010-11-18 21:15:19 +00:00
3625098459
Fill out the set of Thumb2 multiplication operator encodings.
...
llvm-svn: 119733
2010-11-18 20:32:18 +00:00
12f3b3b44f
The DAGCombiner was threading select over pairs of extending loads even
...
if the extension types were not the same. The result was that if you
fed a select with sext and zext loads, as in the testcase, then it
would get turned into a zext (or sext) of the select, which is wrong
in the cases when it should have been an sext (resp. zext). Reported
and diagnosed by Sebastien Deldon.
llvm-svn: 119728
2010-11-18 20:05:18 +00:00
aef146b890
Factor code for testing whether replacing one value with another
...
preserves LCSSA form out of ScalarEvolution and into the LoopInfo
class. Use it to check that SimplifyInstruction simplifications
are not breaking LCSSA form. Fixes PR8622.
llvm-svn: 119727
2010-11-18 19:59:41 +00:00
b9bd594610
Missed the _RET versions of LDMIA.
...
llvm-svn: 119726
2010-11-18 19:44:29 +00:00
b006fc9c07
Rewrite stack callee saved spills and restores to use push/pop instructions.
...
Remove movePastCSLoadStoreOps and associated code for simple pointer
increments. Update routines that depended upon other opcodes for save/restore.
Adjust all testcases accordingly.
llvm-svn: 119725
2010-11-18 19:40:05 +00:00
2e831897d6
Fix an order-of-deallocation issue where the AttrListImpl could be deallocated before the global
...
LLVMContext, causing memory errors. Patch by Peter Collingbourne.
llvm-svn: 119721
2010-11-18 18:59:13 +00:00
aa398c1617
Use thread-safe statics to avoid a static constructor here. This isn't thread-safe on MSVC, but we don't
...
support threaded LLVM there anyways.
llvm-svn: 119718
2010-11-18 18:49:05 +00:00
e4f7ec17f8
Oops, missed this file when remaing ExpandPseudos to ExpandISelPseudos.
...
llvm-svn: 119717
2010-11-18 18:48:28 +00:00
c2b786163c
Rename ExpandPseudos to ExpandISelPseudos to help clarify its role.
...
llvm-svn: 119716
2010-11-18 18:45:06 +00:00
c21c100f3d
Completely rework the datastructure GVN uses to represent the value number to leader mapping. Previously,
...
this was a tree of hashtables, and a query recursed into the table for the immediate dominator ad infinitum
if the initial lookup failed. This led to really bad performance on tall, narrow CFGs.
We can instead replace it with what is conceptually a multimap of value numbers to leaders (actually
represented by a hashtable with a list of Value*'s as the value type), and then
determine which leader from that set to use very cheaply thanks to the DFS numberings maintained by
DominatorTree. Because there are typically few duplicates of a given value, this scan tends to be
quite fast. Additionally, we use a custom linked list and BumpPtr allocation to avoid any unnecessary
allocation in representing the value-side of the multimap.
This change brings with it a 15% (!) improvement in the total running time of GVN on 403.gcc, which I
think is pretty good considering that includes all the "real work" being done by MemDep as well.
The one downside to this approach is that we can no longer use GVN to perform simple conditional progation,
but that seems like an acceptable loss since we now have LVI and CorrelatedValuePropagation to pick up
the slack. If you see conditional propagation that's not happening, please file bugs against LVI or CVP.
llvm-svn: 119714
2010-11-18 18:32:40 +00:00
51fdc47a11
ARMPseudoInst instructions should default to being considered a single 4-byte
...
instruction. Any that may be expanded otherwise by MC lowering should
override this value. rdar://8683274
llvm-svn: 119713
2010-11-18 18:01:40 +00:00
5a1a2d53de
Fix typos.
...
llvm-svn: 119712
2010-11-18 17:44:17 +00:00
5ed61fe6a1
Bounds-check APInt's operator[].
...
llvm-svn: 119708
2010-11-18 17:14:56 +00:00
21a9683641
ExpandPseudos doesn't have any dependencies, so it can use the
...
simple form of INITIALIZE_PASS.
llvm-svn: 119707
2010-11-18 17:14:05 +00:00
f1ebfc1544
Strip trailing whitespace.
...
llvm-svn: 119706
2010-11-18 17:06:31 +00:00
0ab28b62b1
Use llvm_unreachable for "impossible" situations.
...
llvm-svn: 119705
2010-11-18 17:05:57 +00:00
2e1fc849b2
Add support for PHI-translating sext, zext, and trunc instructions,
...
enabling more PRE. PR8586.
llvm-svn: 119704
2010-11-18 17:05:13 +00:00
1385dff8c0
slightly simplify code and substantially improve comment. Instead of
...
saying "it would be bad", give an example of what is going on.
llvm-svn: 119695
2010-11-18 08:07:09 +00:00
731caac7c6
remove a pointless restriction from memcpyopt. It was
...
refusing to optimize two memcpy's like this:
copy A <- B
copy C <- A
if it couldn't prove that noalias(B,C). We can eliminate
the copy by producing a memmove instead of memcpy.
llvm-svn: 119694
2010-11-18 08:00:57 +00:00
c274a83442
remove another pointless noalias check: M is a memcpy, so the
...
source and dest are known to not overlap.
llvm-svn: 119692
2010-11-18 07:39:57 +00:00
75cfe98534
use AA::isNoAlias instead of open coding it. Remove an extraneous noalias check:
...
there is no need to check to see if the source and dest of a memcpy are noalias,
behavior is undefined if not.
llvm-svn: 119691
2010-11-18 07:38:43 +00:00
1e37bbafbb
finish a thought.
...
llvm-svn: 119690
2010-11-18 07:32:33 +00:00
7e9b2ea3bf
rearrange some code, splitting memcpy/memcpy optimization
...
out of processMemCpy into its own function.
llvm-svn: 119687
2010-11-18 07:02:37 +00:00
ac5701319b
allow eliminating an alloca that is just copied from an constant global
...
if it is passed as a byval argument. The byval argument will just be a
read, so it is safe to read from the original global instead. This allows
us to promote away the %agg.tmp alloca in PR8582
llvm-svn: 119686
2010-11-18 06:41:51 +00:00
f183d5c4be
enhance the "alloca is just a memcpy from constant global"
...
to ignore calls that obviously can't modify the alloca
because they are readonly/readnone.
llvm-svn: 119683
2010-11-18 06:26:49 +00:00
7aeae25c78
fix a small oversight in the "eliminate memcpy from constant global"
...
optimization. If the alloca that is "memcpy'd from constant" also has
a memcpy from *it*, ignore it: it is a load. We now optimize the testcase to:
define void @test2() {
%B = alloca %T
%a = bitcast %T* @G to i8*
%b = bitcast %T* %B to i8*
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %b, i8* %a, i64 124, i32 4, i1 false)
call void @bar(i8* %b)
ret void
}
previously we would generate:
define void @test() {
%B = alloca %T
%b = bitcast %T* %B to i8*
%G.0 = getelementptr inbounds %T* @G, i32 0, i32 0
%tmp3 = load i8* %G.0, align 4
%G.1 = getelementptr inbounds %T* @G, i32 0, i32 1
%G.15 = bitcast [123 x i8]* %G.1 to i8*
%1 = bitcast [123 x i8]* %G.1 to i984*
%srcval = load i984* %1, align 1
%B.0 = getelementptr inbounds %T* %B, i32 0, i32 0
store i8 %tmp3, i8* %B.0, align 4
%B.1 = getelementptr inbounds %T* %B, i32 0, i32 1
%B.12 = bitcast [123 x i8]* %B.1 to i8*
%2 = bitcast [123 x i8]* %B.1 to i984*
store i984 %srcval, i984* %2, align 1
call void @bar(i8* %b)
ret void
}
llvm-svn: 119682
2010-11-18 06:20:47 +00:00
dca25f69ca
trivial QoI improvement. On this invalid input:
...
sahf movl 344(%rdi),%r14d
we used to produce:
t.s:2:1: error: unexpected token in argument list
^
we now produce:
t.s:1:11: error: unexpected token in argument list
sahf movl 344(%rdi),%r14d
^
rdar://8581401
llvm-svn: 119676
2010-11-18 02:53:02 +00:00
67c6ab8865
Change CodeGen to use .loc directives. This produces a lot more readable output
...
and testing is easier. A good example is the unknown-location.ll test that
now can just look for ".loc 1 0 0". We also don't use a DW_LNE_set_address for
every address change anymore.
llvm-svn: 119613
2010-11-18 02:04:25 +00:00
2d4e42fba6
Silence compiler warnings.
...
llvm-svn: 119610
2010-11-18 01:43:23 +00:00
9c335bf977
Remove trailing whitespace.
...
llvm-svn: 119608
2010-11-18 01:39:50 +00:00
a74c7ccd59
ARM PseudoInst instructions don't need or use an assembler string. Get rid of
...
the operand to the pattern.
llvm-svn: 119607
2010-11-18 01:38:26 +00:00
ed0d840838
Do not throw away alignment when generating the DAG for
...
memset; we may need it to decide between MOVAPS and MOVUPS
later. Adjust a test that was looking for wrong code.
PR 3866 / 8675131.
llvm-svn: 119605
2010-11-18 01:35:23 +00:00
a2f30cc121
Code clean up.
...
llvm-svn: 119604
2010-11-18 01:28:51 +00:00
19be1fbca1
Add FIXME.
...
llvm-svn: 119603
2010-11-18 01:20:48 +00:00
cfb66204b7
Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not
...
just pretend to be.
llvm-svn: 119602
2010-11-18 01:15:56 +00:00
d127e7174b
Try again at providing Thumb2 encodings for basic multiplication operators.
...
llvm-svn: 119601
2010-11-18 01:08:42 +00:00
8e7f8df4a2
Refactor a few ARM load instructions to better parameterize things and re-use
...
common encoding information.
llvm-svn: 119598
2010-11-18 00:46:58 +00:00
28883834e1
Revert r119593 while I figure out my testing disagrees with the buildbot.
...
llvm-svn: 119597
2010-11-18 00:42:51 +00:00
8ea83d81e0
Introduce memoization for ScalarEvolution dominates and properlyDominates
...
queries, and SCEVExpander getRelevantLoop queries.
llvm-svn: 119595
2010-11-18 00:34:22 +00:00
64aaddcd64
Provide correct Thumb2 encodings for basic multiplication operators.
...
llvm-svn: 119593
2010-11-18 00:19:10 +00:00
ddc7ce548c
Bug 8621 fix - pointer cast stripped from inline asm constraint argument.
...
llvm-svn: 119590
2010-11-17 23:58:47 +00:00
56f471726c
Clean up LEApcrel instuction(s) a bit. It's not really a Pseudo, so don't mark
...
it as such. Add some encoding information.
llvm-svn: 119588
2010-11-17 23:33:14 +00:00
7e6b393e66
Factor out the code for purging a SCEV from all the various memoization maps.
...
Some of these maps may merge in the future, but for now it's convenient to have
a utility function for them.
llvm-svn: 119587
2010-11-17 23:28:48 +00:00
7ee1bbb76c
Merge the implementations of isLoopInvariant and hasComputableLoopEvolution, and
...
memoize the results. This improves compile time in code which highly complex
expressions which get queried many times.
llvm-svn: 119584
2010-11-17 23:21:44 +00:00
534749bf70
Make SCEV::getType() and SCEV::print non-virtual. Move SCEV::hasOperand
...
to ScalarEvolution. Delete SCEV::~SCEV. SCEV is no longer virtual.
llvm-svn: 119578
2010-11-17 22:27:42 +00:00
55425e7f78
Second attempt at correct encodings for Thumb2 bitfield instructions.
...
llvm-svn: 119575
2010-11-17 22:16:31 +00:00
4ded8f264a
Fix comment typo.
...
llvm-svn: 119573
2010-11-17 21:57:51 +00:00
20d9ce21ef
Move SCEV::dominates and properlyDominates to ScalarEvolution.
...
llvm-svn: 119570
2010-11-17 21:41:58 +00:00
881b45ccdf
Change ARMGlobalMerge to keep BSS globals in separate pools.
...
This completes the fixes for Radar 8673120.
llvm-svn: 119566
2010-11-17 21:25:39 +00:00
4c8ab19c22
Fix ARMGlobalMerge pass to check if globals are entirely within range.
...
It is generally not sufficient to check if the starting offset is in range
of the maximum offset that can be efficiently used for the target.
llvm-svn: 119565
2010-11-17 21:25:36 +00:00
59182fb4b5
Change the symbol for merged globals from "merged" to "_MergedGlobals".
...
This makes it more clear that the symbol is an internal, compiler-generated
name and gives a little more description about its contents.
llvm-svn: 119564
2010-11-17 21:25:33 +00:00
f796d4b469
Fix the ARMGlobalMerge pass to look at variable sizes instead of pointer sizes.
...
It was mistakenly looking at the pointer type when checking for the size of
global variables. This is a partial fix for Radar 8673120.
llvm-svn: 119563
2010-11-17 21:25:27 +00:00
afd6db9932
Move SCEV::isLoopInvariant and hasComputableLoopEvolution to be member
...
functions of ScalarEvolution, in preparation for memoization and
other optimizations.
llvm-svn: 119562
2010-11-17 21:23:15 +00:00
08c562bba6
Make the ARM BR_JTadd instruction an explicit pseudo and lower it properly
...
in the MC lowering process.
llvm-svn: 119559
2010-11-17 21:05:55 +00:00
39c81c0a55
Avoid isel movcc of large immediates when the large immediate is available in a register. These immediates aren't free.
...
llvm-svn: 119558
2010-11-17 20:56:30 +00:00
1ee6d24072
Reference ScalarEvolution by name rather than directly in LICM,
...
to avoid an unneeded dependence.
llvm-svn: 119557
2010-11-17 20:50:07 +00:00
39d77131a1
Before replacing a phi node with a different value, it
...
needs to be checked that this won't break LCSSA form.
Change the existing checking method to a more direct one:
rather than seeing if all predecessors belong to the loop,
check that the replacing value is either not in any loop or
is in a loop that contains the phi node.
llvm-svn: 119556
2010-11-17 20:49:12 +00:00
6c37ceb182
Revert r119551, which broke buildbots.
...
llvm-svn: 119555
2010-11-17 20:48:51 +00:00
d3a32ae4c8
Verify SCEVAddRecExpr's invariant in ScalarEvolution::getAddRecExpr
...
instead of in SCEVAddRecExpr's constructor, in preparation for an
upcoming change.
llvm-svn: 119554
2010-11-17 20:48:38 +00:00
7464116bde
Provide Thumb2 encodings for bitfield instructions.
...
llvm-svn: 119551
2010-11-17 20:35:29 +00:00
ed75631743
Fix ScalarEvolution's range memoization to avoid using a
...
default ctor with ConstantRange.
llvm-svn: 119550
2010-11-17 20:23:08 +00:00
7f8ab6ee8b
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
...
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.
Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.
Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.
2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.
rdar://8663787, rdar://8241368
llvm-svn: 119548
2010-11-17 20:13:28 +00:00
7a2cd8b540
make isVirtualSection a virtual method on MCSection. Chris' suggestion.
...
llvm-svn: 119547
2010-11-17 20:03:54 +00:00
bced7ae046
More miscellaneous Thumb2 encodings.
...
llvm-svn: 119546
2010-11-17 19:57:38 +00:00
d82684c7fc
Fix typo.
...
llvm-svn: 119542
2010-11-17 19:30:11 +00:00
11cc1761dd
Add missing opcodes now that this function's used in more than one place.
...
llvm-svn: 119539
2010-11-17 19:16:20 +00:00
07726c7d52
InstCombine: Add a missing irem identity (X % X -> 0).
...
llvm-svn: 119538
2010-11-17 19:11:46 +00:00
c89ac07e7a
Move some those Xor simplifications which don't require creating new
...
instructions out of InstCombine and into InstructionSimplify. While
there, introduce an m_AllOnes pattern to simplify matching with integers
and vectors with all bits equal to one.
llvm-svn: 119536
2010-11-17 18:52:15 +00:00
8839775df6
More ARM encoding bits. LDRH now encodes properly.
...
llvm-svn: 119529
2010-11-17 18:11:11 +00:00
b67912d5cd
Add support for .int.
...
llvm-svn: 119512
2010-11-17 16:24:40 +00:00
5c996894bd
Add support for .2byte, .4byte and .8byte.
...
Fixes PR8631.
llvm-svn: 119511
2010-11-17 16:15:42 +00:00
95d37be1a9
MC-JIT: Stub out "pure" streamer.
...
- No immediate use, but maybe someone feels like hacking on it.
llvm-svn: 119510
2010-11-17 16:06:47 +00:00
7e5d8a765f
MCJIT: Stub out MCJIT implementation, still doesn't do anything useful.
...
llvm-svn: 119509
2010-11-17 16:06:43 +00:00
70ff8b05e3
lli: Add stub -use-mcjit option, which doesn't currently do anything.
...
llvm-svn: 119508
2010-11-17 16:06:37 +00:00
9d9a4e2ca2
Have InlineFunction use SimplifyInstruction rather than
...
hasConstantValue. I was leery of using SimplifyInstruction
while the IR was still in a half-baked state, which is the
reason for delaying the simplification until the IR is fully
cooked.
llvm-svn: 119494
2010-11-17 11:16:23 +00:00
ec7a6ecb92
Now that hasConstantValue has been made simpler, it may return the
...
phi node itself if it occurs in an unreachable basic block. Protect
against this. Hopefully this will fix some more buildbots.
llvm-svn: 119493
2010-11-17 10:23:23 +00:00
7c91bb855f
Revert r119109 for now. It's breaking 176.gcc.
...
llvm-svn: 119492
2010-11-17 09:31:04 +00:00
64e41cf865
Previously SimplifyInstruction could report that an instruction
...
simplified to itself (this can only happen in unreachable blocks).
Change it to return null instead. Hopefully this will fix some
buildbot failures.
llvm-svn: 119490
2010-11-17 08:35:29 +00:00
79ffdc7581
With the newly simplified SourceMgr interfaces and the generalized
...
SrcMgrDiagHandler, we can improve clang diagnostics for inline asm:
instead of reporting them on a source line of the original line,
we can report it on the correct line wherever the string literal came
from. For something like this:
void foo() {
asm("push %rax\n"
".code32\n");
}
we used to get this: (note that the line in t.c isn't helpful)
t.c:4:7: error: warning: ignoring directive for now
asm("push %rax\n"
^
<inline asm>:2:1: note: instantiated into assembly here
.code32
^
now we get:
t.c:5:8: error: warning: ignoring directive for now
".code32\n"
^
<inline asm>:2:1: note: instantiated into assembly here
.code32
^
Note that we're pointing to line 5 properly now.
llvm-svn: 119488
2010-11-17 08:20:42 +00:00
b0e36085c4
now that AsmPrinter::EmitInlineAsm is factored right, we can eliminate the
...
cookie argument to the SourceMgr diagnostic stuff. This cleanly separates
LLVMContext's inlineasm handler from the sourcemgr error handling
definition, increasing type safety and cleaning things up.
llvm-svn: 119486
2010-11-17 08:13:01 +00:00
c03d04ee1f
Add simple arithmetics and %type directive for PTX
...
llvm-svn: 119485
2010-11-17 08:08:49 +00:00
655364797e
Simplify code that toggle optional operand to ARM::CPSR.
...
llvm-svn: 119484
2010-11-17 08:06:50 +00:00
300fa45d8b
rearrange how the handler in SourceMgr is installed, eliminating the use of
...
the cookie argument to setDiagHandler
llvm-svn: 119483
2010-11-17 08:03:32 +00:00
2a7f6fd9d4
refactor the interface to EmitInlineAsm a bit, no functionality change.
...
llvm-svn: 119482
2010-11-17 07:53:40 +00:00
baf00151ba
fix PR8613 - Copy constructor of SwitchInst does not call SwitchInst::init
...
llvm-svn: 119463
2010-11-17 05:41:46 +00:00
9fdd10dbce
tidy up
...
llvm-svn: 119462
2010-11-17 05:41:32 +00:00
b100f91754
The machine instruction no longer encodes the submode as a separate operand. We
...
should get the submode from the load/store multiple instruction's opcode.
llvm-svn: 119461
2010-11-17 05:31:09 +00:00
9898ac97fd
Proper encoding for VLDM and VSTM instructions. The register lists for these
...
instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.
llvm-svn: 119460
2010-11-17 04:32:08 +00:00
7412f6e53d
Fix a layering violation: hasConstantValue, which is part of the PHINode
...
class, uses DominatorTree which is an analysis. This change moves all of
the tricky hasConstantValue logic to SimplifyInstruction, and replaces it
with a very simple literal implementation. I already taught users of
hasConstantValue that need tricky stuff to use SimplifyInstruction instead.
I didn't update InlineFunction because the IR looks like it might be in a
funky state at the point it calls hasConstantValue, which makes calling
SimplifyInstruction dangerous since it can in theory do a lot of tricky
reasoning. This may be a pessimization, for example in the case where
all phi node operands are either undef or a fixed constant.
llvm-svn: 119459
2010-11-17 04:30:22 +00:00
d06f50e2db
Have ScalarEvolution use SimplifyInstruction rather than hasConstantValue.
...
While there, add a note about an inefficiency I noticed.
llvm-svn: 119458
2010-11-17 04:18:45 +00:00
ba0b22c785
Have RemovePredecessorAndSimplify you SimplifyInstruction
...
rather than hasConstantValue.
llvm-svn: 119457
2010-11-17 04:12:05 +00:00
72313843d5
Remove dead code in GVN: now that SimplifyInstruction is called
...
systematically, CollapsePhi will always return null here. Note
that CollapsePhi did an extra check, isSafeReplacement, which
the SimplifyInstruction logic does not do. I think that check
was bogus - I guess we will soon find out! (It was originally
added in commit 41998 without a testcase).
llvm-svn: 119456
2010-11-17 04:05:21 +00:00
761065e3b7
Memoize results from ScalarEvolution's getUnsignedRange and getSignedRange.
...
This fixes some extreme compile times on unrolled sha512 code.
llvm-svn: 119455
2010-11-17 02:44:44 +00:00
bcc230a765
Only avoid the check if we're the last operand before the variable
...
operands in a variadic instruction.
llvm-svn: 119446
2010-11-17 00:55:36 +00:00
345b48fcbd
Add binary emission stuff for VLDM/VSTM. This reuses the
...
"getRegisterListOpValue" logic. If the registers are double or single precision,
the value returned is suitable for VLDM/VSTM.
llvm-svn: 119435
2010-11-17 00:45:23 +00:00
ee5ba319db
Fix typo: Exectuable -> Executable
...
llvm-svn: 119433
2010-11-17 00:43:43 +00:00
a8974af320
Use the correct variable names so that the encodings will be correct.
...
llvm-svn: 119403
2010-11-16 23:44:49 +00:00
aeb5e66772
Reapply r118917. With pseudo-instruction expansion moved to
...
a different pass, the complicated interaction between cmov expansion
and fast isel is no longer a concern.
llvm-svn: 119400
2010-11-16 22:43:23 +00:00
4e61b09a89
Fix assembling X86CompilationCallback_Win64.asm on VS 10.
...
Patch by Louis Zhuang!
llvm-svn: 119394
2010-11-16 22:07:47 +00:00
6397420a30
Fix grammaro.
...
llvm-svn: 119386
2010-11-16 21:27:00 +00:00
3e2ec64367
Add ExpandPseudos.cpp.
...
llvm-svn: 119385
2010-11-16 21:20:36 +00:00
c653a895c8
Add .loc methods to the streamer.
...
Next: Add support for the !HasDotLocAndDotFile case to the MCAsmStreamer
and then switch codegen to use it.
llvm-svn: 119384
2010-11-16 21:20:32 +00:00
8b67c720f2
Split pseudo-instruction expansion into a separate pass, to make it
...
easier to debug, and to avoid complications when the CFG changes
in the middle of the instruction selection process.
llvm-svn: 119382
2010-11-16 21:02:37 +00:00
9beef41f2c
Fix emergency spilling in LiveIntervals::spillPhysRegAroundRegDefsUses.
...
Always spill the full representative register at any point where any subregister
is live.
This fixes PR8620 which caused the old logic to get confused and not spill
anything at all.
The fundamental problem here is that the coalescer is too aggressive about
physical register coalescing. It sometimes makes it impossible to allocate
registers without these emergency spills.
llvm-svn: 119375
2010-11-16 19:55:14 +00:00
7583f68954
Print out the register class of the current interval.
...
llvm-svn: 119374
2010-11-16 19:55:12 +00:00
3bbea57a6e
Parse and ignore some .cfi_* directives.
...
llvm-svn: 119362
2010-11-16 18:34:07 +00:00
5ed2428b3c
This is the first step in adding sane error handling support to LLVMSystem.
...
The system API's will be shifted over to returning an error_code, and returning
other return values as out parameters to the function.
Code that needs to check error conditions will use the errc enum values which
are the same as the posix_errno defines (EBADF, E2BIG, etc...), and are
compatable with the error codes in WinError.h due to some magic in system_error.
An example would be:
if (error_code ec = KillEvil("Java")) { // error_code can be converted to bool.
handle_error(ec);
}
llvm-svn: 119360
2010-11-16 18:31:52 +00:00
e600aba989
ARM conditional mov encoding fix.
...
llvm-svn: 119354
2010-11-16 18:13:42 +00:00
637049515f
Have a few places that want to simplify phi nodes use SimplifyInstruction
...
rather than calling hasConstantValue. No intended functionality change.
llvm-svn: 119352
2010-11-16 17:41:24 +00:00
5ffc298bc7
In which I discover the existence of loops. Threading an operation
...
over a phi node by applying it to each operand may be wrong if the
operation and the phi node are mutually interdependent (the testcase
has a simple example of this). So only do this transform if it would
be correct to perform the operation in each predecessor of the block
containing the phi, i.e. if the other operands all dominate the phi.
This should fix the FFMPEG snow.c regression reported by İsmail Dönmez.
llvm-svn: 119347
2010-11-16 12:16:38 +00:00
7d19efd6ff
A bit more of gnu as compatibility when handling relocations with aliases.
...
llvm-svn: 119328
2010-11-16 04:11:46 +00:00
5aa33ca29d
L_bit doesn't work here.
...
llvm-svn: 119325
2010-11-16 02:20:22 +00:00
3bd60eff26
- Remove dead patterns.
...
- Add encodings to the *LDMIA_RET instrs. Probably not needed...
llvm-svn: 119323
2010-11-16 02:08:45 +00:00
02089a39a0
vldm and vstm are mnemonics for vldmia and vstmia resp.
...
llvm-svn: 119321
2010-11-16 02:00:24 +00:00
08c083148b
Make the verifier a little quieter on instructions that it's probably
...
(and likely) wrong about anyhow.
llvm-svn: 119320
2010-11-16 01:58:21 +00:00
cfedba706c
Fix a bug I introduced in the ppc refactoring, which caused long
...
branches to be emitted as:
bne cr0, 2
instead of:
bne cr0, $+8
llvm-svn: 119317
2010-11-16 01:45:05 +00:00
a68e3a5397
Encode the multi-load/store instructions with their respective modes ('ia',
...
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
llvm-svn: 119310
2010-11-16 01:16:36 +00:00
f177d16f68
Object: Get rid of sys::Path, Triple, and cleanup namespace.
...
llvm-svn: 119309
2010-11-16 01:06:51 +00:00
7b25d6fd52
add copy of comment to the code that will survive the mcjit'ization
...
llvm-svn: 119308
2010-11-16 00:57:32 +00:00
73716a600a
relax an assertion a bit, allowing the GPR argument of
...
these instructions to be encoded with getMachineOpValue.
This unbreaks ExecutionEngine/2003-01-04-ArgumentBug.ll
when running on a G5
llvm-svn: 119307
2010-11-16 00:55:51 +00:00
39aed737a6
Remember to resize SpillSlotToUsesMap when allocating an emergency spill slot.
...
Use amazing new function call technology instead of writing identical code in
multiple places.
This fixes PR8604.
llvm-svn: 119306
2010-11-16 00:41:01 +00:00
e2b8858611
Fix PR8612 in the standard spiller, take two.
...
The live range of a register defined by an early clobber starts at the use slot,
not the def slot.
Except when it is an early clobber tied to a use operand. Then it starts at the
def slot like a standard def.
llvm-svn: 119305
2010-11-16 00:40:59 +00:00
05a8daee21
Add Thumb2 encodings for mov and friends.
...
llvm-svn: 119295
2010-11-16 00:29:56 +00:00
d1993eb2a4
Change the 11 byte nop to be a single instruction.
...
llvm-svn: 119286
2010-11-15 23:10:30 +00:00
bf9f2f2c29
fix a pasto that massively broke the ppc jit while the buildbots happened
...
to be broken for other reasons
llvm-svn: 119283
2010-11-15 22:50:50 +00:00
97154f67d9
Revert "Fix PR8612 in the standard spiller as well."
...
This reverts r119183 which borke the buildbots.
llvm-svn: 119270
2010-11-15 21:51:51 +00:00
ea96321781
Attempt to provide encodings for some miscellaneous Thumb2 encodings.
...
llvm-svn: 119187
2010-11-15 21:30:39 +00:00
2ce016c7f8
Code clean up. The peephole pass should be the one updating the instruction
...
iterator, not TII->OptimizeCompareInstr.
llvm-svn: 119186
2010-11-15 21:20:45 +00:00
7d97a99f4c
Provide Thumb2 encodings for sxtb and friends.
...
llvm-svn: 119185
2010-11-15 21:12:05 +00:00
964943780b
Recommit this change and remove the failing part of the test - it didn't
...
pass in the first place and was masked by earlier failures not warning
and aborting the block.
llvm-svn: 119184
2010-11-15 21:11:06 +00:00
97825bcbfd
Fix PR8612 in the standard spiller as well.
...
The live range of a register defined by an early clobber starts at the use slot,
not the def slot.
llvm-svn: 119183
2010-11-15 20:55:53 +00:00
ddf25c341c
When spilling a register defined by an early clobber, make sure that the new
...
live ranges for the spill register are also defined at the use slot instead of
the normal def slot.
This fixes PR8612 for the inline spiller. A use was being allocated to the same
register as a spilled early clobber def.
This problem exists in all the spillers. A fix for the standard spiller is
forthcoming.
llvm-svn: 119182
2010-11-15 20:55:49 +00:00
38b469effd
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.
...
llvm-svn: 119180
2010-11-15 20:47:07 +00:00
2a3c22efba
Add Thumb2 encodings for comparison and shift operators.
...
llvm-svn: 119176
2010-11-15 19:58:36 +00:00
202d91e433
Fix compiler warnigns.
...
llvm-svn: 119175
2010-11-15 19:20:50 +00:00
0e7d728327
Add correct Thumb2 encodings for mvn and friends.
...
llvm-svn: 119170
2010-11-15 18:45:17 +00:00
5cf10ea1d1
Add FIXMEs.
...
llvm-svn: 119167
2010-11-15 18:36:48 +00:00
40a7f57d0d
Nuke redundant encoding bit set.
...
llvm-svn: 119164
2010-11-15 18:17:24 +00:00
f12ba1dfe1
Teach InstructionSimplify the trick of skipping incoming phi
...
values that are equal to the phi itself.
llvm-svn: 119161
2010-11-15 17:52:45 +00:00
8c3039b67b
Change MCExpr::EvaluateAsRelocatableImpl of variables to return the original
...
variable if recursing fails to simplify it.
Factor AliasedSymbol to be a method of MCSymbol.
Update MCAssembler::EvaluateFixup to match the change in
EvaluateAsRelocatableImpl.
Remove the WeakRefExpr hack, as the object writer now sees the weakref with
no extra effort needed.
Nothing else is using MCTargetExpr, but keep it for now.
Now that the ELF writer sees relocations with aliases, handle
.weak foo2
foo2:
.weak bar2
.set bar2,foo2
.quad bar2
the same way gas does and produce a relocation with bar2.
llvm-svn: 119152
2010-11-15 16:33:49 +00:00
96f4c01cb3
Dovetail with Dan Dunbar's rework of ELFObjectWriter.
...
Added 2 new subclasses - X86ELFObjectWriter and ARMELFObectWriter.
ARM and X86 require different code for RecordRelocation(), possibly others.
llvm-svn: 119149
2010-11-15 16:18:39 +00:00
46c79ef113
Fix PR8565.
...
This moves most of the isUsed logic to the MCSymbol itself. With this we
get a bit more relaxed about allowing definitions after uses: uses that
don't evaluate their argument immediately (jmp foo) are accepted.
ddunbar, this was the smallest compromise I could think of that lets us
accept gcc (and clang!) assembly.
llvm-svn: 119144
2010-11-15 14:40:36 +00:00
731d392d1c
Improve code layout, mostly indentation.
...
No functionality change.
llvm-svn: 119142
2010-11-15 10:12:32 +00:00
aac9fa731d
Wire up primitive support in the assembler backend for writing .o files
...
directly on the mac. This is very early, doesn't support relocations and
has a terrible hack to avoid .machine from being printed, but despite
that it generates an bitwise-identical-to-cctools .o file for stuff like
this:
define i32 @test() nounwind { ret i32 42 }
I don't plan to continue pushing this forward, but if anyone else was
interested in doing it, it should be really straight-forward.
llvm-svn: 119136
2010-11-15 08:49:58 +00:00
efacb9ee42
split out an encoder for memri operands, allowing a relocation to be plopped
...
into the immediate field. This allows us to encode stuff like this:
lbz r3, lo16(__ZL4init)(r4) ; globalopt.cpp:5
; encoding: [0x88,0x64,A,A]
; fixup A - offset: 0, value: lo16(__ZL4init), kind: fixup_ppc_lo16
stw r3, lo16(__ZL1s)(r5) ; globalopt.cpp:6
; encoding: [0x90,0x65,A,A]
; fixup A - offset: 0, value: lo16(__ZL1s), kind: fixup_ppc_lo16
With this, we should have a completely function MCCodeEmitter for PPC, wewt.
llvm-svn: 119134
2010-11-15 08:22:03 +00:00
8f4444d003
add support for encoding the lo14 forms used for a few PPC64 addressing
...
modes. For example, we now get:
ld r3, lo16(_G)(r3) ; encoding: [0xe8,0x63,A,0bAAAAAA00]
; fixup A - offset: 0, value: lo16(_G), kind: fixup_ppc_lo14
llvm-svn: 119133
2010-11-15 08:02:41 +00:00
15e9d5ef8a
fix a regression with the new instprinter: we lost the ability to
...
print DBG_VALUE instructions. This should unbreak the llvm-gcc-powerpc-darwin9
buildbot.
llvm-svn: 119132
2010-11-15 07:52:06 +00:00
6566112e9c
implement the start of support for lo16 and ha16, allowing us to get stuff like:
...
lis r4, ha16(__ZL4init) ; encoding: [0x3c,0x80,A,A]
; fixup A - offset: 0, value: ha16(__ZL4init), kind: fixup_ppc_ha16
llvm-svn: 119127
2010-11-15 06:33:39 +00:00
85e37684bf
add a fixup for conditional branches, giving us output like this:
...
beq cr0, LBB0_4 ; encoding: [0x41,0x82,A,0bAAAAAA00]
; fixup A - offset: 0, value: LBB0_4, kind: fixup_ppc_brcond14
llvm-svn: 119126
2010-11-15 06:12:22 +00:00
0e3461e417
change direct branches to encode with the same encoding method
...
as direct calls. Change conditional branches to encode with
their own method, simplifying the JIT encoder and making room
for adding an mc fixup.
llvm-svn: 119125
2010-11-15 06:09:35 +00:00
7064198397
eliminate a now-unneeded operand printer.
...
llvm-svn: 119124
2010-11-15 06:01:10 +00:00
79fa37152a
split call operands out to their own encoding class, simplifying
...
code in the JIT. Use this to form the first fixup for the PPC backend,
giving us stuff like this:
bl L_foo$stub ; encoding: [0b010010AA,A,A,0bAAAAAA01]
; fixup A - offset: 0, value: L_foo$stub, kind: fixup_ppc_br24
llvm-svn: 119123
2010-11-15 05:57:53 +00:00
9e7d8c0313
correct the fixup comment printer to work on big endian platforms.
...
llvm-svn: 119122
2010-11-15 05:56:19 +00:00
d6a07ccd10
add proper encoding for MTCRF instead of using a hack.
...
llvm-svn: 119121
2010-11-15 05:19:25 +00:00
63274cbc5d
add fields to the .td files unconditionally, simplifying tblgen a bit.
...
Switch the ARM backend to use 'let' instead of 'set' with this change.
llvm-svn: 119120
2010-11-15 05:19:05 +00:00
c877d8f44c
add basic encoding support for immediates and registers, allowing us
...
to encode all of these instructions correctly (for example):
mflr r0 ; encoding: [0x7c,0x08,0x02,0xa6]
stw r0, 8(r1) ; encoding: [0x90,0x01,0x00,0x08]
stwu r1, -64(r1) ; encoding: [0x94,0x21,0xff,0xc0]
llvm-svn: 119118
2010-11-15 04:51:55 +00:00
0ae07e1484
add a dummy entry to fix a build error
...
llvm-svn: 119117
2010-11-15 04:47:16 +00:00
9ec375c8ea
Implement a basic MCCodeEmitter for PPC. This doesn't handle
...
fixups yet, and doesn't handle actually encoding operand values,
but this is enough for llc -show-mc-encoding to show the base
instruction encoding information, e.g.:
mflr r0 ; encoding: [0x7c,0x08,0x02,0xa6]
stw r0, 8(r1) ; encoding: [0x90,0x00,0x00,0x00]
stwu r1, -64(r1) ; encoding: [0x94,0x00,0x00,0x00]
Ltmp0:
lhz r4, 4(r3) ; encoding: [0xa0,0x00,0x00,0x00]
cmplwi cr0, r4, 8 ; encoding: [0x28,0x00,0x00,0x00]
beq cr0, LBB0_2 ; encoding: [0x40,0x00,0x00,0x00]
llvm-svn: 119116
2010-11-15 04:16:32 +00:00
045e04dbfe
dissolve some more hacks.
...
llvm-svn: 119115
2010-11-15 03:53:53 +00:00
fd56ee2c40
fix some fixme's, removing dead code.
...
llvm-svn: 119114
2010-11-15 03:51:13 +00:00
aa4d03d1f5
remove asmstrings (which can never be printed) from pseudo
...
instructions, allowing is to eliminate some dead operand
printing methods from the instprinter.
llvm-svn: 119113
2010-11-15 03:48:58 +00:00
8bcfdab194
strength reduce TOC temp label generation, no functionality change.
...
llvm-svn: 119112
2010-11-15 03:42:54 +00:00
510c66f549
rip out a ton of old instruction printing junk now that the
...
new instprinting logic is there.
llvm-svn: 119111
2010-11-15 03:39:06 +00:00
f4a6a14c93
Object: Add missing makefile.
...
llvm-svn: 119110
2010-11-15 03:33:14 +00:00
dd96e97317
Make sure ARM multi load / store pass copies memoperands when forming ldrd / strd. pr8113.
...
llvm-svn: 119109
2010-11-15 03:30:30 +00:00
d7c2fc7a73
Turn on the new instprinter by default.
...
The only change in the output is:
1) we get a better comment on mfcr, we get:
mfcr r2 ; cr2
instead of:
mfcr r2 ; 32
2) we no longer emit $stub's on powerpc/leopard. The Leopard
linker autosynthesizes them.
llvm-svn: 119108
2010-11-15 03:27:05 +00:00
fe5ee80268
Add LLVMObject Library.
...
llvm-svn: 119107
2010-11-15 03:21:41 +00:00
dd6df84900
convert the operand bits into bitfields since they are all combinable in
...
different ways. Add $non_lazy_ptr support, and proper lowering for
global values.
Now all the ppc regression tests pass with the new instruction printer.
llvm-svn: 119106
2010-11-15 03:13:19 +00:00
edb9d84dcc
add targetoperand flags for jump tables, constant pool and block address
...
nodes to indicate when ha16/lo16 modifiers should be used. This lets
us pass PowerPC/indirectbr.ll.
The one annoying thing about this patch is that the MCSymbolExpr isn't
expressive enough to represent ha16(label1-label2) which we need on
PowerPC. I have a terrible hack in the meantime, but this will have
to be revisited at some point.
Last major conversion item left is global variable references.
llvm-svn: 119105
2010-11-15 02:46:57 +00:00
e75bb34963
remove some extraneous quotes to make the new instprinter match.
...
llvm-svn: 119104
2010-11-15 02:43:46 +00:00
3ddef1ac36
silence a ton of warnings from clang.
...
llvm-svn: 119102
2010-11-15 01:45:44 +00:00
51d2e9ca29
Attempt to unbreak cmake-based builds
...
llvm-svn: 119098
2010-11-15 00:48:12 +00:00
f7183edb59
First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place
...
llvm-svn: 119097
2010-11-15 00:06:54 +00:00
a5ab8f10e4
Whitespace cleanup
...
llvm-svn: 119096
2010-11-15 00:06:05 +00:00
240028d11d
Move the logic to decide with which symbol we produce a relocation (if any) to
...
a central location. This also makes us a bit more compatible with gas.
llvm-svn: 119094
2010-11-14 23:53:26 +00:00
df8e17d80b
implement support for the MO_DARWIN_STUB TargetOperand flag,
...
and have isel apply to to call operands as required. This allows
us to get $stub suffixes on label references on ppc/tiger with the
new instprinter, fixing two tests. Only 2 to go.
llvm-svn: 119093
2010-11-14 23:42:06 +00:00
ea857d357f
tidy up, no functionality change.
...
llvm-svn: 119092
2010-11-14 23:32:42 +00:00
b7c67f6c17
with the picbase nonsense starting to be figured out, implement
...
lowering support for MovePCtoLR[8]. Down to 4 failures again.
llvm-svn: 119090
2010-11-14 22:56:43 +00:00
7077efe894
move the pic base symbol stuff up to MachineFunction
...
since it is trivial and will be shared between ppc and x86.
This substantially simplifies the X86 backend also.
llvm-svn: 119089
2010-11-14 22:48:15 +00:00
239f9a35ed
simplify getPICBaseSymbol a bit.
...
llvm-svn: 119088
2010-11-14 22:37:11 +00:00
94f0c14cb0
reimplement ppc asmprinter "toc" handling to use a VariantKind
...
on the operand, required for .o file writing and fixing
the PowerPC/mult-alt-generic-powerpc64.ll failure with the new
instprinter.
llvm-svn: 119087
2010-11-14 22:22:59 +00:00
2f9f63af0b
lower PPC::MFCRpseud when transforming to MC, avoiding calling
...
the aborting printSpecial() method. This gets us to 8 failures.
llvm-svn: 119084
2010-11-14 22:03:15 +00:00
cfb6287487
make the stubbed-out printer methods abort instead of
...
printing nothing. This gets us back up to 24 failures.
llvm-svn: 119083
2010-11-14 21:54:34 +00:00
f2cb69cb04
wire up a few more things, down to 4 test failures, all
...
about handling $stub, lo/hi etc.
llvm-svn: 119082
2010-11-14 21:51:37 +00:00
e2d75bf681
properly wire up the instprinter to the ppc64 backend, down to 5 failures.
...
llvm-svn: 119081
2010-11-14 21:42:53 +00:00
219cc3d586
implement pretty printing support for the various pseudo
...
ops the asmprinter supported, fixing PowerPC/rlwimi2.ll
among others. Down to 20 failures.
llvm-svn: 119080
2010-11-14 21:39:51 +00:00
c2ac86e261
Wire up symbol hi/lo printing. We don't print hi()/lo(), but this gets
...
us further along. Only 28 failures now.
llvm-svn: 119079
2010-11-14 21:33:07 +00:00
3dc9bb245f
implement basic support for symbol operand lowering,
...
and printing support for call operands. Down to 77 failures.
llvm-svn: 119078
2010-11-14 21:20:46 +00:00
2aa8becf33
trim #includes.
...
llvm-svn: 119075
2010-11-14 21:16:04 +00:00
5c1b0cdec2
switch PPC to a simplified MCInstLowering model.
...
llvm-svn: 119074
2010-11-14 21:12:33 +00:00
a7d0bed336
Fix another case of a .comm directive without a corresponding .type
...
directive.
llvm-svn: 119073
2010-11-14 21:11:16 +00:00
0927edf815
fix PPC.h to not pull in TargetMachine.h
...
llvm-svn: 119072
2010-11-14 21:09:28 +00:00
de16ca8ecc
rename LowerToMCInst -> LowerARMMachineInstrToMCInst.
...
llvm-svn: 119071
2010-11-14 21:00:02 +00:00
c5afd12557
even more simplifications. ARM MCInstLowering is now just
...
a single function instead of a class. It doesn't need the
complexity that X86 does.
llvm-svn: 119070
2010-11-14 20:58:38 +00:00
18442f5543
more shrinkification
...
llvm-svn: 119068
2010-11-14 20:41:53 +00:00
3040e8c69b
more simplifications.
...
llvm-svn: 119067
2010-11-14 20:40:08 +00:00
b28e691657
simplify and tidy up
...
llvm-svn: 119066
2010-11-14 20:31:06 +00:00
0dcd800b22
implement basic support for memory operands and crbit operands,
...
this fixes 3 more ppc tests.
llvm-svn: 119065
2010-11-14 20:22:56 +00:00
9488143769
implement several trivial operand printers, reducing
...
failures in CodeGen/PowerPC from 120 -> 117
llvm-svn: 119063
2010-11-14 20:11:21 +00:00
7a5c57ecf4
Implement support for printing register and immediate operands,
...
add support for darwin vs aix syntax. We now can print instructions
like this:
add r3, r3, r4
blr
and (in aix mode):
add 3, 3, 4
blr
llvm-svn: 119062
2010-11-14 20:02:39 +00:00
686a095d89
stub out PPCMCInstLowering, add a new option that uses it and the new
...
instprinter when -enable-ppc-inst-printer is passed to llc.
llvm-svn: 119061
2010-11-14 19:53:02 +00:00
b05ef7377a
Fix the type of a symbol created with .comm and no corresponding .type.
...
llvm-svn: 119060
2010-11-14 19:40:55 +00:00
a76eab433a
stub out a powerpc MCInstPrinter implementation.
...
llvm-svn: 119059
2010-11-14 19:40:38 +00:00
66031ed839
move all the target's asmprinters into the main target. The piece
...
that should be split out is the InstPrinter (if a target is mc'ized).
This change makes all the targets be consistent.
llvm-svn: 119056
2010-11-14 18:43:56 +00:00
b99f39b9f6
If dom tree information is available, make it possible to pass
...
it to get better phi node simplification.
llvm-svn: 119055
2010-11-14 18:36:10 +00:00
56477d1690
move PPCAsmPrinter into the main PPC library, like ARM and X86.
...
llvm-svn: 119054
2010-11-14 18:33:33 +00:00
dab307c6f4
fix cmake
...
llvm-svn: 119053
2010-11-14 18:27:11 +00:00
9007c368c6
remove JIT support from the Alpha backend. The JIT will be moving to MC,
...
and the Alpha backend isn't MCized yet. Approved by Andrew.
llvm-svn: 119051
2010-11-14 18:24:41 +00:00
57479f5ce9
random acts of tidiness.
...
llvm-svn: 119049
2010-11-14 18:09:50 +00:00
4581ddc123
Teach InstructionSimplify about phi nodes. I chose to have it simply
...
offload the work to hasConstantValue rather than do something more
complicated (such handling mutually recursive phis) because (1) it is
not clear it is worth it; and (2) if it is worth it, maybe such logic
would be better placed in hasConstantValue. Adjust some GVN tests
which are now cleaned up much further (eg: all phi nodes are removed).
llvm-svn: 119043
2010-11-14 13:30:18 +00:00
1d27f01210
Boost the power of phi node constant folding slightly: if all
...
operands are the phi node itself or undef, then return undef.
This logic already existed at a higher level so in practice it
shouldn't make the slightest difference. Note that this code
could be replaced by a call to PN->hasConstantValue(). However
since we bail out the moment we see a non-constant operand, it
is more efficient to have a specialized version of that logic.
llvm-svn: 119041
2010-11-14 12:53:18 +00:00
7e800d6f9c
Strip trailing whitespace.
...
llvm-svn: 119038
2010-11-14 11:23:23 +00:00
e0f6b41618
Second attempt at providing correct encodings for Thumb2 binary operators.
...
llvm-svn: 119029
2010-11-14 05:37:38 +00:00
7d0ba3464e
Handle a peculiar comdat case: Creating a section with an undefined
...
signature symbol causes a local symbol to be created unless there is
some other use of the symbol.
llvm-svn: 119026
2010-11-14 04:17:37 +00:00
0e3decfcf7
Simplify getSymbolIndexInSymbolTable by setting the actual index of
...
the symbols.
llvm-svn: 119022
2010-11-14 03:12:24 +00:00
eba9022652
Fix warning.
...
llvm-svn: 119021
2010-11-14 01:34:31 +00:00
feea10bcdf
Recognise 32-bit ror-based bswap implementation used by uclibc
...
llvm-svn: 119007
2010-11-13 19:54:30 +00:00
1c6437a62a
Support ; as asm separator
...
llvm-svn: 119006
2010-11-13 19:54:23 +00:00
641baf1646
Generalize the reassociation transform in SimplifyCommutative (now renamed to
...
SimplifyAssociativeOrCommutative) "(A op C1) op C2" -> "A op (C1 op C2)",
which previously was only done if C1 and C2 were constants, to occur whenever
"C1 op C2" simplifies (a la InstructionSimplify). Since the simplifying operand
combination can no longer be assumed to be the right-hand terms, consider all of
the possible permutations. When compiling "gcc as one big file", transform 2
(i.e. using right-hand operands) fires about 4000 times but it has to be said
that most of the time the simplifying operands are both constants. Transforms
3, 4 and 5 each fired once. Transform 6, which is an existing transform that
I didn't change, never fired. With this change, the testcase is now optimized
perfectly with one run of instcombine (previously it required instcombine +
reassociate + instcombine, and it may just have been luck that this worked).
llvm-svn: 119002
2010-11-13 15:10:37 +00:00
e5ac78e16e
Fix typo pointed out by Trevor Harmon.
...
llvm-svn: 119001
2010-11-13 12:16:27 +00:00
9430eb489c
Comment out the defms until they're activated.
...
llvm-svn: 119000
2010-11-13 11:20:05 +00:00
705ec77ab5
Add uses of the *_ldst_multi multiclasses. These aren't used yet.
...
llvm-svn: 118999
2010-11-13 10:57:02 +00:00
c4c642832d
Convert the modes to lower case.
...
llvm-svn: 118998
2010-11-13 10:43:34 +00:00
f2fa04acfc
Minor cleanups:
...
- Get the opcode once.
- Add a ParserMatchClass to reglist.
llvm-svn: 118997
2010-11-13 10:40:19 +00:00
e69afc6bb7
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
...
future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.
llvm-svn: 118995
2010-11-13 09:09:38 +00:00
fe0c28f4db
MC: Simplify Mach-O and ELF object writer implementations.
...
- What was I thinking?????
llvm-svn: 118992
2010-11-13 07:33:40 +00:00
82471189b7
Fixed error and re-enabled MBlaze MC disassembler tests.
...
llvm-svn: 118987
2010-11-13 05:48:21 +00:00
79ff5238e9
Conditional moves are slightly more expensive than moves.
...
llvm-svn: 118985
2010-11-13 05:14:20 +00:00
2d006b1ade
Fix warning and add support for printing gnu_unique_object.
...
llvm-svn: 118981
2010-11-13 04:55:06 +00:00
4bcf94c75a
Parse and record the gnu_unique_object type.
...
llvm-svn: 118980
2010-11-13 04:51:02 +00:00
f01b622902
Parse and remember discriminators in .loc line. I try to output them with
...
another patch.
This lets us parse a bit more of the gcc 4.5 output.
llvm-svn: 118975
2010-11-13 03:18:27 +00:00
868e3f0977
JIT: More nitty style tweakage, aka territory marking.
...
llvm-svn: 118973
2010-11-13 02:48:57 +00:00
2ed3fe08e9
report_fatal_error: Simplify a possible ambiguity.
...
llvm-svn: 118972
2010-11-13 02:48:51 +00:00
b3099e6863
1. Adding test cases for MBlaze MC disassembler.
...
2. Fixing several errors in disassembler uncovered by test cases.
3. Fixing invalid encoding of PCMPEQ and PCMPNE uncovered by test cases.
llvm-svn: 118969
2010-11-13 02:37:59 +00:00
2bcb8daa44
Add conditional move of large immediate.
...
llvm-svn: 118968
2010-11-13 02:25:14 +00:00
1aa5863a3e
Swap multiclass operand order for consistency with other patterns.
...
llvm-svn: 118965
2010-11-13 01:28:30 +00:00
69fd90e661
Continue ARM indexed load refactoring. Multiclass for LDR{B} pre/post indexed
...
instructions.
llvm-svn: 118963
2010-11-13 01:07:20 +00:00
1d37f35eea
Fix the encoding of negative line deltas.
...
llvm-svn: 118962
2010-11-13 01:06:27 +00:00
4a92fcb9fd
Fix some more 80-col violas.
...
llvm-svn: 118959
2010-11-13 00:55:45 +00:00
e4f4743409
Fix 80-col violation / non-sensicalness.
...
llvm-svn: 118958
2010-11-13 00:55:42 +00:00
2f790749e8
More ARM load/store indexed refactoring. Also fix an incorrect IndexMode
...
flag for the LDRT/STRT family instructions as a side effect.
llvm-svn: 118955
2010-11-13 00:35:48 +00:00
1279fc47f9
Revert r118917, which is implicated in the llvm-gcc-i386-linux-selfhost failure.
...
llvm-svn: 118954
2010-11-13 00:31:40 +00:00
8ce967e393
Fix an obvious typo which inverted an immediate.
...
llvm-svn: 118951
2010-11-13 00:27:47 +00:00
240162629c
1. Adding missing immediate mode asm parser test cases.
...
2. Fixing improper immediate mode reverse subtract.
llvm-svn: 118948
2010-11-13 00:03:46 +00:00
1293c6a23a
Temporarily revert this.
...
llvm-svn: 118946
2010-11-12 23:50:48 +00:00
9c40af415f
For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled with movi + orr.
...
llvm-svn: 118945
2010-11-12 23:46:13 +00:00
4b074b8995
Fixing improperly encoded reverse subtract instructions in MBlaze backend.
...
llvm-svn: 118943
2010-11-12 23:41:10 +00:00
7cd724ae7d
Revert r118939 while I work out why it broke some buildbots.
...
llvm-svn: 118942
2010-11-12 23:36:03 +00:00
c542248602
1. Finishing MBlaze MC asm parser test cases
...
2. Parsing .word directive in MBlaze asm parser
3. Fixing hack where memory instructions reversed order of last two parameters
4. Fixing many improperly encoded instructions
5. Support parsing special instructions (MFS,MTS,etc.)
6. Removing unused functions from inst printer
llvm-svn: 118941
2010-11-12 23:30:17 +00:00
53a40df6ea
Remove DW_AT_start_scope support. It is incomplete and superseeded by location entries support.
...
llvm-svn: 118940
2010-11-12 23:20:42 +00:00
0003a296ad
Attemt to provide correct encodings for Thumb2 binary operators.
...
llvm-svn: 118939
2010-11-12 23:18:11 +00:00
f478cf9685
Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.
...
llvm-svn: 118938
2010-11-12 23:03:38 +00:00
49a66f7d71
Make this happen for ARM like x86. Don't entirely bail out when
...
an address is in a different block, get it into a register and go
from there.
llvm-svn: 118936
2010-11-12 22:52:32 +00:00
0fc8084a64
Add conditional mvn instructions.
...
llvm-svn: 118935
2010-11-12 22:42:47 +00:00
e09122b46b
Zap a copy/paste-o bit of dead code.
...
llvm-svn: 118926
2010-11-12 21:29:10 +00:00
31a7234a47
Refactor to parameterize some ARM load/store encoding patterns. Preparatory
...
to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.
llvm-svn: 118925
2010-11-12 21:28:15 +00:00
8fdd172502
First stab at providing correct Thumb2 encodings, start with adc.
...
llvm-svn: 118924
2010-11-12 21:12:40 +00:00
246b71c596
Have GVN simplify instructions as it goes. For example, consider
...
"%z = %x and %y". If GVN can prove that %y equals %x, then it turns
this into "%z = %x and %x". With the new code, %z will be replaced
with %x everywhere (and then deleted). Previously %z would be value
numbered too, which is a waste of time. Also, while a clever value
numbering algorithm would give %z the same value number as %x, our
current one doesn't do so (at least I don't think it does). The new
logic has an essentially equivalent effect to what you would get if
%z was given the same value number as %x, i.e. it should make value
numbering smarter. While there, get hold of target data once at the
start rather than a gazillion times all over the place.
llvm-svn: 118923
2010-11-12 21:10:24 +00:00
2d59ee34f1
Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next.
...
llvm-svn: 118922
2010-11-12 20:32:20 +00:00
6bb1ae9d45
Kill more unused stuff.
...
llvm-svn: 118921
2010-11-12 19:27:45 +00:00
dcc7732f88
MCELF: Copy the symbol name only if we're going to modify it.
...
llvm-svn: 118920
2010-11-12 19:26:04 +00:00
984ff7d17e
Remove unused class.
...
llvm-svn: 118919
2010-11-12 19:24:53 +00:00
0284c5d0c7
When the definition of an address value is in a different block
...
from the user of the address, fall back to just using the
address in a register instead of bailing out of fast-isel
altogether.
llvm-svn: 118917
2010-11-12 19:14:00 +00:00
87cf7f787e
accept lret as an alias for lretl, fixing the reopened part of PR8592
...
llvm-svn: 118916
2010-11-12 18:54:56 +00:00
c4f4b2e878
Remove what looks like dead code in the production of debug lines.
...
We only produce debug line information if we have seen a line directive, so
this code is dead. Also, if we want to be bug by bug compatible with
gas and sometimes produce "empty" .debug_line sections, this will
match the content produced by gas.
llvm-svn: 118914
2010-11-12 18:41:26 +00:00
6cbf6c1db5
typo (4th checkin for one fix)
...
llvm-svn: 118913
2010-11-12 18:36:03 +00:00
3fd741191d
Fill in the default predication bits for ARM unconditional branch.
...
llvm-svn: 118907
2010-11-12 18:13:26 +00:00
0deb9c20c0
Encoding for ARM LDRSB instructions.
...
llvm-svn: 118905
2010-11-12 17:52:59 +00:00
116efac780
Fixes PR8287: SD scheduling time. The fix is a failsafe that prevents
...
catastrophic compilation time in the event of unreasonable LLVM
IR. Code quality is a separate issue--someone upstream needs to do a
better job of reducing to llvm.memcpy. If the situation can be reproduced with
any supported frontend, then it will be a separate bug.
llvm-svn: 118904
2010-11-12 17:50:46 +00:00
5b013b102d
implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix.
...
llvm-svn: 118903
2010-11-12 17:41:20 +00:00
64634c36dd
tidy up.
...
llvm-svn: 118896
2010-11-12 17:24:29 +00:00
de990b270d
gnu as support both % and @ before types, do the same.
...
llvm-svn: 118893
2010-11-12 15:47:08 +00:00
970afd926f
Re-disable TBAA for now; it broke MultiSource/Applications/JM/lencod,
...
at least.
llvm-svn: 118890
2010-11-12 11:21:08 +00:00
0a9dd405a5
Fix memory access lowering on SPU, adding
...
support for the case where alignment<value size.
These cases were silently miscompiled before this patch.
Now they are overly verbose -especially storing is- and
any front-end should still avoid misaligned memory
accesses as much as possible. The bit juggling algorithm
added here probably has some room for improvement still.
llvm-svn: 118889
2010-11-12 10:14:03 +00:00
22d0492f34
Fix up a few more spots of addrmode2 (or not) changes that were
...
missed. Update some comments accordingly.
Fixes rdar://8652289
llvm-svn: 118888
2010-11-12 09:48:30 +00:00
ea18d8ec2d
Enable TBAA.
...
llvm-svn: 118884
2010-11-12 06:20:01 +00:00
c702ba6ca1
Fix some style issues in PBQP. Patch by David Blaikie.
...
llvm-svn: 118883
2010-11-12 05:47:21 +00:00
d4b7fff2e8
Enhance DSE to handle the case where a free call makes more than
...
one store dead. This is especially noticeable in
SingleSource/Benchmarks/Shootout/objinst.
llvm-svn: 118875
2010-11-12 02:19:17 +00:00
6d95ed1760
Remove possibly useful info from comment, per Chris.
...
llvm-svn: 118865
2010-11-12 00:43:18 +00:00
03c0330176
Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>
...
llvm-svn: 118864
2010-11-12 00:38:32 +00:00
20b6fd7d5d
Start of support for binary emit of 16-it Thumb instructions.
...
llvm-svn: 118859
2010-11-11 23:41:09 +00:00
ce2250fba4
Fill out support for Thumb2 encodings of NEON instructions.
...
llvm-svn: 118854
2010-11-11 23:12:55 +00:00
8abdf4b6ea
The BRK instruction in the MicroBlaze is a branch-and-link.
...
llvm-svn: 118848
2010-11-11 22:21:08 +00:00
add50b0a5d
Doxygenify
...
llvm-svn: 118846
2010-11-11 21:51:44 +00:00
65316d6749
Add helper functions for computing the Location of load, store,
...
and vaarg instructions.
llvm-svn: 118845
2010-11-11 21:50:19 +00:00
bf65066a37
Fix tblgen instruction errors exposed by MC asm parser tests
...
Fix minimum 16-bit signed value error exposed by MC asm parser tests
Add initial MC asm parser tests for the MBlaze backend
llvm-svn: 118844
2010-11-11 21:40:53 +00:00
99a8cb4875
Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].
...
llvm-svn: 118843
2010-11-11 21:36:43 +00:00
468638826e
Don't forget the TBAA info, if available.
...
llvm-svn: 118842
2010-11-11 21:27:26 +00:00
a826a88755
Factor out Instruction::isSafeToSpeculativelyExecute's code for
...
testing for dereferenceable pointers into a helper function,
isDereferenceablePointer. Teach it how to reason about GEPs
with simple non-zero indices.
Also eliminate ArgumentPromtion's IsAlwaysValidPointer,
which didn't check for weak externals or out of range gep
indices.
llvm-svn: 118840
2010-11-11 21:23:25 +00:00
7ae11c6962
Revert the accidental commit I made reverting the previous commit.
...
llvm-svn: 118835
2010-11-11 20:50:14 +00:00
ba321cb120
Trailing whitespace.
...
llvm-svn: 118831
2010-11-11 20:16:23 +00:00
c33f28bf90
ARM fixup encoding for direct call instructions (BL).
...
llvm-svn: 118829
2010-11-11 20:05:40 +00:00
b90f7004cf
Revert this temporarily.
...
llvm-svn: 118827
2010-11-11 19:47:02 +00:00
e6283f950d
Change the prologue and epilogue to use push/pop for the low ARM registers.
...
llvm-svn: 118823
2010-11-11 19:26:03 +00:00
7dacf8f3f3
Avoid calling alias on non-pointer values.
...
llvm-svn: 118822
2010-11-11 19:23:51 +00:00
7ffe3b35ac
Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
...
More tests to come.
llvm-svn: 118819
2010-11-11 19:07:48 +00:00
84d031870c
Mark labels declared in tls sections as STT_TLS. This matches the behavior of
...
gas.
llvm-svn: 118818
2010-11-11 19:04:55 +00:00
d1a6f5a384
Fixed some bugs in MBlaze asm parser that were introduced when removing OwningPtrs from the code.
...
llvm-svn: 118807
2010-11-11 18:41:33 +00:00
932aab3cbf
add a note
...
llvm-svn: 118806
2010-11-11 18:23:57 +00:00
a3e9a2298d
Initial comdat implementation.
...
llvm-svn: 118805
2010-11-11 18:13:52 +00:00
dcdfd8dd24
TBAA-enable ArgumentPromotion.
...
llvm-svn: 118804
2010-11-11 18:09:32 +00:00
4162e3e213
Add a FIXME comment.
...
llvm-svn: 118803
2010-11-11 18:08:43 +00:00
9d6d77a9f4
Encoding of destination fixup for ARM branch and conditional branch
...
instructions.
llvm-svn: 118801
2010-11-11 18:04:49 +00:00
f11344d770
Check TRI->getReservedRegs because other allocators do it. Even though
...
it makes no sense for allocation_order iterators to visit reserved regs.
The inline spiller depends on AliasAnalysis.
Manage the Query state to avoid uninitialized or stale results.
llvm-svn: 118800
2010-11-11 17:46:29 +00:00
fb6540c112
Make AliasedSymbol able to handle MCTargetExpr. They can get here if
...
a weakref is used with a VariantKind.
llvm-svn: 118798
2010-11-11 17:24:43 +00:00
1d6aa32b87
add pr#
...
llvm-svn: 118797
2010-11-11 17:17:56 +00:00
68685e644f
Encoding for ARM LDRSH_POST.
...
llvm-svn: 118794
2010-11-11 16:55:29 +00:00
fa7b55754c
Fix the symbol index of weak references. Also make RecordRelocation a bit
...
easier to read by having const references to the symbol, aliased symbol and
renamed symbol.
llvm-svn: 118793
2010-11-11 16:48:11 +00:00
f51d06bbee
Include ImmutablePass passes in -debug-pass=Arguments.
...
llvm-svn: 118790
2010-11-11 16:32:17 +00:00
6cf9bb45ad
Remove the memmove->memcpy optimization from CodeGen. MemCpyOpt does this.
...
llvm-svn: 118789
2010-11-11 16:24:49 +00:00
0cc4c7516e
Make Sink tbaa-aware.
...
llvm-svn: 118788
2010-11-11 16:21:47 +00:00
c3b4ea7b7d
It's safe to sink some instructions which are not safe to speculatively
...
execute. Make Sink's predicate more precise.
llvm-svn: 118787
2010-11-11 16:20:28 +00:00
19fa38000a
Remove some explicit arguments to getELFSection. This is
...
a leftover from the removal of isExplicit.
llvm-svn: 118774
2010-11-11 03:40:25 +00:00
f18b951e18
Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.
...
llvm-svn: 118767
2010-11-11 01:55:59 +00:00
e967c0a795
Fix encoding of Ra register for ARM smla* instructions.
...
llvm-svn: 118761
2010-11-11 01:27:41 +00:00
607efcbc3e
ARM STRH encoding information.
...
llvm-svn: 118757
2010-11-11 01:09:40 +00:00
9a2c6b8f3e
Delete SplittingSpiller. It was not being used by anyone, and it is being
...
superceded by SplitKit.
llvm-svn: 118754
2010-11-11 00:52:44 +00:00
c87c843db7
It's not necessary to clear out the Size and TBAATag at each of
...
these points.
llvm-svn: 118752
2010-11-11 00:42:22 +00:00
8bf3d832e5
Set NonLocalDepInfo's Size field to UnknownSize when invalidating
...
it, so that it doesn't appear to be a known size.
llvm-svn: 118748
2010-11-11 00:20:27 +00:00
c400670bf1
Insert two blank SlotIndexes between basic blocks instead of just one.
...
This is the first small step towards using closed intervals for liveness instead
of the half-open intervals we're using now.
We want to be able to distinguish between a SlotIndex that represents a variable
being live-out of a basic block, and an index representing a variable live-in to
its successor.
That requires two separate indexes between blocks. One for live-outs and one for
live-ins.
With this change, getMBBEndIdx(MBB).getPrevSlot() becomes stable so it stays
greater than any instructions inserted at the end of MBB.
llvm-svn: 118747
2010-11-11 00:19:20 +00:00
3cb87f4c31
No need to add liveness that's already there.
...
llvm-svn: 118742
2010-11-10 23:56:00 +00:00
868dd4e66a
Hook up AliasAnalysis in InlineSpiller. This is used for rematerializing
...
constant loads.
llvm-svn: 118741
2010-11-10 23:55:56 +00:00
c4dd2349c7
Move LDM predicate operand encoding into base clase. Add STM missing STM
...
encoding bits.
llvm-svn: 118738
2010-11-10 23:44:32 +00:00
cc4a491557
ARM LDM encoding for the mode (ia, ib, da, db) operand.
...
llvm-svn: 118736
2010-11-10 23:38:36 +00:00
5a8d781caa
Factor some code into WriteSection.
...
llvm-svn: 118733
2010-11-10 23:36:59 +00:00
58ef598cd1
Fix ARM encoding of non-return LDM instructions.
...
llvm-svn: 118732
2010-11-10 23:18:49 +00:00
e39a9fcc0e
Fix ARM encoding of LDM+Return instruction.
...
llvm-svn: 118730
2010-11-10 23:12:48 +00:00
6791936848
When clearing a non-local pointer dependency cache entry, clear
...
the reverse map too. This fixes seflhost build errors.
llvm-svn: 118729
2010-11-10 22:35:02 +00:00
eb97f59753
Update the section index map after we add the medatada sections.
...
llvm-svn: 118728
2010-11-10 22:34:07 +00:00
364bf04267
Take care of special characters while creating named MDNode name to hold function specific local variable's info.
...
This fixes radar 8653152. I am checking in testcase as a separate check-in.
llvm-svn: 118726
2010-11-10 22:19:21 +00:00
1801410fa8
Use SectionIndexMap in WriteSymbolTable to make it a little less brittle.
...
llvm-svn: 118725
2010-11-10 22:16:43 +00:00
1d760ce8b3
Factor out the code for computing an AliasAnalysis::Location
...
for a given instruction into a helper function.
llvm-svn: 118723
2010-11-10 21:51:35 +00:00
d634003ebd
Factor some code into ComputeIndexMap.
...
llvm-svn: 118722
2010-11-10 21:51:05 +00:00
2e8ca44b81
Fully invalidate cached results when a prior query's size or
...
type is insufficient for, or incompatible with, the current query.
llvm-svn: 118721
2010-11-10 21:45:11 +00:00
ca52411955
Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build vector with 2 elts
...
llvm-svn: 118720
2010-11-10 21:35:41 +00:00
8f7220e9fd
Reduce the maximum recursion depth, 5 seems pointlessly too much.
...
Probably it should just be 1, but compromise with 3.
llvm-svn: 118718
2010-11-10 20:53:24 +00:00
0a6021a54d
Enhance GVN to do more precise alias queries for non-local memory
...
references. For example, this allows gvn to eliminate the load in
this example:
void foo(int n, int* p, int *q) {
p[0] = 0;
p[1] = 1;
if (n) {
*q = p[0];
}
}
llvm-svn: 118714
2010-11-10 20:37:15 +00:00
51d68339a2
Change the String<size> methods to take a fragment instead of a buffer.
...
llvm-svn: 118709
2010-11-10 20:02:59 +00:00
6ee7d9aade
Basic rematerialization during splitting.
...
Whenever splitting wants to insert a copy, it checks if the value can be
rematerialized cheaply instead.
Missing features:
- Delete instructions when all uses have been rematerialized.
- Truncate live ranges to the remaining uses after rematerialization.
llvm-svn: 118702
2010-11-10 19:31:50 +00:00
89eb6a8b94
RABasic is nearly functionally complete. There are a few remaining
...
benchmarks hitting an assertion.
Adds LiveIntervalUnion::collectInterferingVRegs.
Fixes "late spilling" by checking for any unspillable live vregs among
all physReg aliases.
llvm-svn: 118701
2010-11-10 19:18:47 +00:00
36ef57d2eb
Use MCSectionELF in places we know we have an ELF section.
...
llvm-svn: 118699
2010-11-10 19:05:07 +00:00
d209911642
Use getValueOperand() and getPointerOperand() on load and store
...
instructions instead of hard-coding operand numbers.
llvm-svn: 118698
2010-11-10 19:03:33 +00:00
f3b1bf1606
Teach InstructionSimplify how to look through PHI nodes. Since PHI
...
nodes can be used in loops, this could result in infinite looping
if there is no recursion limit, so add such a limit. It is also
used for the SelectInst case because in theory there could be an
infinite loop there too if the basic block is unreachable.
llvm-svn: 118694
2010-11-10 18:23:01 +00:00
066c1bb1e9
Add a doesAccessArgPointees helper function, and update code to use
...
it, and to be consistent.
llvm-svn: 118692
2010-11-10 18:17:28 +00:00
ca21cd749e
Simplify and clean up MC symbol lookup for ARM constant pool values. This fixes
...
double quoting of ObjC symbol names in constant pool entries.
rdar://8652107
llvm-svn: 118688
2010-11-10 17:59:10 +00:00
2577580967
Factor out the code for testing whether a function accesses
...
arbitrary memory into a helper function, and adjust some comments.
llvm-svn: 118687
2010-11-10 17:34:04 +00:00
b39a89716f
Fix Whitespace.
...
llvm-svn: 118683
2010-11-10 15:06:00 +00:00
909d238eba
System/Win32/Path: Implement isSymLink.
...
llvm-svn: 118681
2010-11-10 15:05:39 +00:00
b0579e9d3f
Simplify binary operations where one operand is a select instruction.
...
The simplifications performed here never create new instructions, they
only return existing instructions (or a constant), and so are always a
win. In theory they should transform (for example)
%z = and i32 %x, %y
%s = select i1 %cond, i32 %y, i32 %z
%r = and i32 %x, %s
into
%r = and i32 %x, y
but in practice they get into a fight with instcombine, and lose.
Unfortunately instcombine does a poor job in this case. Nonetheless
I'm committing this transform to make it easier to discuss what to
do to make peace with instcombine.
llvm-svn: 118679
2010-11-10 13:00:08 +00:00
23ebef1456
Win32/Process.inc: [PR8527] Process::FileDescriptorIsDisplayed(fd) should not check by FILE_TYPE_CHAR. It must be better to check it with Console API.
...
The special file "NUL" is FILE_TYPE_CHAR with GetFileType(h). It was treated as display device and discarding output to NUL had failed. (eg. opt -o nul)
llvm-svn: 118678
2010-11-10 08:37:47 +00:00
f23b2d9d8d
Update ARMConstantPoolValue to not use a modifier string. Use an explicit
...
VariantKind marker to indicate the additional information necessary. Update
MC to handle the new Kinds. rdar://8647623
llvm-svn: 118671
2010-11-10 03:26:07 +00:00
67fc18a493
Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some minor tweaks
...
llvm-svn: 118667
2010-11-10 02:13:22 +00:00
0171dc30ff
When checking that the necessary bits are zero in
...
order to reduce ((x<<30)>>24) to x<<6, check the
correct bits. PR 8547.
llvm-svn: 118665
2010-11-10 01:30:56 +00:00
91607f878c
Emit a '!' if this is a "writeback" register or memory address.
...
llvm-svn: 118662
2010-11-10 01:07:54 +00:00
de5c4dc24b
Simplify the LiveRangeEdit::canRematerializeAt() interface a bit.
...
llvm-svn: 118661
2010-11-10 01:05:12 +00:00
2694e14087
Make ModRefBehavior a lattice. Use this to clean up AliasAnalysis
...
chaining and simplify FunctionAttrs' GetModRefBehavior logic.
llvm-svn: 118660
2010-11-10 01:02:18 +00:00
55c4cc76ce
Rename a parameter to avoid confusion with a local variable
...
llvm-svn: 118656
2010-11-10 00:08:58 +00:00
e9a9c6da04
Emit the warning about the register list not being in ascending order only once.
...
llvm-svn: 118653
2010-11-09 23:45:59 +00:00
9bb44a5ce8
Fixed version of 118639 with an extra assert to catch similar problems
...
earlier. Implicit bool -> int conversions are evil!
llvm-svn: 118651
2010-11-09 23:42:07 +00:00
bed9465a96
s/std::vector/SmallVector/
...
llvm-svn: 118648
2010-11-09 23:28:44 +00:00
33048f069f
Revert previous patch. Missed a case.
...
llvm-svn: 118645
2010-11-09 22:54:38 +00:00
da3c0fbc64
Delete the allocated vector.
...
llvm-svn: 118644
2010-11-09 22:51:42 +00:00
d0046ca62d
Define the subtarget feature for the architecture version,
...
as derived from the target triple. This is important for enabling
features that are implied based on the architecture version.
llvm-svn: 118643
2010-11-09 22:50:47 +00:00
193722ebc8
Do not use MEMBARRIER_MCR for any Thumb code.
...
It is only supported for ARM code. Normally Thumb2 code would use DMB instead,
but depending on how the compiler is invoked (e.g., -mattr=-db) that might be
disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that
situation. Radar 8644195
llvm-svn: 118642
2010-11-09 22:50:44 +00:00
2cae3277a5
Two types of instructions have register lists:
...
* LDM, et al, uses a bit mask to indicate the register list.
* VLDM, et al, uses a base register plus number.
The LDM instructions may be non-contiguous, but the VLDM ones must be
contiguous. Those are semantic checks that should be done later in the
compiler. Also postpone the creation of the bit mask until it's needed.
llvm-svn: 118640
2010-11-09 22:44:22 +00:00
4bdd2724e3
Remove IsExplicit. It was always false.
...
llvm-svn: 118639
2010-11-09 22:37:44 +00:00
a942ad4222
Change the ARMConstantPoolValue modifier string to an enumeration. This will
...
help in MC'izing the references that use them.
llvm-svn: 118633
2010-11-09 21:36:17 +00:00
488660554e
Adds RABasic verification and tracing.
...
(retry now that the windows build is green)
llvm-svn: 118630
2010-11-09 21:04:34 +00:00
e3467a7687
Teach FunctionAttrs about the VAArg instruction.
...
llvm-svn: 118627
2010-11-09 20:17:38 +00:00
35814e6128
Use the AliasAnalysis interface to determine how a Function accesses
...
memory. This isn't a real improvement with present day AliasAnalysis
implementations; it's mainly for consistency.
llvm-svn: 118624
2010-11-09 20:13:27 +00:00
88ff1ece63
VAArg doesn't capture its operand.
...
llvm-svn: 118623
2010-11-09 20:09:35 +00:00
5d06f892ef
Teach AliasAnalysis about AccessesArgumentsReadonly.
...
llvm-svn: 118621
2010-11-09 20:06:55 +00:00
0f17507478
Teach LICM and AliasSetTracker about AccessesArgumentsReadonly.
...
llvm-svn: 118618
2010-11-09 19:58:21 +00:00
de52155685
Teach FunctionAttrs about AccessesArgumentsReadonly.
...
llvm-svn: 118617
2010-11-09 19:56:27 +00:00
7c1fddb531
Add a trivial virtual dtor to AbstractRegisterDescription to appease
...
-Wnon-virtual-dtor.
llvm-svn: 118616
2010-11-09 19:56:25 +00:00
42d50e920b
Reverting r118604. Windows build broke.
...
llvm-svn: 118613
2010-11-09 19:47:51 +00:00
2fd4c37d8b
Handle ARM constant pool values that need an explicit reference to the '.'
...
pseudo-label. (TLS stuff).
llvm-svn: 118609
2010-11-09 19:40:22 +00:00
4d94e47368
add a case we fail to devirt.
...
llvm-svn: 118608
2010-11-09 19:37:28 +00:00
68147ee320
Trailing whitespace.
...
llvm-svn: 118606
2010-11-09 19:22:26 +00:00
85064c17be
Adds RABasic verification and tracing.
...
llvm-svn: 118604
2010-11-09 19:01:17 +00:00
38f8e76e51
Further MCize ARM constant pool values. This allows basic PIC references for
...
object file emission.
llvm-svn: 118601
2010-11-09 18:45:04 +00:00
7e51095c23
Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding.
...
llvm-svn: 118600
2010-11-09 18:43:54 +00:00
91bfeb10b5
Last try to get this reference counting right, I swear.
...
llvm-svn: 118589
2010-11-09 17:47:10 +00:00
2d335436f3
Really fix the leak in the attributes list. Thanks to Benjamin Kramer for pointing out how I was being stupid.
...
llvm-svn: 118588
2010-11-09 17:46:38 +00:00
59002dc973
For ARM load/store instructions, encode [reg+reg] with no shifter immediate as
...
a left shift by zero.
llvm-svn: 118587
2010-11-09 17:38:15 +00:00
9b973490c9
ARM .word data fixups don't need an adjustment.
...
llvm-svn: 118586
2010-11-09 17:36:59 +00:00
fc5ad3f0f9
Factorize code, no functionality change.
...
llvm-svn: 118516
2010-11-09 17:25:51 +00:00
9c5c829d9a
Fix trailing whitespace and style, no functionality change
...
llvm-svn: 118515
2010-11-09 17:25:34 +00:00
dbfb5edbdb
Add encoder method for ARM load/store shifted register offset operands.
...
llvm-svn: 118513
2010-11-09 17:20:53 +00:00
d7e3b54635
System/Path/Windows: Implement GetLLVMDefaultConfigDir.
...
llvm-svn: 118507
2010-11-09 15:11:42 +00:00
86cdb42737
System/Path/Windows: Generalize GetUserHomeDirectory.
...
llvm-svn: 118506
2010-11-09 15:11:31 +00:00
181fd8cd89
System/Path/Windows: Make GetSystemLibraryPaths more generic.
...
llvm-svn: 118505
2010-11-09 15:11:19 +00:00
bb6e51c957
System/Windows: Reduce dependencies.
...
llvm-svn: 118504
2010-11-09 15:11:07 +00:00
8daf3c00c9
System/Windows: Use normalized case and include method.
...
llvm-svn: 118503
2010-11-09 15:10:56 +00:00
df929cf8df
System/Path/Windows: Change GetRootDirectory to return file:/// instead of C:/.
...
llvm-svn: 118502
2010-11-09 15:10:45 +00:00
4b263dddc4
Update comment.
...
llvm-svn: 118501
2010-11-09 15:10:29 +00:00
25e84078e3
Fix leak in my recent fix for PR8442.
...
llvm-svn: 118490
2010-11-09 05:17:47 +00:00
5db8921422
Fix DAGCombiner to avoid folding a sext-in-reg or similar through a shl
...
in order to fold it into a load.
llvm-svn: 118471
2010-11-09 01:54:35 +00:00
9098714f8b
Add support for a few simple fixups to the ARM Darwin asm backend. This allows
...
constant pool references and global variable refernces to resolve properly
for object file generation. For example,
int x;
void foo(unsigned a, unsigned *p) {
p[a] = x;
}
can now be successfully compiled directly to an (ARM mode) object file.
llvm-svn: 118469
2010-11-09 01:37:15 +00:00
f11ea9ce61
Fix an inline asm pasto from 117667; was preventing
...
{i64, i64} from matching i128.
llvm-svn: 118465
2010-11-09 01:15:07 +00:00
1fc8ec1d4b
Fix PR8441, a thread unsafe static variable in our dynamic library loading facilities.
...
llvm-svn: 118463
2010-11-09 00:36:06 +00:00
1b83ed5f7c
Revert r118457 and r118458. These won't hold for GPRs.
...
llvm-svn: 118462
2010-11-09 00:30:18 +00:00
9b14a25126
Fix PR8441, a race condition in the static attributes list. While the reference counting was itself threadsafe,
...
the implicit removal of each object from the global list was not. Make this operation atomic.
llvm-svn: 118461
2010-11-09 00:27:03 +00:00
31b850be15
Get the register and count from the register list operands.
...
llvm-svn: 118458
2010-11-08 23:51:20 +00:00
aeead4d1e1
reglist has two operands.
...
llvm-svn: 118457
2010-11-08 23:50:20 +00:00
8d2aa03ce1
The "addRegListOperands()" function returns the start register and the total
...
number of registers in the list.
llvm-svn: 118456
2010-11-08 23:49:57 +00:00
c7baee31ad
Add support for ARM's specialized vector-compare-against-zero instructions.
...
llvm-svn: 118453
2010-11-08 23:21:22 +00:00
9c656fe815
Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka (ahatanaka@mips.com)
...
llvm-svn: 118447
2010-11-08 21:42:32 +00:00
a91d02bc61
Add "write back" bit encoding.
...
llvm-svn: 118446
2010-11-08 21:28:03 +00:00
69ba1e9ccb
Fix PR8211
...
llvm-svn: 118445
2010-11-08 21:24:59 +00:00
023270e453
Remove contributor names as per coding statndard.
...
llvm-svn: 118442
2010-11-08 20:56:32 +00:00
142ff82a18
Re-introduce the MaxLookup limit to BasicAliasAnalysis'
...
pointsToConstantMemory code to guard against possible
compile time slowdowns.
llvm-svn: 118440
2010-11-08 20:26:19 +00:00
fc82674b9c
Adding working version of assembly parser for the MBlaze backend
...
Major cleanup of whitespace and formatting issues in MBlaze backend
llvm-svn: 118434
2010-11-08 19:40:01 +00:00
470ade12e0
Fix a thinko that Duncan spotted.
...
llvm-svn: 118430
2010-11-08 19:24:47 +00:00
0ef474730f
Revert 118422 in search of bot verdancy.
...
llvm-svn: 118429
2010-11-08 19:17:22 +00:00
3528465232
Adds support for spilling previously allocated live intervals to
...
handle cases in which a register is unavailable for spill code.
Adds LiveIntervalUnion::extract. While processing interferences on a
live virtual register, reuses the same Query object for each
physcial reg.
llvm-svn: 118423
2010-11-08 18:02:08 +00:00
f3e224f830
Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.
...
llvm-svn: 118422
2010-11-08 17:58:07 +00:00
8a3c3f2ad3
Fix typo.
...
llvm-svn: 118421
2010-11-08 17:53:02 +00:00
2cd1fd4a82
Make FunctionAttrs TBAA-aware.
...
llvm-svn: 118417
2010-11-08 17:12:04 +00:00
601c94b309
Implement getModRefBehavior for TypeBasedAliasAnalysis.
...
llvm-svn: 118416
2010-11-08 17:10:22 +00:00
fc6b6bd5a6
Complete listing of ARM/MC/ELF relocation enums
...
llvm-svn: 118413
2010-11-08 16:47:27 +00:00
9130bad71f
Extend the AliasAnalysis::pointsToConstantMemory interface to allow it
...
to optionally look for constant or local (alloca) memory.
Teach BasicAliasAnalysis::pointsToConstantMemory to look through Select
and Phi nodes, and to support looking for local memory.
Remove FunctionAttrs' PointsToLocalOrConstantMemory function, now that
AliasAnalysis knows all the tricks that it knew.
llvm-svn: 118412
2010-11-08 16:45:26 +00:00
0b56778d65
Delete getIntrinsicModRefBehavior. Clients can just use the normal
...
getModRefBehavior now, since it now understands intrinsics as well
as normal functions.
llvm-svn: 118411
2010-11-08 16:11:19 +00:00
86449d705a
Make FunctionAttrs use AliasAnalysis::getModRefBehavior, now that it
...
knows about intrinsic functions.
llvm-svn: 118410
2010-11-08 16:10:15 +00:00
e461d7d135
Teach BasicAliasAnalysis::getModRefBehavior(const Function *F)
...
to analyze intrinsic functions.
llvm-svn: 118409
2010-11-08 16:08:43 +00:00
fab7697e42
Add generating function declaration for PTX
...
llvm-svn: 118398
2010-11-08 03:06:08 +00:00
09bf309527
Add physical register counting functions
...
llvm-svn: 118397
2010-11-08 03:00:52 +00:00
c03ec0cc42
Add a dummy PTXMCAsmStreamer class
...
llvm-svn: 118396
2010-11-08 02:58:44 +00:00
9d17a3194e
Set default flags for .rodata.
...
llvm-svn: 118395
2010-11-08 02:47:59 +00:00
345b98eddd
Add registry hook for assembly text output
...
llvm-svn: 118394
2010-11-08 02:21:17 +00:00
424601a9b3
Make RegList an ASM operand so that TableGen will generate code for it. This is
...
an initial implementation and may change once reglists are fully fleshed out.
llvm-svn: 118390
2010-11-08 00:39:58 +00:00
2f9d17c44f
Revert.
...
llvm-svn: 118389
2010-11-08 00:32:40 +00:00
a620bd1fa3
Add simplification of floating point comparisons with the result
...
of a select instruction, the same as already exists for integer
comparisons.
llvm-svn: 118379
2010-11-07 16:46:25 +00:00
f532d31198
Fix a README item: when doing a comparison with the result
...
of a select instruction, see if doing the compare with the
true and false values of the select gives the same result.
If so, that can be used as the value of the comparison.
llvm-svn: 118378
2010-11-07 16:12:23 +00:00
20b11eaa01
Speed up AddSectionToTheEnd. It was walking all fragments in all sections.
...
This is really slow with we have 1000s of sections each with a corresponding
relocation section. Also, it is only used by the ELF writer to add
basic data, so there is no need to force a new layout pass.
Should fix PR8563.
llvm-svn: 118377
2010-11-07 15:03:27 +00:00
68bac75190
In this context, a reglist is a reg.
...
llvm-svn: 118375
2010-11-07 13:08:28 +00:00
3e100cf582
Fix memory leak in StringRef::edit_distance(). 'Allocated' could be leaked on an early return.
...
llvm-svn: 118370
2010-11-07 06:09:02 +00:00
559b8fbffc
Add method for checking if a path is a symbolic link.
...
llvm-svn: 118367
2010-11-07 04:36:50 +00:00
5665a93bc5
Relax dwarf line fragments. This fixes a crash in the included testcase.
...
llvm-svn: 118365
2010-11-07 02:07:12 +00:00
0530c024b6
implement aliases for div/idiv that have an explicit A register operand,
...
implementing rdar://8431864
llvm-svn: 118364
2010-11-06 22:41:18 +00:00
e18980aeaa
Add support for parsing register lists. We can't use a bitfield to keep track of
...
the registers, because the register numbers may be much greater than the number
of bits available in the machine's register.
I extracted the register list verification code out of the actual parsing of the
registers. This made checking for errors much easier. It also limits the number
of warnings that would be emitted for cascading infractions.
llvm-svn: 118363
2010-11-06 22:36:58 +00:00
9654e108d7
add aliases for movs between seg registers and mem. There are multiple
...
different forms of this instruction (movw/movl/movq) which we reported
as being ambiguous. Since they all do the same thing, gas just picks the
one with the shortest encoding. Follow its lead here.
This implements rdar://8208615
llvm-svn: 118362
2010-11-06 22:35:34 +00:00
7923358842
move the "sh[lr]d op,op" -> "shld $1, op,op" aliases to the .td file.
...
llvm-svn: 118361
2010-11-06 22:25:39 +00:00
b884a8ee44
Return the base register of a register list for the "getReg()" method. This is
...
to satisfy the ClassifyOperand method of the Asm matcher without having to add a
RegList type to every back-end.
llvm-svn: 118360
2010-11-06 22:19:43 +00:00
2abbeded98
work-in-progress
...
llvm-svn: 118358
2010-11-06 22:05:43 +00:00
ee7f1f9914
General cleanup:
...
- Make ARMOperand a class so that some things are internal to the class.
- Reformatting.
llvm-svn: 118357
2010-11-06 21:42:12 +00:00
ca7801e472
go to great lengths to work around a GAS bug my previous patch
...
exposed:
GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)"
even though st(0) is implicit in all other fp stack instructions.
Fortunately, there is an alias for fcomip named "fcompi" and gas does
accept the default argument for the alias (boggle!).
As such, switch the canonical form of this instruction to "pi" instead
of "ip". This makes the code generator and disassembler generate pi,
avoiding the gas bug.
llvm-svn: 118356
2010-11-06 21:37:06 +00:00
64f91b9825
rework the rotate-by-1 instructions to be defined like the
...
shift-by-1 instructions, where the asmstring doesn't contain
the implicit 1. It turns out that a bunch of these rotate
instructions were completely broken because they used 1
instead of $1.
This fixes assembly mismatches on "rclb $1, %bl" and friends,
where we used to generate the 3 byte form, we now generate the
proper 2-byte form.
llvm-svn: 118355
2010-11-06 21:23:40 +00:00
05031e7f1a
change the fp comparison instructions to not have %st0 explicitly
...
listed in its asm string, for consistency with the other similar
instructions.
llvm-svn: 118354
2010-11-06 20:55:09 +00:00
290199f8ee
move the plethora of fp stack aliases to the .td file.
...
llvm-svn: 118353
2010-11-06 20:47:38 +00:00
4869d346e3
add (and document) the ability for alias results to have
...
fixed physical registers. Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).
llvm-svn: 118352
2010-11-06 19:57:21 +00:00
7cef447c14
Add a RegList (register list) object to ARMOperand. It will be used soon to hold
...
(surprise!) a list of registers. Register lists are consecutive, so we only need
to record the start register plus the number of registers.
llvm-svn: 118351
2010-11-06 19:56:04 +00:00
b6f8e8248d
generalize alias support to allow the result of an alias to
...
add fixed immediate values. Move the aad and aam aliases to
use this, and document it.
llvm-svn: 118350
2010-11-06 19:25:43 +00:00
161bf7de25
move fnstsw aliases to .td file, fix typo
...
llvm-svn: 118349
2010-11-06 18:58:32 +00:00
ec66010e80
move in/out aliases to the .td files.
...
llvm-svn: 118348
2010-11-06 18:52:40 +00:00
6881e175c3
move sldt, imul, and movabsq aliases from c++ to .td file.
...
llvm-svn: 118347
2010-11-06 18:44:26 +00:00
fab9413b01
correct suffix matching to search for s/l/t suffixes on
...
floating point stack instructions instead of looking for b/w/l/q.
This fixes issues where we'd accidentally match fistp to fistpl,
when it is in fact an ambiguous instruction.
This changes the behavior of llvm-mc to reject fstp, which was the
correct fix for rdar://8456389:
t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt')
fstp (%rax)
it also causes us to correctly reject fistp and fist, which addresses
PR8528:
t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl')
fistp (%rax)
^
t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl')
fist (%rax)
^
Thanks to Ismail Donmez for tracking down the issue here!
llvm-svn: 118346
2010-11-06 18:28:02 +00:00
63abc84630
Prune includes.
...
llvm-svn: 118342
2010-11-06 11:45:59 +00:00
8300d834c9
Fix grammar.
...
llvm-svn: 118341
2010-11-06 10:51:53 +00:00
4f4bce0682
Fix grammar.
...
llvm-svn: 118340
2010-11-06 10:48:18 +00:00
518e43c453
MatchRegisterName() returns 0 if it can't match the register.
...
llvm-svn: 118339
2010-11-06 10:45:34 +00:00
6d2eb737af
Use TryParseRegister() instead of MatchRegisterName(). The former returns -1
...
while the latter doesn't.
llvm-svn: 118338
2010-11-06 10:40:24 +00:00
8628e2a19c
Add a note.
...
llvm-svn: 118337
2010-11-06 10:37:16 +00:00
db6f90c61c
fix a bug where we had an implicit assumption that the
...
result instruction operand numbering matched the result pattern.
Fixing this allows us to move the xchg/test aliases to the .td file.
llvm-svn: 118334
2010-11-06 08:20:59 +00:00
89965d7091
Make sure we have movw on the target before using it.
...
Fixes 8559.
llvm-svn: 118333
2010-11-06 07:53:11 +00:00
aa7847df06
move the lcall/ljmp aliases to the .td file.
...
llvm-svn: 118332
2010-11-06 07:48:45 +00:00
9535f90abe
move the "movsd -> movsl" alias to the .td files,
...
tidy up the movsx and movzx aliases.
llvm-svn: 118331
2010-11-06 07:34:58 +00:00
8188fb264f
fix some bugs in the alias support, unblocking changing of "clr" aliases
...
from c++ hacks to proper .td InstAlias definitions. Change them!
llvm-svn: 118330
2010-11-06 07:31:43 +00:00
fecdad6237
Reimplement BuildResultOperands to be in terms of the result instruction's
...
operand list instead of the operand list redundantly declared on the alias
or instruction.
With this change, we finally remove the ins/outs list on the alias. Before:
def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
def : InstAlias<"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.
llvm-svn: 118329
2010-11-06 07:14:44 +00:00
2db0ea03ba
Hook up the '.code {16|32}' directive to the streamer.
...
llvm-svn: 118310
2010-11-05 22:40:53 +00:00
cbdf7efe1c
Add '.code 32' assembler directive to MC streamers.
...
llvm-svn: 118309
2010-11-05 22:40:09 +00:00
c6db8ce5da
Hook up the '.thumb_func' directive to the streamer.
...
llvm-svn: 118307
2010-11-05 22:33:53 +00:00
0fe92e3fea
Fix past-o.
...
llvm-svn: 118304
2010-11-05 22:11:33 +00:00
5a2c68d308
MC'ize the '.code 16' and '.thumb_func' ARM directives.
...
llvm-svn: 118301
2010-11-05 22:08:08 +00:00
a4076924d1
Disallow the certain NEON modified-immediate forms when generating vorr or vbic.
...
llvm-svn: 118300
2010-11-05 21:57:54 +00:00
ff9e507d8e
MC'ize simple ARMConstantValue entry emission (with a FIXME).
...
llvm-svn: 118295
2010-11-05 20:34:24 +00:00
80bb80f5fc
Put class into an anonymous namespace.
...
llvm-svn: 118294
2010-11-05 19:56:38 +00:00
30c4892ea5
Add codegen and encoding support for the immediate form of vbic.
...
llvm-svn: 118291
2010-11-05 19:27:46 +00:00
2bab7570f5
Enable MachO writing for ARM/Darwin. Lots of stuff still doesn't work
...
(relocations, e.g.), but this will allow simple things to flow through.
llvm-svn: 118289
2010-11-05 18:50:35 +00:00
46c2acbcb4
Allow targets to specify the MachO CPUType/CPUSubtype information.
...
llvm-svn: 118288
2010-11-05 18:48:58 +00:00
c75bb744e1
syntaxunified directive is a no-op for MachO writing.
...
llvm-svn: 118287
2010-11-05 18:47:32 +00:00
1df82e67d1
Add FIXME.
...
llvm-svn: 118280
2010-11-05 17:37:13 +00:00
6c25ca4f2b
When passing a parameter using the 'byval' mechanism, inline code needs to be used
...
to perform the copy, which may be of lots of memory [*]. It would be good if the
fall-back code generated something reasonable, i.e. did the copy in a loop, rather
than vast numbers of loads and stores. Add a note about this. Currently target
specific code seems to always kick in so this is more of a theoretical issue rather
than a practical one now that X86 has been fixed.
[*] It's amazing how often people pass mega-byte long arrays by copy...
llvm-svn: 118275
2010-11-05 15:20:29 +00:00
f4d90ba9f5
CrashRecoveryContext: Add RunSafelyOnThread helper function.
...
llvm-svn: 118272
2010-11-05 07:19:09 +00:00
98512315f7
When passing a huge parameter using the byval mechanism, a long
...
sequence of loads and stores was being generated to perform the
copy on the x86 targets if the parameter was less than 4 byte
aligned, causing llc to use up vast amounts of memory and time.
Use a "rep movs" form instead. PR7170.
llvm-svn: 118260
2010-11-04 21:16:46 +00:00
ed8b7bf9ed
Use arrays instead of constant-sized SmallVectors.
...
llvm-svn: 118257
2010-11-04 18:45:27 +00:00
38d0756b88
Add 118023 back, but with proper spelling for .uleb128/.sleb128.
...
llvm-svn: 118254
2010-11-04 18:17:08 +00:00
bbc0ac2236
Revert previous patch. Some targets don't support uleb and say
...
they do :-(
llvm-svn: 118250
2010-11-04 17:04:24 +00:00
cfd6243940
MCize.
...
llvm-svn: 118249
2010-11-04 16:32:18 +00:00
57c5a20364
Introduce DIBuilder. It is intended to be a front-end friendly interface to emit debuggging information entries in LLVM IR.
...
To create debugging information for a pointer, using DIBUilder front-end just needs
DBuilder.CreatePointerType(Ty, Size);
instead of
DebugFactory.CreateDerivedType(llvm::dwarf::DW_TAG_pointer_type,
TheCU, "", getOrCreateMainFile(),
0, Size, 0, 0, 0, OCTy);
llvm-svn: 118248
2010-11-04 15:01:38 +00:00
71049f78ed
In the calling convention logic, ValVT is always a legal type,
...
and as such can be represented by an MVT - the more complicated
EVT is not needed. Use MVT for ValVT everywhere.
llvm-svn: 118245
2010-11-04 10:49:57 +00:00
21acf9fb38
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.
...
llvm-svn: 118237
2010-11-04 05:19:35 +00:00
cdd4c5443e
System: Add llvm_execute_on_thread, which does what it says.
...
- Primarily useful for running some code with a specified stack size, when
pthreads are available.
llvm-svn: 118222
2010-11-04 01:26:25 +00:00
0fb841fd19
Add ARM fixup info for load/store label references. Probably will need a bit of
...
tweaking when we start using it for object file emission or JIT, but it's a
start.
llvm-svn: 118221
2010-11-04 01:12:30 +00:00
c002463ac4
Add encoding for VSTR.
...
llvm-svn: 118220
2010-11-04 00:59:42 +00:00
a2e098df12
Disable fancy splitting during spilling unless -extra-spiller-splits is given.
...
This way, InlineSpiller does the same amount of splitting as the standard
spiller. Splitting should really be guided by the register allocator, and
doesn't belong in the spiller at all.
llvm-svn: 118216
2010-11-04 00:32:32 +00:00
2eed7a1310
Teach ARM Target to use the tblgen support for generating an MC'ized
...
CodeEmitter.
llvm-svn: 118209
2010-11-03 23:52:49 +00:00
bc9b31c493
Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization.
...
This is both the conceptually correct place for it, as well as allowing it to be more aggressive.
llvm-svn: 118204
2010-11-03 23:15:26 +00:00
0747307049
Add support for code generation of the one register with immediate form of vorr.
...
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.
llvm-svn: 118201
2010-11-03 22:44:51 +00:00
49b0c45ecf
trailing whitespace
...
llvm-svn: 118199
2010-11-03 22:03:20 +00:00
c6418b105a
Just return undef for invalid masks or elts, and since we're doing that,
...
just do it earlier too.
llvm-svn: 118195
2010-11-03 20:44:42 +00:00
c913201259
Let RegAllocBasic require MachineDominators - they are already available and
...
splitting needs them.
llvm-svn: 118194
2010-11-03 20:39:26 +00:00
cbbd819248
Tag debug output as regalloc
...
llvm-svn: 118193
2010-11-03 20:39:23 +00:00
e4dd7378d0
Optimize generated code for integer materialization a bit.
...
llvm-svn: 118192
2010-11-03 20:21:17 +00:00
bb81f80af6
Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead,
...
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.
llvm-svn: 118183
2010-11-03 18:16:27 +00:00
7d0ac84abd
Add codegen patterns for VST1-lane instructions. Radar 8599955.
...
llvm-svn: 118176
2010-11-03 16:24:53 +00:00
ceb49296ef
Check for extractelement with a variable operand for the element number.
...
For NEON we had been assuming this was always an immediate constant.
llvm-svn: 118175
2010-11-03 16:24:50 +00:00
b8211b80bc
Rename FindExecutable to PrependMainExecutablePath.
...
Makes it more clear that it is just a path manipulation function.
llvm-svn: 118174
2010-11-03 16:14:16 +00:00
9d1fe4c40d
Rename PointsToLocalMemory to PointsToLocalOrConstantMemory to make
...
the code more self-documenting.
llvm-svn: 118171
2010-11-03 14:45:05 +00:00
1462777017
Simplify uses of MVT and EVT. An MVT can be compared directly
...
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.
llvm-svn: 118169
2010-11-03 12:17:33 +00:00
f5dda01f33
Inside the calling convention logic LocVT is always a simple
...
value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
llvm-svn: 118167
2010-11-03 11:35:31 +00:00
fcc9e6848a
If we have an undef mask our Elt will be -1 for our access, handle
...
this by using an undef as a pointer.
Fixes rdar://8625016
llvm-svn: 118164
2010-11-03 09:36:40 +00:00
8740ee3637
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
...
llvm-svn: 118160
2010-11-03 06:34:55 +00:00
6f36042557
Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
...
llvm-svn: 118152
2010-11-03 05:14:24 +00:00
6552a109bb
Put the PC encoding in the correct bit position.
...
llvm-svn: 118151
2010-11-03 04:57:44 +00:00
c63d846ad6
Invert these branches by default, it makes assembly comparisons a little
...
easier to read.
llvm-svn: 118148
2010-11-03 04:29:11 +00:00
e84eb99cbb
The MC code couldn't handle ARM LDR instructions with negative offsets:
...
vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
llvm-svn: 118144
2010-11-03 01:49:29 +00:00
68fb004616
Fix DAGCombiner to avoid going into an infinite loop when it
...
encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff).
This fixes rdar://8606584.
llvm-svn: 118143
2010-11-03 01:47:46 +00:00
fd96701456
Remove unused function.
...
llvm-svn: 118141
2010-11-03 01:35:15 +00:00
e7f7de95e0
Remove the no longer used 'Modifier' optional operand to the ARM
...
printOperand() asm printer helper functions. rdar://8425198
llvm-svn: 118140
2010-11-03 01:11:15 +00:00
50ba3c09bf
Remove unused function.
...
llvm-svn: 118139
2010-11-03 01:07:48 +00:00
c6af2b4066
Break ARM addrmode4 (load/store multiple base address) into its constituent
...
parts. Represent the operation mode as an optional operand instead.
rdar://8614429
llvm-svn: 118137
2010-11-03 01:01:43 +00:00
debf9c502a
Two sets of changes. Sorry they are intermingled.
...
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
"optimize for latency". Call instructions don't have the right latency and
this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
not # of micro-ops since multi-latency instructions is completely executed
even when the predicate is false. Also, some instruction will be "slower"
when they are predicated due to the register def becoming implicit input.
rdar://8598427
llvm-svn: 118135
2010-11-03 00:45:17 +00:00
634ab6c2b7
Modify scheduling itineraries to correct instruction latencies (not operand
...
latencies) of loads.
llvm-svn: 118134
2010-11-03 00:40:22 +00:00
0baea2aa1b
Print an error as one big string instead of breaking it up.
...
llvm-svn: 118130
2010-11-03 00:24:33 +00:00
a3bb142db6
Delete unused variables.
...
llvm-svn: 118128
2010-11-03 00:09:12 +00:00
ecc4d73498
Remove several unhelpful checks for isValid from sys::Path.
...
llvm-svn: 118127
2010-11-03 00:01:23 +00:00
1e43892e4b
Make sure we're only storing a single bit here.
...
llvm-svn: 118126
2010-11-02 23:59:09 +00:00
9c9bfb6870
per a suggestion by Frits van Bommel, mark all MBlaze Pseudo
...
instructions as isCodeGenOnly in the parent class instead of
sprinkling it throughout the .td files.
llvm-svn: 118125
2010-11-02 23:57:05 +00:00
0ebd1fd594
Revert r118097 to fix buildbots.
...
llvm-svn: 118121
2010-11-02 23:47:29 +00:00
cc5dce89d4
Completely reject instructions that have an operand in their
...
ins/outs list that isn't specified by their asmstring. Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right. Mark a bunch of ARM instructions that use this as
isCodeGenOnly. Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).
llvm-svn: 118119
2010-11-02 23:40:41 +00:00
31a7eb40c1
Let the -inline-threshold command line argument take precedence over the
...
threshold given to createFunctionInliningPass().
Both opt -O3 and clang would silently ignore the -inline-threshold option.
llvm-svn: 118117
2010-11-02 23:40:26 +00:00
c0a8bee4b0
Don't try to enforce MAXPATHLEN in sys::Path for Unix. OS's can check
...
limits on their own.
llvm-svn: 118113
2010-11-02 23:19:55 +00:00
a8b6315cd7
Simplify.
...
llvm-svn: 118110
2010-11-02 23:16:26 +00:00
6e05d6c218
Fix a copy+pasto.
...
llvm-svn: 118106
2010-11-02 22:56:51 +00:00
a47bfef1bf
Avoid manipulating paths in fixed-sized arrays.
...
llvm-svn: 118105
2010-11-02 22:55:34 +00:00
f9eebb58b9
Obsessive formatting changes. No functionality impact.
...
llvm-svn: 118103
2010-11-02 22:53:11 +00:00
32d51fa0b5
Simplify this code.
...
llvm-svn: 118102
2010-11-02 22:50:10 +00:00
23436b6530
Omit unused parameter name.
...
llvm-svn: 118099
2010-11-02 22:46:04 +00:00
91da9abbee
Simplify the EncodeInstruction method now that a lot of the special case stuff
...
is handled with the MC encoder.
llvm-svn: 118098
2010-11-02 22:44:12 +00:00
7c30390277
Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning.
...
llvm-svn: 118097
2010-11-02 22:41:42 +00:00
f6e13ceb2b
Use '\0' instead of 0 for nul character constants.
...
llvm-svn: 118096
2010-11-02 22:41:19 +00:00
603bd8f54c
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
...
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.
llvm-svn: 118094
2010-11-02 22:31:46 +00:00
a4b63e19d2
Rename encoder methods to match naming convention.
...
llvm-svn: 118093
2010-11-02 22:28:01 +00:00
15977afb02
mark a few codegenonly instructions.
...
llvm-svn: 118092
2010-11-02 22:26:33 +00:00
7282901079
appendSuffix: don't append a dot when the suffix is empty.
...
Additionally, move the implementation of appendSuffix to Path.cpp: it is
platform-independent.
llvm-svn: 118089
2010-11-02 22:18:37 +00:00
4fb337560c
Revert r118057, this is better fixed in appendSuffix itself.
...
llvm-svn: 118088
2010-11-02 22:18:28 +00:00
dec87e10fd
Provide correct encodings for the remaining vst variants that we currently generate.
...
llvm-svn: 118087
2010-11-02 22:18:18 +00:00
44e24e5403
Eliminate some temporary std::strings.
...
llvm-svn: 118086
2010-11-02 22:07:47 +00:00
adf88d4c5f
Tentative encodings for the "single element from one lane" variant of vst1.
...
llvm-svn: 118084
2010-11-02 21:54:45 +00:00
b95618cfe0
Add correct encodings for basic variants for vst3 and vst4.
...
llvm-svn: 118082
2010-11-02 21:47:03 +00:00
f8343f87e7
Do relaxations with FT_Org fragments. Fixes the FIXME:
...
// FIXME: We should compute this sooner, we don't want to recurse here, and
// we would like to be more functional.
In MCAssembler::ComputeFragmentSize.
llvm-svn: 118080
2010-11-02 21:38:23 +00:00
d80b29d6f7
Add NEON VST1-lane instructions. Partial fix for Radar 8599955.
...
llvm-svn: 118069
2010-11-02 21:18:25 +00:00
fa08e1e277
Add correct encodings for the basic variants for vst2.
...
llvm-svn: 118068
2010-11-02 21:16:58 +00:00
87c62e54e6
Add correct encodings for the basic form of vst1.
...
llvm-svn: 118067
2010-11-02 21:06:06 +00:00
bba85850e3
Micro-optimize.
...
llvm-svn: 118058
2010-11-02 20:52:47 +00:00
35b2013bf8
Don't append a dot on platforms which don't use exe suffixes.
...
llvm-svn: 118057
2010-11-02 20:49:48 +00:00
0ddd57451e
llvmc: Fix tool finding logic.
...
llvm-svn: 118056
2010-11-02 20:47:41 +00:00
9f20daf3b4
Factor out a common encoding class for loads and stores with a lane parameter.
...
llvm-svn: 118055
2010-11-02 20:47:39 +00:00
415c551459
Fix DIType verifier. The element 3 is DIFile now.
...
llvm-svn: 118054
2010-11-02 20:41:13 +00:00
a83859539f
Add correct encodings for the rest of the vld instructions that we generate.
...
llvm-svn: 118053
2010-11-02 20:40:59 +00:00
2c3991acf3
GetDLLSuffix: Remove the leading dot from LTDL_SHLIB_EXT.
...
This allows using GetDLLSuffix() with appendSuffix().
llvm-svn: 118051
2010-11-02 20:32:59 +00:00
f26f4a0535
Trailing whitespace.
...
llvm-svn: 118050
2010-11-02 20:32:52 +00:00
82ee8dad50
FindExecutable: remove the executability check.
...
This makes the behaviour of FindExecutable more consistent across platforms, but
I'm not very happy with the name...
llvm-svn: 118049
2010-11-02 20:32:46 +00:00
a581d8a27a
Make FindProgramByName return paths with slashes unmodified on Windows.
...
This makes its behaviour more consistent across platforms.
llvm-svn: 118048
2010-11-02 20:32:39 +00:00
b4921a035e
80-col violations.
...
llvm-svn: 118045
2010-11-02 20:32:31 +00:00
fcfaf51e52
Path: Add GetEXESuffix() to complement GetDLLSuffix().
...
llvm-svn: 118042
2010-11-02 20:32:26 +00:00
82ae9a95a5
Fixes <rdar://problem/8612856>: During postRAsched, the antidependence
...
breaker needs to check all definitions of the antidepenent register to
avoid multiple defs of the same new register.
llvm-svn: 118032
2010-11-02 18:16:45 +00:00
e81d45d2cc
Apply patch for use-after-free in InlineAsm constant handling,
...
PR 8522 / 8616046. Test reduction, analysis and patch by Tim Deegan!
(However, review by someone who understands the classes here better
is welcome. John Krum will return!)
llvm-svn: 118030
2010-11-02 17:59:27 +00:00
93a4d44ee6
Sort bit assignments. Cosmetic change only.
...
llvm-svn: 118029
2010-11-02 17:59:04 +00:00
e755966913
Simplify.
...
llvm-svn: 118027
2010-11-02 17:37:00 +00:00
0b7fda23cc
Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke
...
assumptions about stack layout. Specifically, LR must be saved next to FP.
llvm-svn: 118026
2010-11-02 17:35:25 +00:00
5e874982f2
Add support for expressions in .sleb/.uleb directives.
...
llvm-svn: 118023
2010-11-02 17:22:24 +00:00
bc741405a7
If value map does not have register for an argument then try to find frame index before giving up.
...
llvm-svn: 118022
2010-11-02 17:19:03 +00:00
94f2a2578c
Use frameindex, if available, as a last resort to emit debug info for a parameter.
...
llvm-svn: 118020
2010-11-02 17:01:30 +00:00
526ffd57d2
Add correct NEON encodings for vld2, vld3, and vld4 basic variants.
...
llvm-svn: 117997
2010-11-02 01:24:55 +00:00
b2abb508ae
Remove an assert - it's possible to be hit, and we just want to avoid
...
handling those cases for now.
llvm-svn: 117996
2010-11-02 01:24:49 +00:00
ac746e1b38
Whitespeace
...
llvm-svn: 117995
2010-11-02 01:22:45 +00:00
e8fccc82e4
No really, no thumb1 for arm fast isel. Also add an informative comment as
...
to what someone would need to do to support thumb1.
llvm-svn: 117994
2010-11-02 01:21:28 +00:00
ea26319185
Don't try to split weird critical edges that really aren't:
...
BB#1: derived from LLVM BB %bb.nph28
Live Ins: %AL
Predecessors according to CFG: BB#0
TEST8rr %reg16384<kill>, %reg16384, %EFLAGS<imp-def>; GR8:%reg16384
JNE_4 <BB#2>, %EFLAGS<imp-use,kill>
JMP_4 <BB#2>
Successors according to CFG: BB#2 BB#2
These double CFG edges only ever occur in bugpoint-generated code, so there is
no need to attempt something clever.
llvm-svn: 117992
2010-11-02 00:58:37 +00:00
b3ca2060c0
Attempt to provide correct encodings for a number of other vld1 variants, which we can't test
...
since we can neither generate nor parse them at the moment.
llvm-svn: 117988
2010-11-02 00:24:52 +00:00
f1610f7910
Add aesthetic break.
...
llvm-svn: 117986
2010-11-02 00:14:00 +00:00
ad40234eff
Add correct NEON encodings for the "multiple single elements" form of vld.
...
llvm-svn: 117984
2010-11-02 00:05:05 +00:00
5c86d22e67
MachineLICM should not claim to be preserving the CFG when it can split critical
...
edges on demand.
llvm-svn: 117982
2010-11-01 23:59:55 +00:00
2551f13c83
Be more precise about verifying missing kill flags.
...
It is legal for an instruction to have two operands using the same register,
only one a kill. This is interpreted as a kill.
llvm-svn: 117981
2010-11-01 23:59:53 +00:00
1e32688e4c
When inserting copies during splitting, always use the parent register as the
...
source, and let rewrite() clean it up.
This way, kill flags on the inserted copies are fixed as well during rewrite().
We can't just assume that all the copies we insert are going to be kills since
critical edges into loop headers sometimes require both source and dest to be
live out of a block.
llvm-svn: 117980
2010-11-01 23:59:48 +00:00
2ba03aa618
Explicitly check for non-consant reference in an LDRi12 instruction. Add FIXME
...
for handling the fixup necessary.
llvm-svn: 117978
2010-11-01 23:45:50 +00:00
a3efae35f5
Remove unused function.
...
llvm-svn: 117977
2010-11-01 23:40:56 +00:00
dd9fbaa9c0
Add support for alignment operands on VLD1-lane instructions.
...
This is another part of the fix for Radar 8599955.
llvm-svn: 117976
2010-11-01 23:40:51 +00:00
3f37ade36e
Missed reverting this bit.
...
llvm-svn: 117971
2010-11-01 23:17:54 +00:00
f7e176a3ec
Minor cleanup.
...
llvm-svn: 117969
2010-11-01 23:11:22 +00:00
60d555c178
rearrange a bit.
...
llvm-svn: 117967
2010-11-01 23:07:52 +00:00
dc44990c7d
Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.
...
llvm-svn: 117964
2010-11-01 22:04:05 +00:00
d7a824006e
Add kill flag verification.
...
At least X86FloatingPoint requires correct kill flags after register allocation,
and targets using register scavenging benefit. Conservative kill flags are not
enough.
llvm-svn: 117960
2010-11-01 21:51:31 +00:00
a5d4b4ffa2
Update kill flags while rewriting instructions after splitting.
...
llvm-svn: 117959
2010-11-01 21:51:29 +00:00
418bd53008
Move the machine operand MC encoding patterns to the parent classes.
...
llvm-svn: 117956
2010-11-01 21:17:06 +00:00
6186c96765
When folding away a (shl (shr)) pair, we need to check that the bits that will BECOME the low
...
bits are zero, not that the current low bits are zero. Fixes <rdar://problem/8606771>.
llvm-svn: 117953
2010-11-01 21:08:20 +00:00
865dd96f22
use our fancy new MnemonicAlias mechanism to remove a bunch of hacks
...
from X86AsmParser.cpp
llvm-svn: 117952
2010-11-01 21:06:34 +00:00
c6627eec13
When we look at instructions to convert to setting the 's' flag, we need to look
...
at more than those which define CPSR. You can have this situation:
(1) subs ...
(2) sub r6, r5, r4
(3) movge ...
(4) cmp r6, 0
(5) movge ...
We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:
(1) sub r1, r2, r3
(2) sub r4, r5, r6
(3) cmp r4, ...
(5) movge ...
(6) cmp r1, ...
(7) movge ...
We cannot convert (1) to "subs" because of the intervening use of CPSR.
llvm-svn: 117950
2010-11-01 20:41:43 +00:00
ba9a4985a2
Don't assign new registers created during a split to the same stack slot, but
...
give them individual stack slots once the are actually spilled.
llvm-svn: 117945
2010-11-01 19:49:57 +00:00
31fffb62d9
Add basic LiveStacks verification.
...
When an instruction refers to a spill slot with a LiveStacks entry, check that
the spill slot is live at the instruction.
llvm-svn: 117944
2010-11-01 19:49:52 +00:00
44be217af1
NEON does not support truncating vector stores. Radar 8598391.
...
llvm-svn: 117940
2010-11-01 18:31:39 +00:00
7d45c101e5
Add FIXME.
...
llvm-svn: 117936
2010-11-01 18:11:14 +00:00
fddf36d254
Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates
...
codegen using the patterns; the latter gates the assembler recognizing the
instruction.
llvm-svn: 117931
2010-11-01 17:08:58 +00:00
13ddd6d410
Write the line info to .debug_line.
...
llvm-svn: 117930
2010-11-01 17:07:14 +00:00
0190a649e8
Mark ARM subtarget features that are available for the assembler.
...
llvm-svn: 117929
2010-11-01 16:59:54 +00:00
99710a871c
trailing whitespace
...
llvm-svn: 117927
2010-11-01 16:44:21 +00:00
72b5488680
Move EmitInstruction to MCObjectStreamer so that ELF and MachO can share it.
...
llvm-svn: 117925
2010-11-01 16:27:31 +00:00
5b373341fc
The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the
...
patterns as such
llvm-svn: 117923
2010-11-01 15:59:52 +00:00
144fb8af58
Add support for .value.
...
llvm-svn: 117922
2010-11-01 15:29:07 +00:00
1614597873
Implement .weakref.
...
llvm-svn: 117911
2010-11-01 14:28:48 +00:00
2623343625
Move instruction encoding bits into the parent class and remove the temporary
...
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.
llvm-svn: 117906
2010-11-01 06:00:39 +00:00
7a23c1fb7d
The testcase is now XFAILed. Sorry about the breakage.
...
llvm-svn: 117904
2010-11-01 05:50:55 +00:00
1acd6b1edc
"mov[zs]x (mem), GR16" are not ambiguous: the mem
...
must be 8 bits. Support this memory form.
llvm-svn: 117902
2010-11-01 05:41:10 +00:00
dd3b09c234
Implement enough of the missing instalias support to get
...
aliases installed and working. They now work when the
matched pattern and the result instruction have exactly
the same operand list.
This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.
Note that we do not accept instructions like:
movzx 0(%rsp), %rsi
GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand. It could be 8/16/32 bits.
llvm-svn: 117901
2010-11-01 05:34:34 +00:00
178f4bb62d
make the asm matcher emitter reject instructions that have comments
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in their asmstring. Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.
llvm-svn: 117897
2010-11-01 04:44:29 +00:00
941c19b7ba
reject instructions that contain a \n in their asmstring. Mark
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various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.
llvm-svn: 117884
2010-11-01 00:46:16 +00:00
ef5a1c3ec3
Revert r117876 for now, it's causing more testsuite failures.
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llvm-svn: 117879
2010-10-31 22:42:55 +00:00
0392f1b437
Disable the peephole optimizer until 186.crafty on armv6 is fixed. This is what
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looks like is happening:
Without the peephole optimizer:
(1) sub r6, r6, #32
orr r12, r12, lr, lsl r9
orr r2, r2, r3, lsl r10
(x) cmp r6, #0
ldr r9, LCPI2_10
ldr r10, LCPI2_11
(2) sub r8, r8, #32
(a) movge r12, lr, lsr r6
(y) cmp r8, #0
LPC2_10:
ldr lr, [pc, r10]
(b) movge r2, r3, lsr r8
With the peephole optimizer:
ldr r9, LCPI2_10
ldr r10, LCPI2_11
(1*) subs r6, r6, #32
(2*) subs r8, r8, #32
(a*) movge r12, lr, lsr r6
(b*) movge r2, r3, lsr r8
(1) is used by (x) for the conditional move at (a). (2) is used by (y) for the
conditional move at (b). After the peephole optimizer, these the flags resulting
from (1*) are ignored and only the flags from (2*) are considered for both
conditional moves.
llvm-svn: 117876
2010-10-31 22:07:12 +00:00
3dbe6cc155
Attach a GCModuleInfo to a MachineFunction.
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llvm-svn: 117867
2010-10-31 20:38:38 +00:00
7ff334687d
fix the !eq operator in tblgen to return a bit instead of an int.
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Use this to make the X86 and ARM targets set isCodeGenOnly=1
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.
llvm-svn: 117862
2010-10-31 19:22:57 +00:00
9492c17baf
two changes: make the asmmatcher generator ignore ARM pseudos properly,
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and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.
llvm-svn: 117861
2010-10-31 19:15:18 +00:00
33fc3e095b
reapply r117858 with apparent editor malfunction fixed (somehow I
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got a dulicated line).
llvm-svn: 117860
2010-10-31 19:10:56 +00:00
e59eef3dd1
revert r117858 while I check out a failure I missed.
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llvm-svn: 117859
2010-10-31 19:05:32 +00:00
9293008e90
the asm matcher can't handle operands with modifiers (like ${foo:bar}).
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Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the
instruction 'isCodeGenOnly'.
Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are
doing this.
llvm-svn: 117858
2010-10-31 18:48:12 +00:00
eb8c0fc2eb
sketch out the planned instruction alias mechanism, add some comments about
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how the push/pop mnemonic aliases are wrong.
llvm-svn: 117857
2010-10-31 18:43:46 +00:00
fb0a48ef96
Factorize the duplicated logic for choosing the right argument
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calling convention out of the fast and normal ISel files, and
into the calling convention TD file.
llvm-svn: 117856
2010-10-31 13:21:44 +00:00
fa7e6f2417
Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86,
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which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.
llvm-svn: 117855
2010-10-31 13:02:38 +00:00
3fe87a1eed
Add support for files with more than 65280 sections. No testcase since
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it would be a bit too big :-)
llvm-svn: 117849
2010-10-31 00:16:26 +00:00
04b0a3e651
Make sure we have a legal type (and simple) before continuing.
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llvm-svn: 117848
2010-10-30 21:25:26 +00:00
Owen Anderson