5 Commits

Author	SHA1	Message	Date
Bob Wilson	c7334a146e	SelectionDAG shuffle nodes do not allow operands with different numbers of ... elements than the result vector type. So, when an instruction like: %8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2> is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is: shuffle [a,b], [c,d] is changed to: shuffle [a,b,u,u], [c,d,u,u] That's probably the right thing for x86 but for NEON, we'd much rather have: shuffle [a,b,c,d], undef Teach the DAG combiner how to do that transformation for ARM. Radar 8597007. llvm-svn: 117482	2010-10-27 20:38:28 +00:00
Bob Wilson	411dfad981	Allow more cases of undef shuffle indices and add tests for them. ... llvm-svn: 111226	2010-08-17 05:54:34 +00:00
Rafael Espindola	29dda21e96	Remove arm_apcscc from the test files. It is the default and doing this ... matches what llvm-gcc and clang now produce. llvm-svn: 106221	2010-06-17 15:18:27 +00:00
Dan Gohman	c8054d90fb	Eliminate more uses of llvm-as and llvm-dis. ... llvm-svn: 81293	2009-09-09 00:09:15 +00:00
Bob Wilson	8a37bbebfd	Add support for ARM Neon VREV instructions. ... Patch by Anton Korzh, with some modifications from me. llvm-svn: 77101	2009-07-26 00:39:34 +00:00