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6 Commits

Author SHA1 Message Date
Evan Cheng cc2efe11db Fix some latency computation bugs: if the use is not a machine opcode do not just return zero. 
llvm-svn: 105061
 2010-05-28 23:26:21 +00:00
Dale Johannesen cee887425e Make g5 target explicit; scheduling affects register choice. 
llvm-svn: 96413
 2010-02-16 23:25:23 +00:00
Dale Johannesen 0062f7bf59 Adjust register numbers in tests to compensate for the 
new lack of R2.

llvm-svn: 96407
 2010-02-16 22:31:31 +00:00
Dan Gohman c8054d90fb Eliminate more uses of llvm-as and llvm-dis. 
llvm-svn: 81293
 2009-09-09 00:09:15 +00:00
Dale Johannesen f582ac7c11 Alter 79292 to produce output that actually assembles. 
llvm-svn: 80119
 2009-08-26 18:10:32 +00:00
Dale Johannesen 4a50e68b65 PowerPC inline asm was emitting two output operands 
for a single "m" constraint; this is wrong because the
opcode of a load or store would have to change in parallel.
This patch makes it always compute addresses into a register,
which is correct but not as efficient as possible.  7144566.

llvm-svn: 79292
 2009-08-18 00:18:39 +00:00