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183 Commits

Author SHA1 Message Date
Bob Wilson fa27a8621c Add Neon VCVT instructions for f32 <-> f16 conversions. 
Clang is now providing intrinsics for these and so we need to support them
in the backend.  Radar 8068427.

llvm-svn: 121902
 2010-12-15 22:14:12 +00:00
Bob Wilson c3ff538dcf Fix misspelled target triples in MC/ARM test commands. 
llvm-svn: 121901
 2010-12-15 22:14:01 +00:00
Kevin Enderby 4886cc8be7 Add some more MC tests for ARM arithmetic instructions that update or don't 
update the condition codes.  These come from my test generator and are just
the ones that MC currently assembles correctly.

llvm-svn: 121830
 2010-12-15 01:24:36 +00:00
Daniel Dunbar a9b9300bb8 MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup. 
llvm-svn: 121772
 2010-12-14 17:37:16 +00:00
Kevin Enderby 3164a346e6 Add support for parsing ARM arithmetic instructions that update or don't update 
the condition codes.  Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix.  The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present.  Four simple test cases added for now, lots more to come.

llvm-svn: 121401
 2010-12-09 19:19:43 +00:00
Jim Grosbach 567ebd0cb5 Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order 
halfword being emitted to the stream first. rdar://8728174

llvm-svn: 120848
 2010-12-03 22:31:40 +00:00
Owen Anderson 6187e66801 Add tests for more forms of Thumb2 loads and stores. 
llvm-svn: 120436
 2010-11-30 18:15:21 +00:00
Bill Wendling 811c936ed5 Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost 
certainly be made more generic. But it does allow us to parse something like:

          ldr     r3, [r2, r4]

correctly in Thumb mode.

llvm-svn: 120408
 2010-11-30 07:44:32 +00:00
Owen Anderson e22c7322b8 Correct Thumb2 encodings for a much wider range of loads and stores. 
llvm-svn: 120364
 2010-11-30 00:14:31 +00:00
Owen Anderson 50d662b6cb Provide Thumb2 encodings for basic loads and stores. 
llvm-svn: 120340
 2010-11-29 22:44:32 +00:00
Bill Wendling 232e52cfb7 Add more Thumb encodings. 
llvm-svn: 120279
 2010-11-29 01:07:48 +00:00
Bill Wendling ccba1a8d95 More Thumb encodings. 
llvm-svn: 120278
 2010-11-29 01:00:43 +00:00
Bill Wendling 9600e97c60 Add Thumb encodings for REV instructions. 
llvm-svn: 120277
 2010-11-29 00:42:50 +00:00
Bill Wendling 775899eb2e Add more Thumb encodings. 
llvm-svn: 120272
 2010-11-29 00:18:15 +00:00
Bill Wendling c01d679928 Add encoding for ARM "trap" instruction. 
llvm-svn: 119938
 2010-11-21 11:05:29 +00:00
Bill Wendling 945b776b6e Add MC encodings for some Thumb instructions. Test for a few of them. The "bx 
lr" instruction cannot be tested just yet. It requires matching a "condition
code", but adding one of those makes things go south quickly...

llvm-svn: 119774
 2010-11-19 01:33:10 +00:00
Bill Wendling 2063b84297 Add support for parsing the writeback ("!") token. 
llvm-svn: 119761
 2010-11-18 23:43:05 +00:00
Owen Anderson 690fa953e1 More tests. 
llvm-svn: 119756
 2010-11-18 23:30:10 +00:00
Owen Anderson 3517585249 Fix encodings for pkhbt, and fix some tests where I accidentally tested ARM mode instead of Thumb2. 
llvm-svn: 119755
 2010-11-18 23:29:56 +00:00
Owen Anderson 3fec5ff14b More Thumb2 encodings. 
llvm-svn: 119737
 2010-11-18 21:15:19 +00:00
Owen Anderson 3625098459 Fill out the set of Thumb2 multiplication operator encodings. 
llvm-svn: 119733
 2010-11-18 20:32:18 +00:00
Owen Anderson d127e7174b Try again at providing Thumb2 encodings for basic multiplication operators. 
llvm-svn: 119601
 2010-11-18 01:08:42 +00:00
Owen Anderson 28883834e1 Revert r119593 while I figure out my testing disagrees with the buildbot. 
llvm-svn: 119597
 2010-11-18 00:42:51 +00:00
Owen Anderson 64aaddcd64 Provide correct Thumb2 encodings for basic multiplication operators. 
llvm-svn: 119593
 2010-11-18 00:19:10 +00:00
Owen Anderson 55425e7f78 Second attempt at correct encodings for Thumb2 bitfield instructions. 
llvm-svn: 119575
 2010-11-17 22:16:31 +00:00
Owen Anderson 6c37ceb182 Revert r119551, which broke buildbots. 
llvm-svn: 119555
 2010-11-17 20:48:51 +00:00
Owen Anderson 7464116bde Provide Thumb2 encodings for bitfield instructions. 
llvm-svn: 119551
 2010-11-17 20:35:29 +00:00
Owen Anderson bced7ae046 More miscellaneous Thumb2 encodings. 
llvm-svn: 119546
 2010-11-17 19:57:38 +00:00
Bill Wendling 9898ac97fd Proper encoding for VLDM and VSTM instructions. The register lists for these 
instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.

llvm-svn: 119460
 2010-11-17 04:32:08 +00:00
Bill Wendling 92756fff57 Test encodings for LDM and STM. 
llvm-svn: 119315
 2010-11-16 01:38:20 +00:00
Owen Anderson 05a8daee21 Add Thumb2 encodings for mov and friends. 
llvm-svn: 119295
 2010-11-16 00:29:56 +00:00
Owen Anderson 7d97a99f4c Provide Thumb2 encodings for sxtb and friends. 
llvm-svn: 119185
 2010-11-15 21:12:05 +00:00
Owen Anderson 2a3c22efba Add Thumb2 encodings for comparison and shift operators. 
llvm-svn: 119176
 2010-11-15 19:58:36 +00:00
Owen Anderson 0e7d728327 Add correct Thumb2 encodings for mvn and friends. 
llvm-svn: 119170
 2010-11-15 18:45:17 +00:00
Owen Anderson 8fdd172502 First stab at providing correct Thumb2 encodings, start with adc. 
llvm-svn: 118924
 2010-11-12 21:12:40 +00:00
Owen Anderson ce2250fba4 Fill out support for Thumb2 encodings of NEON instructions. 
llvm-svn: 118854
 2010-11-11 23:12:55 +00:00
Owen Anderson 99a8cb4875 Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4]. 
llvm-svn: 118843
 2010-11-11 21:36:43 +00:00
Owen Anderson a56a2e1fc5 Flesh out tests for Thumb2 encodings of NEON instructions. 
llvm-svn: 118837
 2010-11-11 21:15:47 +00:00
Owen Anderson 7ffe3b35ac Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure. 
More tests to come.

llvm-svn: 118819
 2010-11-11 19:07:48 +00:00
Owen Anderson c7baee31ad Add support for ARM's specialized vector-compare-against-zero instructions. 
llvm-svn: 118453
 2010-11-08 23:21:22 +00:00
Owen Anderson 30c4892ea5 Add codegen and encoding support for the immediate form of vbic. 
llvm-svn: 118291
 2010-11-05 19:27:46 +00:00
Bill Wendling c002463ac4 Add encoding for VSTR. 
llvm-svn: 118220
 2010-11-04 00:59:42 +00:00
Owen Anderson bc9b31c493 Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization. 
This is both the conceptually correct place for it, as well as allowing it to be more aggressive.

llvm-svn: 118204
 2010-11-03 23:15:26 +00:00
Owen Anderson 0747307049 Add support for code generation of the one register with immediate form of vorr. 
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.

llvm-svn: 118201
 2010-11-03 22:44:51 +00:00
Owen Anderson bb81f80af6 Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead, 
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.

llvm-svn: 118183
 2010-11-03 18:16:27 +00:00
Bill Wendling e84eb99cbb The MC code couldn't handle ARM LDR instructions with negative offsets: 
vldr.64 d1, [r0, #-32]

The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.

llvm-svn: 118144
 2010-11-03 01:49:29 +00:00
Bill Wendling 603bd8f54c Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work 
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.

llvm-svn: 118094
 2010-11-02 22:31:46 +00:00
Owen Anderson dec87e10fd Provide correct encodings for the remaining vst variants that we currently generate. 
llvm-svn: 118087
 2010-11-02 22:18:18 +00:00
Owen Anderson b95618cfe0 Add correct encodings for basic variants for vst3 and vst4. 
llvm-svn: 118082
 2010-11-02 21:47:03 +00:00
Owen Anderson fa08e1e277 Add correct encodings for the basic variants for vst2. 
llvm-svn: 118068
 2010-11-02 21:16:58 +00:00