194ad82666
Add an operator for vaba so it can be implemented using vabd.
...
llvm-svn: 121276
2010-12-08 20:09:10 +00:00
55bc7187ac
Use this new fangled StringSwitch technology.
...
llvm-svn: 121273
2010-12-08 20:02:49 +00:00
4182a16930
Cleanup table a bit.
...
llvm-svn: 121250
2010-12-08 13:03:15 +00:00
8a6449c46e
Add support for loading from a constant pool.
...
llvm-svn: 121226
2010-12-08 01:57:09 +00:00
97b44b5b4a
Add operators for vadd[lw] and vsub[lw]
...
so they can be implemented without clang builtins.
llvm-svn: 121213
2010-12-08 00:14:04 +00:00
c40935fa0c
Add operators for vmlal{_n,_lane} and vmlsl{_n,_lane}
...
so they can be implemented without clang builtins.
llvm-svn: 121209
2010-12-07 23:53:37 +00:00
7a36c68748
Emit vmovl intrinsics first in the arm_neon.h header
...
so they can be used in the implementations of other intrinsics.
llvm-svn: 121208
2010-12-07 23:53:32 +00:00
fb116aed60
Add source Record* reference to PatternToMatch. Allows better diagnostics.
...
llvm-svn: 121196
2010-12-07 23:05:49 +00:00
361afe4ef2
Add an operator for vdup_lane so it can be implemented without a clang builtin.
...
llvm-svn: 121190
2010-12-07 22:39:24 +00:00
17a233c0e5
Add an operator for vmull_lane so it can be implemented without a clang builtin.
...
llvm-svn: 121187
2010-12-07 22:02:48 +00:00
eea0fd0942
Handle recursive values. Add comments.
...
llvm-svn: 121184
2010-12-07 21:12:05 +00:00
f878e62a0d
Remove reference to the CMPz instruction patterns for ARM.
...
llvm-svn: 121180
2010-12-07 20:44:33 +00:00
192336b865
Add new built-in operations for vmull and vmull_n
...
so they can be implemented without requiring clang builtins.
Radar 8446238.
llvm-svn: 121173
2010-12-07 20:02:45 +00:00
8656d82b5b
Trailing whitespace.
...
llvm-svn: 121167
2010-12-07 19:36:07 +00:00
e99956eb3e
Change assert to diagnostic. Message still needs work, but it's better than
...
an assert, at least.
llvm-svn: 121166
2010-12-07 19:35:36 +00:00
182ea825a9
utils/lit/lit/TestFormats.py: [PR8438] unittests: Seek *Tests (not BUILD_MODE/*Tests) under whole unittests/ if BUILD_MODE == '.'
...
llvm-svn: 121118
2010-12-07 07:41:32 +00:00
654db47903
Add an OpReinterpret operation to TableGen's NeonEmitter.
...
An OpReinterpret entry is handled by translating it to OpCast intrinsics for
all combinations of source and destination types with the same total size.
This will be used to generate all the vreinterpret intrinsics.
llvm-svn: 121087
2010-12-07 01:12:23 +00:00
b87116e30a
Fix whitespace.
...
llvm-svn: 121086
2010-12-07 01:12:19 +00:00
52700c348b
Add python scripts to extract debug info using LLDB and do comparison.
...
llvm-svn: 121079
2010-12-07 00:34:59 +00:00
9e1994698d
Add fixup for Thumb1 BL/BLX instructions.
...
llvm-svn: 121072
2010-12-06 23:57:07 +00:00
459a6f150a
KillTheDoctor: Cleanup error_code usage.
...
llvm-svn: 120986
2010-12-06 04:28:01 +00:00
1e4f03ce9f
KillTheDoctor: Fix spelling.
...
llvm-svn: 120985
2010-12-06 04:27:52 +00:00
236ba8d862
Remove trailing whitespace.
...
llvm-svn: 120891
2010-12-04 04:40:15 +00:00
074436b090
Get Neon intrinsic names from the new "Name" field in the tblgen records
...
instead of just converting the record name to lowercase.
llvm-svn: 120809
2010-12-03 17:19:39 +00:00
4e7eb12f6f
I did it wrong. Don't disregard these encodings here.
...
llvm-svn: 120786
2010-12-03 02:25:59 +00:00
e38f1149fa
Ignore decode table conflicts in the tMOVgpr2tgpr, tMOVgpr2gpr, and tMOVtgpr2gpr
...
instructions. They are handled as special moves, but encoded as a normal move.
llvm-svn: 120779
2010-12-03 01:55:30 +00:00
e6b421ccb5
Add support for "_lane" variants of VMUL, VMLA, and VMLS Neon intrinsics.
...
llvm-svn: 120764
2010-12-03 00:34:12 +00:00
791934e122
Support using macros for Neon intrinsics implemented without builtins.
...
Intrinsics implemented with Clang builtins could already be implemented as
either inline functions or macros, but intrinsics implemented directly
(without builtins) could only be inline functions.
llvm-svn: 120763
2010-12-03 00:34:09 +00:00
4375586bd9
Simplify code in Neon intrinsics. No functional changes intended.
...
For most intrinsics, there is no need to allocate a temporary to hold the
result value; just return it directly.
llvm-svn: 120695
2010-12-02 07:44:23 +00:00
79026235e6
Assign arguments of Neon intrinsic macros to local temporaries.
...
Since we're casting them for the calls to the builtins, we need this to
make sure their types get checked in the same way they would if the intrinsics
were implemented as inline functions.
llvm-svn: 120693
2010-12-02 07:10:39 +00:00
014fe01ac8
Use statement expressions in Neon intrinsics defined as macros.
...
This is in preparation for adding assignments to temporaries to ensure
that the proper type checking is done.
llvm-svn: 120649
2010-12-02 02:42:51 +00:00
492de6da40
Add casts for splatted scalars in calls to Neon builtins.
...
llvm-svn: 120641
2010-12-02 01:18:23 +00:00
ec626b09cb
Add a missing cast for Neon vsbl results.
...
The bitwise operations are always done with unsigned values, but the result may
be signed.
llvm-svn: 120640
2010-12-02 01:18:20 +00:00
c08944fd5a
Add another missing cast for Neon vcombine results.
...
llvm-svn: 120639
2010-12-02 01:18:18 +00:00
a9ea9ef840
Add casts in arm_neon.h for result values in inline functions as well as macros.
...
We should not rely on lax-vector-conversions for these intrinsics to work.
llvm-svn: 120638
2010-12-02 01:18:15 +00:00
743eeae937
Avoid "char" for Neon vector elements; make it explicitly signed (or unsigned).
...
llvm-svn: 120632
2010-12-02 00:24:59 +00:00
be764f0cd1
Cast scalar results of Neon macros to the correct type.
...
llvm-svn: 120631
2010-12-02 00:24:56 +00:00
3e8f3f94ef
Add explicit casts for vector arguments to Neon builtins.
...
This avoids warnings with -Wvector-conversions. Radar 8228022.
llvm-svn: 120597
2010-12-01 19:49:58 +00:00
fa5207595e
Add some comments for TableGen's NeonEmitter.
...
llvm-svn: 120596
2010-12-01 19:49:56 +00:00
65a96d082a
Cleanup: simplify checks for integers between 2 and 4.
...
llvm-svn: 120595
2010-12-01 19:49:51 +00:00
dc35e067c1
Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR
...
instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.
llvm-svn: 120594
2010-12-01 19:47:31 +00:00
8335e8fa63
Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the
...
Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.
llvm-svn: 120481
2010-11-30 22:45:47 +00:00
299382e8cb
Add encoding support for Thumb2 PLD and PLI instructions.
...
llvm-svn: 120449
2010-11-30 19:19:31 +00:00
8b16618685
The VLDMQ/VSTMQ instructions are reprented as true Pseudo-insts now (i.e.,
...
no extra encoding information), so we no longer need to special case them
here.
llvm-svn: 120444
2010-11-30 19:08:32 +00:00
f01da1a7df
Tidy up.
...
llvm-svn: 120443
2010-11-30 19:00:13 +00:00
89a4795b52
Delete a few no longer needed references to pseudos.
...
llvm-svn: 120441
2010-11-30 18:56:13 +00:00
318ce7cb3f
Fix the encoding of VLD4-dup alignment.
...
The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function. Use it
for all the VLD-dup instructions for the sake of consistency.
llvm-svn: 120358
2010-11-30 00:00:42 +00:00
7ec3d34553
Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw
...
instructions. This simplifies instruction printing and disassembly.
llvm-svn: 120333
2010-11-29 22:37:40 +00:00
81af4f9eb1
Rename t2 TBB and TBH instructions to reference that they encode the jump table
...
data. Next up, pseudo-izing them.
llvm-svn: 120320
2010-11-29 21:28:32 +00:00
ab425d8360
I swear I did a make clean and make before committing all this...
...
llvm-svn: 120304
2010-11-29 18:47:54 +00:00
457c10e154
Missed another one.
...
llvm-svn: 120302
2010-11-29 18:33:08 +00:00
447762da85
Merge System into Support.
...
llvm-svn: 120298
2010-11-29 18:16:10 +00:00
b91ae1ac52
Fix copy-and-paste error in exception message.
...
llvm-svn: 120033
2010-11-23 19:38:34 +00:00
1801996111
lit.GoogleTest: On case-insensitive filesystem, matching should be case-insensitive when directory name is checked with test_sub_dir.
...
On MSVS8, ${CMAKE_CFG_INTDIR}, aka $(OutDir), has capitalized name(eg. Debug), although $(OutDir) is made with lower case(eg. debug).
llvm-svn: 119781
2010-11-19 03:19:26 +00:00
5a97bd873e
Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM.
...
Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.
llvm-svn: 119760
2010-11-18 23:37:15 +00:00
4a08e563d7
Give the exclamation point a name instead of a number.
...
llvm-svn: 119759
2010-11-18 23:36:54 +00:00
4e22a38759
Change the 'x' type modifier for Neon intrinsics to force a signed integer.
...
This makes it symmetric with the 'u' modifier that forces an unsigned type.
This is needed for unsigned vector shifts, where the shift amount still needs
to be signed. PR8482 (Radar 8603521).
llvm-svn: 119742
2010-11-18 21:43:22 +00:00
7f8ab6ee8b
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
...
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.
Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.
Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.
2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.
rdar://8663787, rdar://8241368
llvm-svn: 119548
2010-11-17 20:13:28 +00:00
9898ac97fd
Proper encoding for VLDM and VSTM instructions. The register lists for these
...
instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.
llvm-svn: 119460
2010-11-17 04:32:08 +00:00
712f07de0e
Use new neon_vector_type and neon_polyvector_type attributes for Neon vectors.
...
llvm-svn: 119406
2010-11-16 23:57:06 +00:00
789e015ce7
Change Neon polynomial types to be signed to match GCC.
...
llvm-svn: 119405
2010-11-16 23:57:03 +00:00
0045702afe
Refactor to new GetNumElements function.
...
No functional change.
llvm-svn: 119404
2010-11-16 23:57:01 +00:00
dfac58bed1
Tidy up some things in <arm_neon.h>.
...
Stop defining types with "__neon_" prefixes and then using typedefs without
the prefix; there's no reason to do that anymore. Remove types that combine
multiple Neon vectors and treat them as a single long vector; they are not
used.
llvm-svn: 119369
2010-11-16 19:39:14 +00:00
2880185194
Reapply "Stop using struct wrappers for Neon vector types in <arm_neon.h>."
...
I've temporarily disabled the failing clang test.
llvm-svn: 119367
2010-11-16 19:16:06 +00:00
4d9c9a646b
Revert "Stop using struct wrappers for Neon vector types in <arm_neon.h>."
...
It's breaking buildbots.
llvm-svn: 119363
2010-11-16 18:43:07 +00:00
5ed2428b3c
This is the first step in adding sane error handling support to LLVMSystem.
...
The system API's will be shifted over to returning an error_code, and returning
other return values as out parameters to the function.
Code that needs to check error conditions will use the errc enum values which
are the same as the posix_errno defines (EBADF, E2BIG, etc...), and are
compatable with the error codes in WinError.h due to some magic in system_error.
An example would be:
if (error_code ec = KillEvil("Java")) { // error_code can be converted to bool.
handle_error(ec);
}
llvm-svn: 119360
2010-11-16 18:31:52 +00:00
d6b6755414
Stop using struct wrappers for Neon vector types in <arm_neon.h>.
...
Thanks to Nate Begeman for an earlier version of this patch.
llvm-svn: 119358
2010-11-16 18:17:03 +00:00
a68e3a5397
Encode the multi-load/store instructions with their respective modes ('ia',
...
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
llvm-svn: 119310
2010-11-16 01:16:36 +00:00
578c765fc8
pull the code to get the operand value out of the loop.
...
llvm-svn: 119130
2010-11-15 07:09:28 +00:00
c19d510363
split the giant encoder loop into two new helper functions.
...
llvm-svn: 119129
2010-11-15 06:59:17 +00:00
42c4ac4841
reduce nesting and minor cleanups, no functionality change.
...
llvm-svn: 119128
2010-11-15 06:42:13 +00:00
63274cbc5d
add fields to the .td files unconditionally, simplifying tblgen a bit.
...
Switch the ARM backend to use 'let' instead of 'set' with this change.
llvm-svn: 119120
2010-11-15 05:19:05 +00:00
fd781bf043
FileCheck: Eliminate DOSish \r from input file.
...
It can pass two tests below on Win32.
- Clang :: CodeGenCXX/dyncast.cpp
- LLVM :: CodeGen/ARM/globals.ll
llvm-svn: 119023
2010-11-14 03:28:22 +00:00
c33f28bf90
ARM fixup encoding for direct call instructions (BL).
...
llvm-svn: 118829
2010-11-11 20:05:40 +00:00
c88ce8329c
Add support for specifying a PostEncoderMethod, which can perform post-processing after the automated encoding of an instruction.
...
Not yet used.
llvm-svn: 118759
2010-11-11 01:19:24 +00:00
f899c87343
Rename AccessesArguments and AccessesArgumentsReadonly, and rewrite
...
their comments.
llvm-svn: 118696
2010-11-10 18:30:00 +00:00
88d5f7fd95
Translate IntrReadArgMem to AccessesArgumentsReadonly.
...
llvm-svn: 118622
2010-11-09 20:07:20 +00:00
d6746d5b46
pass literals like $$1 through to the asm matcher. This isn't right yet, but doesn't hurt.
...
llvm-svn: 118359
2010-11-06 22:06:03 +00:00
4869d346e3
add (and document) the ability for alias results to have
...
fixed physical registers. Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).
llvm-svn: 118352
2010-11-06 19:57:21 +00:00
b6f8e8248d
generalize alias support to allow the result of an alias to
...
add fixed immediate values. Move the aad and aam aliases to
use this, and document it.
llvm-svn: 118350
2010-11-06 19:25:43 +00:00
db6f90c61c
fix a bug where we had an implicit assumption that the
...
result instruction operand numbering matched the result pattern.
Fixing this allows us to move the xchg/test aliases to the .td file.
llvm-svn: 118334
2010-11-06 08:20:59 +00:00
8188fb264f
fix some bugs in the alias support, unblocking changing of "clr" aliases
...
from c++ hacks to proper .td InstAlias definitions. Change them!
llvm-svn: 118330
2010-11-06 07:31:43 +00:00
fecdad6237
Reimplement BuildResultOperands to be in terms of the result instruction's
...
operand list instead of the operand list redundantly declared on the alias
or instruction.
With this change, we finally remove the ins/outs list on the alias. Before:
def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
def : InstAlias<"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.
llvm-svn: 118329
2010-11-06 07:14:44 +00:00
b625dd2d87
implement more checking to reject things like:
...
(someinst GR16:$foo, GR32:$foo)
Reimplement BuildAliasOperandReference to be correctly
based on the names of operands in the result pattern,
instead of on the instruction operand definitions.
llvm-svn: 118328
2010-11-06 07:06:09 +00:00
7603052d49
decode and validate instruction alias result definitions.
...
llvm-svn: 118327
2010-11-06 06:54:38 +00:00
23064cb4e5
simplify
...
llvm-svn: 118326
2010-11-06 06:45:08 +00:00
9f093815fa
fix another fixme, replacing a string with a semantic pointer.
...
llvm-svn: 118325
2010-11-06 06:43:11 +00:00
8ffd129950
disolve a hack, having CodeGenInstAlias decode the alias in the .td
...
file instead of the asmmatcher.
llvm-svn: 118324
2010-11-06 06:39:47 +00:00
71049f78ed
In the calling convention logic, ValVT is always a legal type,
...
and as such can be represented by an MVT - the more complicated
EVT is not needed. Use MVT for ValVT everywhere.
llvm-svn: 118245
2010-11-04 10:49:57 +00:00
4efe13d8d4
partition operand processing between aliases and instructions.
...
Right now the code is partitioned but the behavior is the same.
This should be improved in the near future. This removes some
uses of TheOperandList.
llvm-svn: 118232
2010-11-04 02:11:18 +00:00
ccde463250
pull name slicing out of BuildInstructionOperandReference so
...
it doesn't do any lexical stuff anymore.
llvm-svn: 118230
2010-11-04 01:58:23 +00:00
897a140e2a
cleanups.
...
llvm-svn: 118228
2010-11-04 01:55:23 +00:00
7108dad130
replace SrcOpNum with SrcOpName, eliminating a numering dependency
...
on the incoming operand list. This also makes the code simpler.
llvm-svn: 118225
2010-11-04 01:42:59 +00:00
4779e3e94a
strength reduce some code, resolving a fixme.
...
llvm-svn: 118219
2010-11-04 00:57:06 +00:00
743081d097
take a big step to making aliases more general and less of a hack:
...
now matchables contain an explicit list of how to populate each
operand in the result instruction instead of having them somehow
magically be correlated to the input inst.
llvm-svn: 118217
2010-11-04 00:43:46 +00:00
e4e6bf49f3
Support generating an MC'ized CodeEmitter directly. Maintain a reference to the
...
Fixups list for the instruction so the operand encoders can add to it as
needed.
llvm-svn: 118206
2010-11-03 23:38:14 +00:00
896cf04885
rename Operand -> AsmOperand for clarity.
...
llvm-svn: 118190
2010-11-03 19:47:34 +00:00
f5dda01f33
Inside the calling convention logic LocVT is always a simple
...
value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
llvm-svn: 118167
2010-11-03 11:35:31 +00:00
c6af2b4066
Break ARM addrmode4 (load/store multiple base address) into its constituent
...
parts. Represent the operation mode as an optional operand instead.
rdar://8614429
llvm-svn: 118137
2010-11-03 01:01:43 +00:00
cc5dce89d4
Completely reject instructions that have an operand in their
...
ins/outs list that isn't specified by their asmstring. Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right. Mark a bunch of ARM instructions that use this as
isCodeGenOnly. Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).
llvm-svn: 118119
2010-11-02 23:40:41 +00:00
Bob Wilson