a8d177b2d4
Implement frame unwinding information emission for Thumb1. Not finished yet because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed.
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llvm-svn: 127104
2011-03-05 18:43:50 +00:00
2f93128109
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
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llvm-svn: 123170
2011-01-10 12:39:04 +00:00
bcaf681cde
Add const qualifiers to CodeGen's use of LLVM IR constructs.
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llvm-svn: 101334
2010-04-15 01:51:59 +00:00
294aea709e
Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2.
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llvm-svn: 85406
2009-10-28 17:33:28 +00:00
5a9788b979
80-column cleanup
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llvm-svn: 85064
2009-10-25 18:55:46 +00:00
5457a96b63
Trim more includes.
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llvm-svn: 84832
2009-10-22 05:11:00 +00:00
55f1c09e31
Push LLVMContexts through the IntegerType APIs.
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llvm-svn: 78948
2009-08-13 21:58:54 +00:00
780748d565
- More refactoring. This gets rid of all of the getOpcode calls.
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- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
llvm-svn: 77300
2009-07-28 05:48:47 +00:00
8953720f23
Refactor. Get rid of a few more getOpcode() calls.
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llvm-svn: 77164
2009-07-26 18:55:14 +00:00
c1a5cfa9a0
Get rid of a couple of unnecessary getOpcode calls.
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llvm-svn: 77035
2009-07-25 01:25:08 +00:00
edb4a70325
Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come.
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llvm-svn: 77011
2009-07-24 23:12:02 +00:00
c3259f3ffb
Thumb2 should use the register scavenger.
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llvm-svn: 76930
2009-07-24 01:05:51 +00:00
cdd405d804
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
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llvm-svn: 76919
2009-07-24 00:16:18 +00:00
47db941fd3
Get rid of the Pass+Context magic.
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llvm-svn: 76702
2009-07-22 00:24:57 +00:00
84517443ca
Let callers decide the sub-register index on the def operand of rematerialized instructions.
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Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.
llvm-svn: 75900
2009-07-16 09:20:10 +00:00
b6b2530000
Move EVER MORE stuff over to LLVMContext.
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llvm-svn: 75703
2009-07-14 23:09:55 +00:00
22c2fba978
Use common code for both ARM and Thumb-2 instruction and register info.
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llvm-svn: 75067
2009-07-08 23:10:31 +00:00
fb8d6d5b58
Implement changes from Chris's feedback.
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Finish converting lib/Target.
llvm-svn: 75043
2009-07-08 20:53:28 +00:00
03ab0bbb24
Generalize opcode selection in ARMBaseRegisterInfo.
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llvm-svn: 75036
2009-07-08 20:28:28 +00:00
9ca33e8a9f
Push methods into base class in preparation for sharing.
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llvm-svn: 75020
2009-07-08 18:31:39 +00:00
6dd2730024
Start converting to new error handling API.
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cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)
llvm-svn: 75018
2009-07-08 18:01:40 +00:00
ade05a37f1
Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2.
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llvm-svn: 74731
2009-07-02 22:18:33 +00:00
Anton Korobeynikov