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Author SHA1 Message Date
Yaxun Liu c41e2f6e7b Recommit CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value 
The regression on ppc64 was not due to this commit.

llvm-svn: 320788
 2017-12-15 03:56:57 +00:00
Yaxun Liu f902ef0a5d Revert CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value 
This commit might have caused regression on ppc64. Revert it to verify that.

llvm-svn: 320712
 2017-12-14 16:12:04 +00:00
Yaxun Liu a5315a040d CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value 
Two issues were found about machine inst scheduler when compiling ProRender
with -g for amdgcn target:

GCNScheduleDAGMILive::schedule tries to update LiveIntervals for DBG_VALUE, which it
should not since DBG_VALUE is not mapped in LiveIntervals.

when DBG_VALUE is the last instruction of MBB, ScheduleDAGInstrs::buildSchedGraph and
ScheduleDAGMILive::scheduleMI does not move RPTracker properly, which causes assertion.

This patch fixes that.

Differential Revision: https://reviews.llvm.org/D41132

llvm-svn: 320650
 2017-12-13 22:38:09 +00:00