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25 Commits

Author SHA1 Message Date
Venkatraman Govindaraju 81aae57282 [Sparc] Add support for parsing fcmp with %fcc registers. 
llvm-svn: 202610
 2014-03-02 03:39:39 +00:00
Venkatraman Govindaraju e0c5bff720 [Sparc] Add support for parsing sparcv9 instructions addc/subc/addccc/subccc. 
llvm-svn: 202598
 2014-03-01 18:54:52 +00:00
Rafael Espindola b4eec1daa1 Remove support for not using .loc directives. 
Clang itself was not using this. The only way to access it was via llc.

llvm-svn: 200862
 2014-02-05 18:00:21 +00:00
Venkatraman Govindaraju 52b6473d74 [Sparc] Set %o7 as the return address register instead of %i7 in MCRegisterInfo. Also, add CFI instructions to initialize the frame correctly. 
llvm-svn: 200617
 2014-02-01 18:54:16 +00:00
Rafael Espindola e41383f899 Pass a MCSubtargetInfo down to the TargetStreamer creation. 
With this the target streamers will be able to know the target features that
are in use.

llvm-svn: 200135
 2014-01-26 06:38:58 +00:00
Rafael Espindola 24ea09ef7d Construct the MCStreamer before constructing the MCTargetStreamer. 
This has a few advantages:
* Only targets that use a MCTargetStreamer have to worry about it.
* There is never a MCTargetStreamer without a MCStreamer, so we can use a
  reference.
* A MCTargetStreamer can talk to the MCStreamer in its constructor.

llvm-svn: 200129
 2014-01-26 06:06:37 +00:00
Venkatraman Govindaraju dc3bcc19cf [SparcV9] Add support for JIT in Sparc64. 
With this change, all supported tests in test/ExecutionEngine pass in sparcv9.

llvm-svn: 199977
 2014-01-24 07:10:19 +00:00
Chandler Carruth 8a8cd2bab9 Re-sort all of the includes with ./utils/sort_includes.py so that 
subsequent changes are easier to review. About to fix some layering
issues, and wanted to separate out the necessary churn.

Also comment and sink the include of "Windows.h" in three .inc files to
match the usage in Memory.inc.

llvm-svn: 198685
 2014-01-07 11:48:04 +00:00
Venkatraman Govindaraju b73aeca888 [Sparc] Add ELF Object Writer for Sparc. 
llvm-svn: 198580
 2014-01-06 01:22:54 +00:00
Venkatraman Govindaraju 5f1cce50e6 [Sparc] Add initial implementation of MC Code emitter for sparc. 
llvm-svn: 198533
 2014-01-05 02:13:48 +00:00
Venkatraman Govindaraju c2dee7dc74 [Sparc] Add the initial implementation of an asm parser for sparc/sparcv9. 
llvm-svn: 198484
 2014-01-04 11:30:13 +00:00
Venkatraman Govindaraju bf683fd15c [Sparc] Lower and MachineInstr to MC and print assembly using MCInstPrinter. 
llvm-svn: 198030
 2013-12-26 01:49:59 +00:00
Jakob Stoklund Olesen 15b3e90081 Define SPARC code models. 
Currently, only abs32 and pic32 are implemented. Add a test case for
abs32 with 64-bit code. 64-bit PIC code is currently broken.

llvm-svn: 179463
 2013-04-13 19:02:23 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Craig Topper c4965bce14 Convert assert(0) to llvm_unreachable 
llvm-svn: 149814
 2012-02-05 07:21:30 +00:00
Evan Cheng ecb2908bf9 Sink codegen optimization level into MCCodeGenInfo along side relocation model 
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.

llvm-svn: 144788
 2011-11-16 08:38:26 +00:00
Evan Cheng 2bb4035707 Move TargetRegistry and TargetSelect from Target to Support where they belong. 
These are strictly utilities for registering targets and components.

llvm-svn: 138450
 2011-08-24 18:08:43 +00:00
Evan Cheng 4d6c9d711d Some refactoring so TargetRegistry.h no longer has to include any files 
from MC.

llvm-svn: 138367
 2011-08-23 20:15:21 +00:00
Evan Cheng 6376593ed1 createXXXMCCodeGenInfo should be static. 
llvm-svn: 135826
 2011-07-23 00:01:04 +00:00
Evan Cheng 8c886a40d2 Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo, 
InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC.

llvm-svn: 135812
 2011-07-22 21:58:54 +00:00
Evan Cheng efd9b4240f - Move CodeModel from a TargetMachine global option to MCCodeGenInfo. 
- Introduce JITDefault code model. This tells targets to set different default
  code model for JIT. This eliminates the ugly hack in TargetMachine where
  code model is changed after construction.

llvm-svn: 135580
 2011-07-20 07:51:56 +00:00
Evan Cheng 2129f59637 Introduce MCCodeGenInfo, which keeps information that can affect codegen 
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.

llvm-svn: 135468
 2011-07-19 06:37:02 +00:00
Evan Cheng d60fa58ba1 Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down 
to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.

llvm-svn: 135424
 2011-07-18 20:57:22 +00:00
Evan Cheng 1705ab00ab Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes. 
llvm-svn: 135219
 2011-07-14 23:50:31 +00:00
Evan Cheng bc153d49b7 Next round of MC refactoring. This patch factor MC table instantiations, MC 
registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184
 2011-07-14 20:59:42 +00:00