840beec2d0
Make consistent use of MCPhysReg instead of uint16_t throughout the tree.
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llvm-svn: 205610
2014-04-04 05:16:06 +00:00
b6d0bd48bd
[C++11] Replace llvm::next and llvm::prior with std::next and std::prev.
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Remove the old functions.
llvm-svn: 202636
2014-03-02 12:27:27 +00:00
3b6b0e42f0
[Sparc] 80 column rule. No functionality change.
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llvm-svn: 202565
2014-03-01 02:28:34 +00:00
7a9c6549ba
Lower FNEG just like FABS to fneg[ds] and fmov[ds], thus avoiding
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expensive libcall. Also, Qp_neg is not implemented on at least
FreeBSD. This is also what gcc is doing.
llvm-svn: 202422
2014-02-27 19:26:29 +00:00
facca1f049
SPARC: Implement TRAP lowering. Matches what GCC emits.
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llvm-svn: 201994
2014-02-23 21:43:52 +00:00
37136c0333
Expand 64bit {SHL,SHR,SRA}_PARTS on sparcv9.
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llvm-svn: 201718
2014-02-19 21:35:39 +00:00
104643d0aa
[Sparc] Emit correct relocations for PIC code when integrated assembler is used.
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llvm-svn: 200961
2014-02-07 04:24:35 +00:00
dfe09b1b5b
[Sparc] Use SparcMCExpr::VariantKind itself as MachineOperand's target flags.
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llvm-svn: 200960
2014-02-07 02:36:06 +00:00
ef1d59a175
Implement SPARCv9 atomic_swap_64 with a pseudo.
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The SWAP instruction only exists in a 32-bit variant, but the 64-bit
atomic swap can be implemented in terms of CASX, like the other atomic
rmw primitives.
llvm-svn: 200453
2014-01-30 04:48:46 +00:00
fd5c1f9497
[Sparc] Use %r_disp32 for pc_rel entries in gcc_except_table and eh_frame.
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Otherwise, assembler (gas) fails to assemble them with error message "operation
combines symbols in different segments". This is because MC computes
pc_rel entries with subtract expression between labels from different sections.
llvm-svn: 200373
2014-01-29 04:51:35 +00:00
6f39ce4be2
Clean up the Legal/Expand logic for SPARC popc.
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llvm-svn: 200141
2014-01-26 08:12:34 +00:00
ead3b3d7a1
Only generate the popc instruction for SPARC CPUs that implement it.
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The popc instruction is defined in the SPARCv9 instruction set
architecture, but it was emulated on CPUs older than Niagara 2.
llvm-svn: 200131
2014-01-26 06:09:59 +00:00
39f0833f47
Fix swapped CASA operands.
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Found by SingleSource/UnitTests/AtomicOps.c
llvm-svn: 200130
2014-01-26 06:09:54 +00:00
dc3bcc19cf
[SparcV9] Add support for JIT in Sparc64.
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With this change, all supported tests in test/ExecutionEngine pass in sparcv9.
llvm-svn: 199977
2014-01-24 07:10:19 +00:00
05ae2d6715
Implement atomicrmw operations in 32 and 64 bits for SPARCv9.
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These all use the compare-and-swap CASA/CASXA instructions.
llvm-svn: 199975
2014-01-24 06:23:31 +00:00
dd634cac74
[Sparc] Add support for inline assembly constraints which specify registers by their aliases.
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llvm-svn: 199786
2014-01-22 03:18:42 +00:00
407e442245
[Sparc] Add support for inline assembly constraint 'I'.
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llvm-svn: 199781
2014-01-22 01:29:51 +00:00
06234ec147
Add FPExt option to CCValAssign::LocInfo. When generating calling-convention
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promotion code, Tablegen will now select FPExt for floating point promotions
(previously it had returned AExt, which is not valid for floating point types).
Any out-of-tree targets that were relying on AExt being returned for FP
promotions will need to update their code check for FPExt instead.
llvm-svn: 199252
2014-01-14 19:56:36 +00:00
e7084a1c5c
The SPARCv9 ABI returns a float in %f0.
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This is different from the argument passing convention which puts the
first float argument in %f1.
With this patch, all returned floats are treated as if the 'inreg' flag
were set. This means multiple float return values get packed in %f0,
%f1, %f2, ...
Note that when returning a struct in registers, clang will set the
'inreg' flag on the return value, so that behavior is unchanged. This
also happens when returning a float _Complex.
llvm-svn: 199028
2014-01-12 04:13:17 +00:00
8a8cd2bab9
Re-sort all of the includes with ./utils/sort_includes.py so that
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subsequent changes are easier to review. About to fix some layering
issues, and wanted to separate out the necessary churn.
Also comment and sink the include of "Windows.h" in three .inc files to
match the usage in Memory.inc.
llvm-svn: 198685
2014-01-07 11:48:04 +00:00
13199b17f8
Remove unnecessary #includes.
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llvm-svn: 198585
2014-01-06 06:00:00 +00:00
908bf814e7
Refactor function that checks that __builtin_returnaddress's argument is constant.
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This moves the check up into the parent class so that all targets can use it
without having to copy (and keep in sync) the same error message.
llvm-svn: 198579
2014-01-06 00:43:20 +00:00
df7dd28dc8
Emit an error message if the value passed to __builtin_returnaddress isn't a constant
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__builtin_returnaddress requires that the value passed into is be a constant.
However, at -O0 even a constant expression may not be converted to a constant.
Emit an error message intead of crashing.
llvm-svn: 198531
2014-01-05 01:47:20 +00:00
96ab3bc5bd
[SparcV9]: Implement RETURNADDR and FRAMEADDR lowering in SPARC64.
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Fixes PR18356.
llvm-svn: 198480
2014-01-04 07:17:21 +00:00
9a3da52ea2
[Sparc] Handle atomic loads/stores in sparc backend.
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llvm-svn: 198286
2014-01-01 22:11:54 +00:00
77011e861b
[SparcV9]: Custom lower UMULO/SMULO so that the arguments are send to __multi3() in correct order.
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llvm-svn: 198281
2014-01-01 20:22:45 +00:00
5ac9c8faec
[SparcV9] For codegen generated library calls that return float, set inreg flag manually in LowerCall().
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This makes the sparc backend to generate Sparc64 ABI compliant code.
llvm-svn: 198149
2013-12-29 04:27:21 +00:00
0776cc0acd
[SparcV9]: Implement lowering of long double (fp128) arguments in Sparc64 ABI.
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Also, pass fp128 arguments to varargs through integer registers if necessary.
llvm-svn: 198145
2013-12-29 01:20:36 +00:00
61116e7084
[SPARCV9]: Adjust the resultant pointer of DYNAMIC_STACKALLOC with the stack BIAS on sparcV9.
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llvm-svn: 196755
2013-12-09 05:13:25 +00:00
f6c8fe983b
[Sparc]: Implement getSetCCResultType() in SparcTargetLowering so that umulo/smulo can be lowered on sparcv9 without an assertion error.
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llvm-svn: 196751
2013-12-09 04:02:15 +00:00
72cc248524
[SparcV9]: Expand MULHU/MULHS:i64 and UMUL_LOHI/SMUL_LOHI:i64 on sparcv9.
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This fixes PR18150.
llvm-svn: 196735
2013-12-08 22:06:07 +00:00
0510db0597
[SparcV9] Enable custom lowering of DYNAMIC_STACKALLOC in sparc64.
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llvm-svn: 195573
2013-11-24 17:41:41 +00:00
b6517850fb
Expand rotate instructions on sparcv9 as well.
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llvm-svn: 194500
2013-11-12 19:04:45 +00:00
5ae77f7564
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode.
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llvm-svn: 193957
2013-11-03 12:28:40 +00:00
f1d807ee13
[Sparc] Expand FP_TO_UINT, UINT_TO_FP for fp128.
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llvm-svn: 193947
2013-11-03 08:00:19 +00:00
5615aca219
[SparcV9] Add ctpop instruction for i64. Also, expand ctlz, cttz and bswap.
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llvm-svn: 193941
2013-11-03 05:59:07 +00:00
2262cfaf19
SparcV9 doesnt have rem instruction either.
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llvm-svn: 193789
2013-10-31 19:22:33 +00:00
8812485d41
[Sparc] Disable tail call optimization for sparc64.
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This patch fixes PR17506.
llvm-svn: 192294
2013-10-09 12:50:39 +00:00
2ea4c2880c
[Sparc] Implement JIT for SPARC.
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No new testcases. However, this patch makes all supported JIT testcases in
test/ExecutionEngine pass on Sparc.
llvm-svn: 192176
2013-10-08 07:15:22 +00:00
572d5057e3
[Sparc] Custom lower addc/adde/subc/sube on i64 in sparc64.
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This is required because i64 is a legal type but addxcc/subxcc reads icc carry bit, which are 32 bit conditional codes.
llvm-svn: 192054
2013-10-06 03:36:18 +00:00
ece63dbd0d
[Sparc] Use correct alignment while loading/storing fp128 values.
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llvm-svn: 192023
2013-10-05 02:29:47 +00:00
30781deb1c
[Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP with fp128 operand.
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llvm-svn: 192015
2013-10-05 00:31:41 +00:00
4c0cdd734c
[Sparc] Implements exception handling in SPARC with DwarfCFI.
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llvm-svn: 191432
2013-09-26 15:11:00 +00:00
cb1dca602c
[Sparc] Add support for TLS in sparc.
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llvm-svn: 191164
2013-09-22 06:48:52 +00:00
7e7eb8ce69
[SPARC] Make functions with GLOBAL_OFFSET_TABLE access as non-leaf functions.
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llvm-svn: 191160
2013-09-22 01:40:24 +00:00
829aec5900
[Sparc] Fix lowering FABS on fp128 (long double) on pre-v9 targets.
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llvm-svn: 191154
2013-09-21 23:51:08 +00:00
55ecb10e99
[Sparc] Correctly handle call to functions with ReturnsTwice attribute.
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In sparc, setjmp stores only the registers %fp, %sp, %i7 and %o7. longjmp restores
the stack, and the callee-saved registers (all local/in registers: %i0-%i7, %l0-%l7)
using the stored %fp and register windows. However, this does not guarantee that the longjmp
will restore the registers, as they were when the setjmp was called. This is because these
registers may be clobbered after returning from setjmp, but before calling longjmp.
This patch prevents the registers %i0-%i5, %l0-l7 to live across the setjmp call using the register mask.
llvm-svn: 190033
2013-09-05 05:32:16 +00:00
b803cec00e
[Sparc] Fix an assertion failure while lowering fcmp on long double.
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This assertion is triggered because an integer constant is created with wrong
type.
llvm-svn: 189948
2013-09-04 15:15:20 +00:00
59039dc1bf
[Sparc] Add support for soft long double (fp128).
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llvm-svn: 189780
2013-09-03 04:11:59 +00:00
35e0c382d5
[Sparc] Add long double (f128) instructions to sparc backend.
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llvm-svn: 189198
2013-08-25 18:30:06 +00:00
Craig Topper