wangtao
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
297,703 Commits 29 Branches 0 Tags 2.2 GiB
Commit Graph

225 Commits

Author SHA1 Message Date
Craig Topper f517f1a516 [X86] Implement old kunpck intrinsics using vector ops on vXi1 instead of integer shift/and/or 
Summary:
kunpck intrinsics were removed in favor of native IR a few months ago. The implementation lowers them as by operation on the integer types passed to the intrinsic and then just shifting, masking, and oring them together. A special X86 DAG combine was added to recognize this patter and turn it into a concat_vector operation.

I think it makes more sense to keep the IR implementation closer to vector operations on vXi1. Given that we expect these builtins to be used around other builtins that operate on k-registers which we try to represent in IR with vXi1. InstCombine should be able to get rid of the bitcasts between integers and vXi1 leaving only the vector operations.

Reviewers: RKSimon, spatel, zvi, jina.nahias

Reviewed By: RKSimon

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D42016

llvm-svn: 322461
 2018-01-14 19:23:50 +00:00
Martin Bohme 06997a767e [X86] Use {{.*}} instead of hardcoded %1 in knot test. 
This makes the test more resilient and consistent with the other tests
introduced in r320919.

llvm-svn: 320971
 2017-12-18 11:29:21 +00:00
Craig Topper 5028ace602 [X86] Implement kand/kandn/kor/kxor/kxnor/knot intrinsics using native IR. 
llvm-svn: 320919
 2017-12-16 08:26:22 +00:00
Jina Nahias eb0829155f [x86][AVX512] Lowering kunpack intrinsics to LLVM IR 
This patch, together with a matching llvm patch (https://reviews.llvm.org/D39720), implements the lowering of X86 kunpack intrinsics to IR.

Differential Revision: https://reviews.llvm.org/D39719

Change-Id: Id5d3cb394ad33b98be79a6783d1d15569e2b798d
llvm-svn: 319777
 2017-12-05 15:42:47 +00:00
Uriel Korach 5b2b71d909 [X86] test/testn intrinsics lowering to IR. clang side 
Change Header files of the intrinsics for lowering test and testn intrinsics to IR code.
Removed test and testn builtins from clang

Differential Revision: https://reviews.llvm.org/D38737

llvm-svn: 318035
 2017-11-13 12:50:52 +00:00
Jina Nahias aecd4f5f9d Change 
// CHECK: shufflevector <8 x double> %0, <8 x double> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 8, i32 9>
To
// CHECK: shufflevector <8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 8, i32 9>
for fixing 318025 commit warning

Change-Id: Id48a1fe1f247fe6a0b84e7189f18d2e637678e79
llvm-svn: 318031
 2017-11-13 11:41:41 +00:00
Jina Nahias dca979194d [x86][AVX512] Lowering shuffle i/f intrinsics to LLVM IR 
This patch, together with a matching llvm patch (https://reviews.llvm.org/D38671), implements the lowering of X86 shuffle i/f intrinsics to IR.

Differential Revision: https://reviews.llvm.org/D38672

Change-Id: I9b3c2f2b34323bd9ccb21d0c1832f848b88ec047
llvm-svn: 318025
 2017-11-13 09:15:31 +00:00
Sanjay Patel d386336441 [x86] make assertions less strict in avx512f test file 
Missed a line in r314158.

llvm-svn: 314159
 2017-09-25 21:31:08 +00:00
Sanjay Patel 0433194e55 [x86] make assertions less strict in avx512f test file 
I'm not sure why yet, but there may be differences depending on the host?

llvm-svn: 314158
 2017-09-25 21:27:37 +00:00
Sanjay Patel 1acd2cf15a [x86] remove RUNs that were checking fully optimized IR 
Clang regression tests that depend on the optimizer can break
when there are changes to LLVM...as in: 
https://reviews.llvm.org/rL314117

llvm-svn: 314144
 2017-09-25 19:56:57 +00:00
Jina Nahias 3ad702a1ed Lowering Mask Set1 intrinsics to LLVM IR 
This patch, together with a matching llvm patch (https://reviews.llvm.org/D37669), implements the lowering of X86 mask set1 intrinsics to IR.

Differential Revision: https://reviews.llvm.org/D37668

llvm-svn: 313624
 2017-09-19 11:00:27 +00:00
Craig Topper 04370d3a82 [X86] Disable _mm512_maskz_set1_epi64 intrinsic on 32-bit targets to prevent a backend isel failure. 
The __builtin_ia32_pbroadcastq512_mem_mask we were previously trying to use in 32-bit mode is not implemented in the x86 backend and causes isel to fail in release builds. In debug builds it fails even earlier during legalization with an llvm_unreachable.

While there add the missing test case for this intrinsic for this for 64-bit mode.

This fixes PR34631. D37668 should be able to recover this for 32-bit mode soon. But I wanted to fix the crash ahead of that.

llvm-svn: 313392
 2017-09-15 20:27:59 +00:00
Uriel Korach 3fba3c3b0c [X86] [PATCH] [intrinsics] Lowering X86 ABS intrinsics to IR. (clang) 
This patch, together with a matching llvm patch (https://reviews.llvm.org/D37693), implements the lowering of X86 ABS intrinsics to IR.

Differential Revision: https://reviews.llvm.org/D37694

llvm-svn: 313133
 2017-09-13 09:02:02 +00:00
Simon Pilgrim 1ba2bf2162 [X86][AVX512] _mm512_stream_load_si512 should take a void const* argument (PR33977) 
Based off the Intel Intrinsics guide, we should expect a void const* argument.

Prevents 'passing 'const void *' to parameter of type 'void *' discards qualifiers' warnings.

Differential Revision: https://reviews.llvm.org/D37449

llvm-svn: 312523
 2017-09-05 10:06:41 +00:00
Sanjay Patel d53f6a8980 [x86] weaken test checks that shouldn't be here in the first place 
This test would fail after the proposed change in:
https://reviews.llvm.org/D34242

llvm-svn: 306433
 2017-06-27 17:39:46 +00:00
Simon Pilgrim 96d02f5503 [X86][AVX] Added support for _mm256_zext* helper intrinsics (PR32839) 
llvm-svn: 301749
 2017-04-29 17:17:06 +00:00
Simon Pilgrim 9f6e79c5e4 [X86][SSE] Update MOVNTDQA non-temporal loads to generic implementation (clang) 
MOVNTDQA non-temporal aligned vector loads can be correctly represented using generic builtin loads, allowing us to remove the existing x86 intrinsics.

LLVM companion patch: D31767.

Differential Revision: https://reviews.llvm.org/D31766

llvm-svn: 300326
 2017-04-14 15:05:57 +00:00
Simon Pilgrim 60e924985c [X86][AVX512] Add _mm512_cvtsd_f64 and _mm512_cvtss_f32 intrinsics (PR32305) 
Differential Revision: https://reviews.llvm.org/D31155

llvm-svn: 298364
 2017-03-21 12:46:13 +00:00
Igor Breger f050b797ac [X86][AVX512][Clang][Intrinsics] Adding missing intrinsics to Clang . 
Summary:
Adding missing intrinsics :
    _mm512_set_epi16,
    _mm512_set_epi8,
    _mm512_permutevar_epi32
    _mm512_mask_permutevar_epi32

Reviewers: zvi, guyblank, eladcohen, craig.topper

Reviewed By: craig.topper

Subscribers: craig.topper, cfe-commits

Differential Revision: https://reviews.llvm.org/D31034

llvm-svn: 298208
 2017-03-19 08:27:16 +00:00
Sanjay Patel e795daa55e [x86] these aren't the undefs you're looking for (PR32176) 
x86 has undef SSE/AVX intrinsics that should represent a bogus register operand. 
This is not the same as LLVM's undef value which can take on multiple bit patterns.

There are better solutions / follow-ups to this discussed here:
https://bugs.llvm.org/show_bug.cgi?id=32176
...but this should prevent miscompiles with a one-line code change.

Differential Revision: https://reviews.llvm.org/D30834

llvm-svn: 297588
 2017-03-12 19:15:10 +00:00
Craig Topper 367c86ddbe [AVX-512] Replace subvector broadcast builtins with shufflevectors and selects. 
Verified that the backend codegens this equally well.

llvm-svn: 292329
 2017-01-18 02:17:10 +00:00
Craig Topper 70536f4e47 [AVX-512] Replace masked 512-bit pmuldq and pmuludq builtins with the newly added unmasked versions and selects. 
llvm-svn: 290580
 2016-12-27 04:04:57 +00:00
Craig Topper c5ab78d4c3 Revert r290575 "[AVX-512] Replace masked 512-bit pmuldq and pmuludq builtins with the newly added unmasked versions and selects." 
I failed to merge this with r290574.

llvm-svn: 290578
 2016-12-27 04:03:25 +00:00
Craig Topper 6ad5bcc8ac [AVX-512] Replace masked 512-bit pmuldq and pmuludq builtins with the newly added unmasked versions and selects. 
llvm-svn: 290575
 2016-12-27 03:46:16 +00:00
Craig Topper 678b07fe3c [AVX-512] Remove masking from 512-bit vpermil builtins. The backend now has versions without masking so wrap it with select. 
This will allow the backend to constant fold these to generic shuffle vectors like 128-bit and 256-bit without having to working about handling masking.

llvm-svn: 289351
 2016-12-11 01:26:52 +00:00
Craig Topper 6aefe00ccf [X86] Replace valignd/q builtins with appropriate __builtin_shufflevector. 
llvm-svn: 287733
 2016-11-23 01:47:12 +00:00
Simon Pilgrim 698528d83b [X86][AVX512] Replace lossless i32/u32 to f64 conversion intrinsics with generic IR 
Both the (V)CVTDQ2PD (i32 to f64) and (V)CVTUDQ2PD (u32 to f64) conversion instructions are lossless and can be safely represented as generic __builtin_convertvector calls instead of x86 intrinsics without affecting final codegen.

This patch removes the clang builtins and their use in the headers - a future patch will deal with removing the llvm intrinsics.

This is an extension patch to D20528 which dealt with the equivalent sse/avx cases.

Differential Revision: https://reviews.llvm.org/D26686

llvm-svn: 287088
 2016-11-16 09:27:40 +00:00
Craig Topper 5e0709d60b [AVX-512] Replace masked dword and qword variable shift builtins with unmasked builtins and a select. 
This is part of a set of changes to allow InstCombine in the backend to optimize variable shifts without having to know about masking.

llvm-svn: 286757
 2016-11-13 07:26:34 +00:00
Craig Topper 2c8f49e67b [AVX-512] Use scalar vfmsub/vfnmsub mask3 intrinsics instead of inverting the mask argument of a vfmadd intrinsic. 
Summary: Inverting the mask argument does not reflect the intended semantics of the intrinsic.

Reviewers: igorb, delena

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D26019

llvm-svn: 286733
 2016-11-12 23:24:34 +00:00
Craig Topper 1a44193afd [AVX-512] Convert the rest of the masked shift by immediate and by single element builtins over to the newly added unmasked builtins and a select. 
This should also fix PR30691 since the new builtins are handled like the legacy builtins in the backend.

llvm-svn: 286714
 2016-11-12 07:16:59 +00:00
Ayman Musa e60a41ca28 [X86][AVX512][Clang] Add support for mask_{move|store|load}_s{s/d} and int2mask/mask2int intrinsics. 
Differential Revision: https://reviews.llvm.org/D26021

llvm-svn: 286229
 2016-11-08 12:00:30 +00:00
Craig Topper 08bf53ffda [AVX-512] Remove masked vector insert builtins and replace with native shufflevectors and selects. 
Unfortunately, the backend currently doesn't fold masks into the instructions correctly when they come from these shufflevectors. I'll work on that in a future commit.

llvm-svn: 285667
 2016-11-01 05:47:56 +00:00
Craig Topper 93ffabd28d [AVX-512] Remove masked vector extract builtins and replace with native shufflevectors and selects. 
Unfortunately, the backend currently doesn't fold masks into the instructions correctly when they come from these shufflevectors. I'll work on that in a future commit.

llvm-svn: 285540
 2016-10-31 04:30:56 +00:00
Craig Topper 531ce28311 [AVX-512] Replace 64-bit element and 512-bit vector pmin/pmax builtins with native IR like we do for 128/256-bit, but with the addition of masking. 
llvm-svn: 284956
 2016-10-24 04:04:24 +00:00
Craig Topper 0c5da26572 [AVX-512] Replace 512-bit pmovzx/sx builtins with native IR. 
llvm-svn: 284936
 2016-10-23 07:35:47 +00:00
Michael Zuckerman 9e43ccfe68 [Clang][AVX512][BuiltIn]Adding missing intrinsics move_{sd|ss} to clang 
Differential Revision: http://reviews.llvm.org/D21021

llvm-svn: 283314
 2016-10-05 12:56:06 +00:00
Craig Topper c4a8228bcc [AVX-512] Use native IR for masked 512-bit add/sub/mul/div ps/pd intrinsics when rounding mode isn't used. 
llvm-svn: 283073
 2016-10-02 17:43:00 +00:00
Craig Topper 4910755107 [AVX-512] Add _MM_FROUND_NO_EXC to test cases that pass a rounding mode intrinsics. This is preparation for a follow up commit that will check validity of rounding mode argument. 
llvm-svn: 283053
 2016-10-01 21:03:46 +00:00
Elad Cohen b107a22afb [X86] Remove the mm_malloc.h include guard hack from the X86 builtins tests 
The X86 clang/test/CodeGen/*builtins.c tests define the mm_malloc.h include
guard as a hack for avoiding its inclusion (mm_malloc.h requires a hosted
environment since it expects stdlib.h to be available - which is not the case
in these internal clang codegen tests).
This patch removes this hack and instead passes -ffreestanding to clang cc1.

Differential Revision: https://reviews.llvm.org/D24825

llvm-svn: 282581
 2016-09-28 11:59:09 +00:00
Ayman Musa 2e250e8845 [avx512] Add aliases to some missing avx512 intrinsics. 
Differential Revision:https: //reviews.llvm.org/D24961

llvm-svn: 282488
 2016-09-27 14:06:32 +00:00
Craig Topper 5fbabd77c7 [X86] Fix some illegal rounding modes in some builtin test cases to ones that would properly compile to valid assembly. 
llvm-svn: 282137
 2016-09-22 06:13:33 +00:00
Craig Topper f43e4a1728 [AVX-512] Remove masked integer mullo builtins and replace with native IR. 
llvm-svn: 280597
 2016-09-03 19:19:49 +00:00
Craig Topper 0e18976b8d [AVX-512] Remove masked integer add/sub builtins and replace with native IR. 
llvm-svn: 280596
 2016-09-03 18:29:35 +00:00
Asaf Badouh 2f344b788c [AVX512] integer comparisions enumeration. 
fix Bug 28842 https://llvm.org/bugs/show_bug.cgi?id=28842

Differential Revision: https://reviews.llvm.org/D22212

 

llvm-svn: 277955
 2016-08-07 10:43:04 +00:00
Eric Christopher abb2b54ad3 After PR28761 use -Wall with -Werror in builtins tests to identify 
possible problems in headers.

llvm-svn: 277696
 2016-08-04 06:02:50 +00:00
Craig Topper 45db56c375 [X86] Add missing __x86_64__ qualifiers on a bunch of intrinsics that assume 64-bit GPRs are available. 
Usages of these intrinsics in a 32-bit build results in assertions in the backend.

llvm-svn: 276249
 2016-07-21 07:38:39 +00:00
Craig Topper 4d61a3c2d8 [AVX512] Replace masked AND/OR/XOR intrinsics with native code and remove the builtins. 
llvm-svn: 275049
 2016-07-11 06:14:18 +00:00
Craig Topper 6e76fb61a7 [X86] Use __butilin_shufflevector for 512-bit shufps intrinsics. 
llvm-svn: 275012
 2016-07-10 05:57:21 +00:00
Simon Pilgrim f5a8837e1b [X86][AVX512] Converted the VBROADCAST intrinsics to generic IR 
llvm-svn: 274544
 2016-07-05 12:59:33 +00:00
Asaf Badouh 136332888a [X86][AVX512F] add float/double abs intrinsics 
add abs intrinsics that use native LLVM-IR.
change _mm512_mask[z]_and_epi{32|64} to use select intrinsic

Differential Revision: http://reviews.llvm.org/D21973

llvm-svn: 274542
 2016-07-05 12:24:14 +00:00
Craig Topper 2a383c9273 [X86] Use undefined instead of setzero in shufflevector based intrinsics when the second source is unused. Rewrite immediate extractions in shuffle intrinsics to be in ((c >> x) & y) form instead of ((c & z) >> x). This way only x varies between each use instead of having to vary x and z. 
llvm-svn: 274525
 2016-07-04 22:18:01 +00:00
Simon Pilgrim 427154db2a [X86][AVX512] Converted the VSHUFPD intrinsics to generic IR 
llvm-svn: 274523
 2016-07-04 21:30:47 +00:00
Simon Pilgrim 30db811526 [X86][AVX512] Converted the VPERMPD/VPERMQ intrinsics to generic IR 
llvm-svn: 274502
 2016-07-04 13:34:44 +00:00
Simon Pilgrim 17388f2569 [X86][AVX512] Converted the VPERMILPD/VPERMILPS intrinsics to generic IR 
llvm-svn: 274492
 2016-07-04 11:06:15 +00:00
Simon Pilgrim 275d721485 [X86][AVX512] Converted the MOVDDUP/MOVSLDUP/MOVSHDUP masked intrinsics to generic IR 
llvm companion patch imminent

llvm-svn: 274442
 2016-07-02 17:16:25 +00:00
Artur Pilipenko 70d4bb566c Update the expected masked load/store intrinsics names in tests 
The mangling of their names was changed in order to support arbitrary addrspace pointers as arguments in rL274043.

llvm-svn: 274044
 2016-06-28 18:28:45 +00:00
Craig Topper 79f53ca0b5 [AVX512] Replace masked unpack builtins with shufflevector and selects. 
llvm-svn: 273533
 2016-06-23 06:36:42 +00:00
Craig Topper d1691c7026 [AVX512] Replace masked integer cmp and ucmp builtins with native IR. 
llvm-svn: 273378
 2016-06-22 04:47:58 +00:00
Craig Topper a54c21e742 [AVX512] Use native IR for mask pcmpeq/pcmpgt intrinsics. 
llvm-svn: 272787
 2016-06-15 14:06:34 +00:00
Michael Zuckerman 223676d2cc [Clang][AVX512][intrinsics] Adding missing intrinsics div_pd and div_ps 
Differential Revision: http://reviews.llvm.org/D20626

llvm-svn: 272658
 2016-06-14 12:38:58 +00:00
Asaf Badouh 880f0c252b [X86][AVX512F] bugfix - sqrtps should get __mask16 as mask parameter 
CR: Michael Zuckerman
llvm-svn: 272549
 2016-06-13 15:15:57 +00:00
Simon Pilgrim beca5f295c [Clang][X86] Convert non-temporal store builtins to generic __builtin_nontemporal_store in headers 
We can now use __builtin_nontemporal_store instead of target specific builtins for naturally aligned nontemporal stores which avoids the need for handling in CGBuiltin.cpp

The scalar integer nontemporal (unaligned) store builtins will have to wait as __builtin_nontemporal_store currently assumes natural alignment and doesn't accept the 'packed struct' trick that we use for normal unaligned load/stores.

The nontemporal loads require further backend support before we can safely convert them to __builtin_nontemporal_load

Differential Revision: http://reviews.llvm.org/D21272

llvm-svn: 272540
 2016-06-13 09:57:52 +00:00
Craig Topper 7cc9263ec2 [AVX512] Implement masked and 512-bit pshufd intrinsics directly with __builtin_shufflevector and __builtin_ia32_select. 
llvm-svn: 272467
 2016-06-11 12:50:19 +00:00
Igor Breger aadb876200 [AVX512] Emit select instruction instead of using x86 specific instrinsics. 
This will allow us to remove the x86 instrinics from the backend.

Differential Revision: http://reviews.llvm.org/D21060

llvm-svn: 272141
 2016-06-08 13:59:20 +00:00
Michael Zuckerman 95721ac863 [Clang][AVX512]Adding set4 intrinsics 
Differential Revision: http://reviews.llvm.org/D20866

llvm-svn: 271835
 2016-06-05 15:43:30 +00:00
Michael Zuckerman f36f6eb036 [Clang][AVX512][Intrinsics] Adding two definitions _mm512_setzero and _mm512_setzero_epi32 
Differential Revision: http://reviews.llvm.org/D20871

llvm-svn: 271832
 2016-06-05 15:12:52 +00:00
Asaf Badouh 89f657611c [X86][AVX512] add intrinsics of Scalar FP to integer 
Differential Revision: http://reviews.llvm.org/D20861

llvm-svn: 271499
 2016-06-02 08:11:35 +00:00
Michael Zuckerman 6170c15fc6 [Clang][Intrinsics][avx512] Continue Adding round cvt to clang 
And remove trailing spaces in intrinsic f test
Differential Revision: http://reviews.llvm.org/D20810

llvm-svn: 271398
 2016-06-01 14:41:41 +00:00
Michael Zuckerman e6aa66a53d [Clang][Intrinsics][avx512] Adding round intrinsics fot max/min/sqrt instruction set to clang 
Differential Revision: http://reviews.llvm.org/D20812

llvm-svn: 271373
 2016-06-01 08:34:03 +00:00
Michael Zuckerman c301c194ec [Clang][Intrinsics][avx512] Adding round roundscale to clang 
Differential Revision: http://reviews.llvm.org/D20815

llvm-svn: 271368
 2016-06-01 07:35:44 +00:00
Michael Zuckerman 186d86738d [Clang][Intrinsics][avx512] Adding round cvt to clang 
Differential Revision: http://reviews.llvm.org/D20790

llvm-svn: 271265
 2016-05-31 11:27:34 +00:00
Craig Topper 4b060e31c9 [AVX512] Convert masked load builtins to generic masked load intrinsics instead of the x86 specific ones. 
This will allow the x86 intrinsics to be removed from the backend.

llvm-svn: 271253
 2016-05-31 06:58:07 +00:00
Craig Topper 6e891fbdd2 [AVX512] Emit generic masked store instrinsics instead of using x86 specific intrinsics. 
This will allow us to remove the x86 instrinics from the backend.

llvm-svn: 271246
 2016-05-31 01:50:10 +00:00
Michael Zuckerman 9fcf3552ad [Clang][avx512][builtin] Adding missing intrinsics for cvt 
Differential Revision: http://reviews.llvm.org/D20618

llvm-svn: 271205
 2016-05-30 13:22:12 +00:00
Craig Topper cbdbbac875 [AVX512] Add masked v16i32 and v8i64 unaligned store tests. 
llvm-svn: 271134
 2016-05-28 18:59:06 +00:00
Michael Zuckerman 22c47e606a Adding missing _mm512_castsi512_si256 intrinsic. 
llvm-svn: 270851
 2016-05-26 14:32:11 +00:00
Michael Zuckerman 6f08cebf36 [Clang][AVX512][BUILTIN] Adding intrinsics for set1 
Differential Revision: http://reviews.llvm.org/D20562

llvm-svn: 270825
 2016-05-26 06:54:52 +00:00
Benjamin Kramer 1f4381f810 [AVX512] Don't rely on value names. They're different in release builds. 
llvm-svn: 270704
 2016-05-25 14:30:01 +00:00
Michael Zuckerman d5cc6cd262 [Clang][AVX512][BUILTIN] Add missing intrinsics for cast 
Differential Revision: http://reviews.llvm.org/D20523

llvm-svn: 270699
 2016-05-25 14:04:21 +00:00
Michael Zuckerman e6542002fc [Clang][AVX512][BUILTIN]adding missing intrinsics for movdaq instruction set 
Differential Revision: http://reviews.llvm.org/D20514

llvm-svn: 270401
 2016-05-23 08:01:48 +00:00
Benjamin Kramer 504c01cc67 Don't rely on value numbers in test, those are fragile and change in Release (no asserts) builds. 
llvm-svn: 270085
 2016-05-19 17:57:35 +00:00
Michael Zuckerman 178113e8cc [Clang][AVX512][intrinsics] continue completing missing set intrinsics 
Differential Revision: http://reviews.llvm.org/D20160

llvm-svn: 270047
 2016-05-19 12:07:49 +00:00
Michael Zuckerman 2cacc35343 [Clang][AVX512] completing missing intrinsics [pandnd]. 
Differential Revision: http://reviews.llvm.org/D20101

llvm-svn: 269939
 2016-05-18 15:25:53 +00:00
Craig Topper dbbe4a5542 [AVX512] Fix return types in several test cases to match the intrinsic they're testing. 
llvm-svn: 269738
 2016-05-17 04:41:32 +00:00
Michael Zuckerman bf05a4589e [Clang][AVX512] completing missing intrinsics for [vpabs] instruction set 
Differential Revision: http://reviews.llvm.org/D20069

llvm-svn: 269680
 2016-05-16 18:57:24 +00:00
Michael Zuckerman cb85677471 [Clang][AVX512] completing missing intrinsics [vsqrt|vrsqrt|vrcp14 ]. 
Differential Revision: http://reviews.llvm.org/D20068

llvm-svn: 269649
 2016-05-16 11:42:01 +00:00
Craig Topper 9c6c85f1ad [AVX512] Add typecasts to some intrinsics to avoid doing operations on the __m512/__m512i/__m512d types. 
llvm-svn: 269631
 2016-05-16 06:38:36 +00:00
Craig Topper e5cc18054a [AVX512] Use correct types in test case. 
llvm-svn: 269622
 2016-05-16 01:09:19 +00:00
Craig Topper dca1f230ae [AVX512] Add intrinsics for 512-bit insertf32x8/insertf32x4/inserti32x4. 
llvm-svn: 269617
 2016-05-15 21:26:20 +00:00
Michael Zuckerman 13d3c002df [clang][AVX512] completing missing set intrinsics 
Differential Revision: http://reviews.llvm.org/D20099

llvm-svn: 269172
 2016-05-11 11:41:29 +00:00
Michael Zuckerman 5e2c6b6200 [clang][AVX512] completing missing intrinsics for [vpermt2d|vptestm] instruction set. 
Differential Revision: http://reviews.llvm.org/D20096

llvm-svn: 269170
 2016-05-11 11:21:18 +00:00
NAKAMURA Takumi d4fbaef2b0 clang/test/CodeGen/avx512f-builtins.c: Fix for -Asserts. 
llvm-svn: 269079
 2016-05-10 17:16:12 +00:00
Michael Zuckerman e9e8e573e3 [Clang][AVX512] completing missing intrinsics [load/store] 
Differential Revision: http://reviews.llvm.org/D20063

llvm-svn: 269056
 2016-05-10 13:13:54 +00:00
Michael Zuckerman de860e5585 [Clang][AVX512] completing missing intrinsics [vmin/vmax]{sd|sq|uq|ud}. 
Differential Revision: http://reviews.llvm.org/D20064

llvm-svn: 269042
 2016-05-10 11:34:19 +00:00
Michael Zuckerman 2564d2f5fe [Clang][AVX512] completing missing intrinsics [vextractf]. 
Differential Revision: http://reviews.llvm.org/D20061

llvm-svn: 269037
 2016-05-10 10:14:50 +00:00
Michael Zuckerman 7360d8a9cc [Clang][AVX512] completing missing intrinsics [roundscale, ceil, floor] 
Differential Revision: http://reviews.llvm.org/D20070

llvm-svn: 269022
 2016-05-10 07:30:58 +00:00
Michael Zuckerman f9be3bb1d5 [clang][AVX512] completing missing intrinsics [vmin/vmax]. 
Differential Revision: http://reviews.llvm.org/D20062

llvm-svn: 268910
 2016-05-09 12:38:49 +00:00
Michael Zuckerman f15447537f [Clang][AVX512] completing missing intrinsics [CVT] 
Differential Revision: http://reviews.llvm.org/D20056

llvm-svn: 268903
 2016-05-09 10:32:51 +00:00
Michael Zuckerman e6f7389b5a [Clang][Builtin][AVX512] Adding intrinsics fot cvt{u}si2s{d|s} cvt{sd|ss}2{ss|sd} instruction set 
Differential Revision: http://reviews.llvm.org/D19765

llvm-svn: 268481
 2016-05-04 08:55:11 +00:00
Pete Cooper 71dfcb42eb Change test to use regex instead of explicit value numbers. NFC. 
We were seeing an internal failure when running this test.  I can't
see a good reason for the difference, but the simple fix is to use
%{{.*}} instead of %1.

llvm-svn: 268416
 2016-05-03 18:32:01 +00:00