6 Commits

Author	SHA1	Message	Date
Shiva Chen	7c17242b92	[RISCV] Implement c.lui immediate operand constraint ... Implement c.lui immediate constraint to [1, 31] and [0xfffe0, 0xfffff]. The RISC-V ISA describes the constraint as [1, 63], with that value being loaded in to bits 17-12 of the destination register and sign extended from bit 17. Therefore, this 6-bit immediate can represent values in the ranges [1, 31] and [0xfffe0, 0xfffff]. Differential Revision: https://reviews.llvm.org/D42834 llvm-svn: 325792	2018-02-22 15:02:28 +00:00
Shiva Chen	b22c1d29bc	[RISCV] Fix c.addi and c.addi16sp immediate constraints which should be non-zero ... Differential Revision: https://reviews.llvm.org/D42782 llvm-svn: 324055	2018-02-02 02:43:23 +00:00
Alex Bradbury	0ad4c265d7	[RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero ... c.slli/c.srli/c.srai allow a 5-bit shift in RV32C and a 6-bit shift in RV64C. This patch adds uimmlog2xlennonzero to reflect this constraint as well as tests. Differential Revision: https://reviews.llvm.org/D41216 Patch by Shiva Chen. llvm-svn: 320799	2017-12-15 10:20:51 +00:00
Alex Bradbury	60714f98ba	[RISCV] MC layer support for the remaining RVC instructions ... Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558	2017-12-13 09:32:55 +00:00
Alex Bradbury	f8f4b90544	[RISCV] MC layer support for the jump/branch instructions of the RVC extension ... Differential Revision: https://reviews.llvm.org/D40002 Patch by Shiva Chen. llvm-svn: 320038	2017-12-07 13:19:57 +00:00
Alex Bradbury	9f6aec4b7a	[RISCV] MC layer support for load/store instructions of the C (compressed) extension ... Differential Revision: https://reviews.llvm.org/D40001 Patch by Shiva Chen. llvm-svn: 320037	2017-12-07 12:50:32 +00:00