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Author SHA1 Message Date
Quentin Colombet b51a68681a During SelectionDAG building explicitly set a node to constant zero when the 
value is zero.
This allows optmizations to kick in more easily.
Fix some test cases so that they remain meaningful (i.e., not completely dead
coded) when optimizations apply.

<rdar://problem/14096009> superfluous multiply by high part of zero-extended
value.

llvm-svn: 184222
 2013-06-18 20:14:39 +00:00
David Blaikie 0252265be0 Debug Info: Simplify Frame Index handling in DBG_VALUE Machine Instructions 
Rather than using the full power of target-specific addressing modes in
DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This
reduces the complexity of debug info handling down to two
representations of values (reg+offset and frame index+offset) rather
than three or four.

Ideally we could ensure that frame indicies had been eliminated by the
time we reached an assembly or dwarf generation, but I haven't spent the
time to figure out where the FIs are leaking through into that & whether
there's a good place to convert them. Some FI+offset=>reg+offset
conversion is done (see PrologEpilogInserter, for example) which is
necessary for some SelectionDAG assumptions about registers, I believe,
but it might be possible to make this a more thorough conversion &
ensure there are no remaining FIs no matter how instruction selection
is performed.

llvm-svn: 184066
 2013-06-16 20:34:15 +00:00
Stephen Lin 605207fe75 SelectionDAG: slightly refactor DAGCombiner::visitSELECT_CC to avoid redudant checks... 
This doesn't really effect performance due to all the relevant calls being transparent but is clearer. 

llvm-svn: 184027
 2013-06-15 04:03:33 +00:00
Matt Arsenault d2f0332a29 Introduce getSelect usage and use more getSelectCC 
llvm-svn: 184012
 2013-06-14 22:04:37 +00:00
Stephen Lin 4e69d01b67 SelectionDAG: minor fix to order of operands in comments to match the code 
llvm-svn: 184008
 2013-06-14 21:33:58 +00:00
Stephen Lin e31f2d2d54 SelectionDAG: Fix incorrect condition checks in some cases of folding FADD/FMUL combinations; also improve accuracy of comments 
llvm-svn: 183993
 2013-06-14 18:17:35 +00:00
David Majnemer 0fc8670cb0 TargetLowering: Clean up method description comments 
llvm-svn: 183623
 2013-06-08 23:51:45 +00:00
Bill Wendling f77190855d Cache the TargetLowering info object as a pointer. 
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.

llvm-svn: 183361
 2013-06-06 00:43:09 +00:00
Bill Wendling 8db01cb262 Don't cache the TargetLoweringInfo object inside of the FunctionLowering object. 
The TargetLoweringInfo object is owned by the TargetMachine. In the future, the
TargetMachine object may change, which may also change the TargetLoweringInfo
object.

llvm-svn: 183356
 2013-06-06 00:11:39 +00:00
Andrew Trick ad6d08ac6f Order CALLSEQ_START and CALLSEQ_END nodes. 
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.

Patch by Xiaoyi Guo!

This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.

llvm-svn: 182885
 2013-05-29 22:03:55 +00:00
Benjamin Kramer 262b154247 Simplify code. No functionality change. 
llvm-svn: 182779
 2013-05-28 16:39:36 +00:00
Benjamin Kramer 351d53c225 Remove double semicolons. 
llvm-svn: 182778
 2013-05-28 16:31:26 +00:00
Preston Gurd 048f99de11 Convert sqrt functions into sqrt instructions when -ffast-math is in effect. 
When -ffast-math is in effect (on Linux, at least), clang defines
__FINITE_MATH_ONLY__ > 0 when including <math.h>. This causes the
preprocessor to include <bits/math-finite.h>, which renames the sqrt functions.
For instance, "sqrt" is renamed as "__sqrt_finite". 

This patch adds the 3 new names in such a way that they will be treated
as equivalent to their respective original names.

llvm-svn: 182739
 2013-05-27 15:44:35 +00:00
Andrew Trick c66d26adf0 Fix PR16143: Insert DEBUG_VALUE before terminator. 
llvm-svn: 182717
 2013-05-26 08:58:50 +00:00
Andrew Trick e2431c64bc Track IR ordering of SelectionDAG nodes 3/4. 
Remove the old IR ordering mechanism and switch to new one.  Fix unit
test failures.

llvm-svn: 182704
 2013-05-25 03:08:10 +00:00
Andrew Trick ef9de2a739 Track IR ordering of SelectionDAG nodes 2/4. 
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

llvm-svn: 182703
 2013-05-25 02:42:55 +00:00
Andrew Trick 175143bf88 Track IR ordering of SelectionDAG nodes 1/4. 
Use a field in the SelectionDAGNode object to track its IR ordering.
This adds fields and utility classes without changing existing
interfaces or functionality.

llvm-svn: 182701
 2013-05-25 02:20:36 +00:00
Michael J. Spencer df1ecbd734 Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros. 
llvm-svn: 182680
 2013-05-24 22:23:49 +00:00
Adrian Prantl 0d1e5592a6 Unify formatting of debug output. 
llvm-svn: 182495
 2013-05-22 18:02:19 +00:00
Justin Holewinski fff1f5f5e2 Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen. 
The intrinsic calls are dropped, but the annotated value is propagated.

Fixes PR 15253

Original patch by Zeng Bin!

llvm-svn: 182387
 2013-05-21 14:37:16 +00:00
Benjamin Kramer 8aaf197990 DAGCombine: Avoid an edge case where it tried to create an i0 type for (x & 0) == 0. 
Fixes PR16083.

llvm-svn: 182357
 2013-05-21 08:51:09 +00:00
Matt Arsenault 75865923c9 Add LLVMContext argument to getSetCCResultType 
llvm-svn: 182180
 2013-05-18 00:21:46 +00:00
Matt Arsenault 04126234e5 Replace redundant code 
Use EVT::changeExtendedVectorElementTypeToInteger instead of doing the
same thing that it does

llvm-svn: 182165
 2013-05-17 21:43:43 +00:00
Matt Arsenault 52ddb7bcdd Add missing -*- C++ -*- to headers 
llvm-svn: 182164
 2013-05-17 21:43:39 +00:00
Adrian Prantl 9c93059aa4 Generate debug info for by-value struct args even if they are not used. 
radar://problem/13865940

llvm-svn: 182062
 2013-05-16 23:44:12 +00:00
Benjamin Kramer fc88c3761f DAGCombine: Also shrink eq compares where the constant is exactly as large as the smaller type. 
if ((x & 255) == 255)

before: movzbl  %al, %eax
        cmpl  $255, %eax

after:  cmpb  $-1, %al
llvm-svn: 182038
 2013-05-16 18:47:58 +00:00
Hal Finkel 1f6a7f53d8 Fix legalization of SETCC with promoted integer intrinsics 
If the input operands to SETCC are promoted, we need to make sure that we
either use the promoted form of both operands (or neither); a mixture is not
allowed. This can happen, for example, if a target has a custom promoted
i1-returning intrinsic (where i1 is not a legal type). In this case, we need to
use the promoted form of both operands.

This change only augments the behavior of the existing logic in the case where
the input types (which may or may not have already been legalized) disagree,
and should not affect existing target code because this case would otherwise
cause an assert in the SETCC operand promotion code.

This will be covered by (essentially all of the) tests for the new PPCCTRLoops
infrastructure.

llvm-svn: 181926
 2013-05-15 21:37:27 +00:00
Bob Wilson c5c0823724 Remove redundant variable introduced by r181682. 
llvm-svn: 181721
 2013-05-13 19:02:31 +00:00
Hao Liu bc60196951 Fix PR15950 A bug in DAG Combiner about undef mask 
llvm-svn: 181682
 2013-05-13 02:07:05 +00:00
Benjamin Kramer a5d59333b3 DAGCombiner: Generate a correct constant for vector types when folding (xor (and)) into (and (not)). 
PR15948.

llvm-svn: 181597
 2013-05-10 14:09:52 +00:00
Owen Anderson 32baf99b1d Teach SelectionDAG to constant fold all-constant FMA nodes the same way that it constant folds FADD, FMUL, etc. 
llvm-svn: 181555
 2013-05-09 22:27:13 +00:00
David Majnemer 386ab7f872 DAGCombiner: Simplify inverted bit tests 
Fold (xor (and x, y), y) -> (and (not x), y)

This removes an opportunity for a constant to appear twice.

llvm-svn: 181395
 2013-05-08 06:44:42 +00:00
Matt Arsenault a5733dc97e Fix vselect when getSetCCResultType returns a different type from the operands 
llvm-svn: 181348
 2013-05-07 20:24:18 +00:00
Michael Kuperstein ac868757d0 Fix slightly too aggressive conact_vector optimization. 
(Would sometimes optimize away conacts used to extend a vector with undef values)

llvm-svn: 181186
 2013-05-06 08:06:13 +00:00
Dmitri Gribenko 3238fb7595 Add ArrayRef constructor from None, and do the cleanups that this constructor enables 
Patch by Robert Wilhelm.

llvm-svn: 181138
 2013-05-05 00:40:33 +00:00
Chad Rosier 8e4824f350 [inline asm] Return an undef SDValue of the expected value type, rather than 
report a fatal error.  This allows us to continue processing the translation
unit.  Test case to come on the clang side because we need an inline asm
diagnostics handler in place.
rdar://13446483

llvm-svn: 180873
 2013-05-01 19:49:26 +00:00
Nadav Rotem e5a2dda372 Optimize away nop CONCAT_VECTOR nodes. 
Optimize CONCAT_VECTOR nodes that merge EXTRACT_SUBVECTOR values that extract from the same vector.

rdar://13402653
PR15866

llvm-svn: 180871
 2013-05-01 19:18:51 +00:00
Stephen Lin 699808ceb2 Only pass 'returned' to target-specific lowering code when the value of entire register is guaranteed to be preserved. 
llvm-svn: 180825
 2013-04-30 22:49:28 +00:00
Adrian Prantl a2888e71eb Temporarily revert "Change the informal convention of DBG_VALUE so that we can express a" 
because it breaks some buildbots.

This reverts commit 180816.

llvm-svn: 180819
 2013-04-30 22:35:14 +00:00
Adrian Prantl 9a576644e4 Change the informal convention of DBG_VALUE so that we can express a 
register-indirect address with an offset of 0.
It used to be that a DBG_VALUE is a register-indirect value if the offset
(operand 1) is nonzero. The new convention is that a DBG_VALUE is
register-indirect if the first operand is a register and the second
operand is an immediate. For plain registers use the combination reg, reg.

rdar://problem/13658587

llvm-svn: 180816
 2013-04-30 22:16:46 +00:00
Silviu Baranga af7e8c367f Re-write the address propagation code for pre-indexed loads/stores to take into account some previously misssed cases (PRE_DEC addressing mode, the offset and base address are swapped, etc). This should fix PR15581. 
llvm-svn: 180609
 2013-04-26 15:52:24 +00:00
Benjamin Kramer d56ffc709d DAGCombiner: Canonicalize vector integer abs in the same way we do it for scalars. 
This already helps SSE2 x86 a lot because it lacks an efficient way to
represent a vector select. The long term goal is to enable the backend to match
a canonicalized pattern into a single instruction (e.g. vabs or pabs).

llvm-svn: 180597
 2013-04-26 09:19:19 +00:00
Silviu Baranga 4ad2bc5963 Fix constant folding for one lane vector types. Constant folding one lane vector types not returns a vector instead of a scalar. 
llvm-svn: 180254
 2013-04-25 09:32:33 +00:00
Chad Rosier 108d5a61b7 [inline asm] Fix a crasher for an invalid value type/register class. 
rdar://13731657

llvm-svn: 180226
 2013-04-24 22:53:10 +00:00
Owen Anderson 2d4cca35c3 DAGCombine should not aggressively fold SEXT(VSETCC(...)) into a wider VSETCC without first checking the target's vector boolean contents. 
This exposed an issue with PowerPC AltiVec where it appears it was setting the wrong vector boolean contents.  The included change
fixes the PowerPC tests, and was OK'd by Hal.

llvm-svn: 180129
 2013-04-23 18:09:28 +00:00
Jim Grosbach 563983c8a3 Legalize vector truncates by parts rather than just splitting. 
Rather than just splitting the input type and hoping for the best, apply
a bit more cleverness. Just splitting the types until the source is
legal often leads to an illegal result time, which is then widened and a
scalarization step is introduced which leads to truly horrible code
generation. With the loop vectorizer, these sorts of operations are much
more common, and so it's worth extra effort to do them well.

Add a legalization hook for the operands of a TRUNCATE node, which will
be encountered after the result type has been legalized, but if the
operand type is still illegal. If simple splitting of both types
ends up with the result type of each half still being legal, just
do that (v16i16 -> v16i8 on ARM, for example). If, however, that would
result in an illegal result type (v8i32 -> v8i8 on ARM, for example),
we can get more clever with power-two vectors. Specifically,
split the input type, but also widen the result element size, then
concatenate the halves and truncate again.  For example on ARM,
To perform a "%res = v8i8 trunc v8i32 %in" we transform to:
  %inlo = v4i32 extract_subvector %in, 0
  %inhi = v4i32 extract_subvector %in, 4
  %lo16 = v4i16 trunc v4i32 %inlo
  %hi16 = v4i16 trunc v4i32 %inhi
  %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
  %res = v8i8 trunc v8i16 %in16

This allows instruction selection to generate three VMOVN instructions
instead of a sequences of moves, stores and loads.

Update the ARMTargetTransformInfo to take this improved legalization
into account.

Consider the simplified IR:

define <16 x i8> @test1(<16 x i32>* %ap) {
  %a = load <16 x i32>* %ap
  %tmp = trunc <16 x i32> %a to <16 x i8>
  ret <16 x i8> %tmp
}

define <8 x i8> @test2(<8 x i32>* %ap) {
  %a = load <8 x i32>* %ap
  %tmp = trunc <8 x i32> %a to <8 x i8>
  ret <8 x i8> %tmp
}

Previously, we would generate the truly hideous:
	.syntax unified
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_test1
	.align	2
_test1:                                 @ @test1
@ BB#0:
	push	{r7}
	mov	r7, sp
	sub	sp, sp, #20
	bic	sp, sp, #7
	add	r1, r0, #48
	add	r2, r0, #32
	vld1.64	{d24, d25}, [r0:128]
	vld1.64	{d16, d17}, [r1:128]
	vld1.64	{d18, d19}, [r2:128]
	add	r1, r0, #16
	vmovn.i32	d22, q8
	vld1.64	{d16, d17}, [r1:128]
	vmovn.i32	d20, q9
	vmovn.i32	d18, q12
	vmov.u16	r0, d22[3]
	strb	r0, [sp, #15]
	vmov.u16	r0, d22[2]
	strb	r0, [sp, #14]
	vmov.u16	r0, d22[1]
	strb	r0, [sp, #13]
	vmov.u16	r0, d22[0]
	vmovn.i32	d16, q8
	strb	r0, [sp, #12]
	vmov.u16	r0, d20[3]
	strb	r0, [sp, #11]
	vmov.u16	r0, d20[2]
	strb	r0, [sp, #10]
	vmov.u16	r0, d20[1]
	strb	r0, [sp, #9]
	vmov.u16	r0, d20[0]
	strb	r0, [sp, #8]
	vmov.u16	r0, d18[3]
	strb	r0, [sp, #3]
	vmov.u16	r0, d18[2]
	strb	r0, [sp, #2]
	vmov.u16	r0, d18[1]
	strb	r0, [sp, #1]
	vmov.u16	r0, d18[0]
	strb	r0, [sp]
	vmov.u16	r0, d16[3]
	strb	r0, [sp, #7]
	vmov.u16	r0, d16[2]
	strb	r0, [sp, #6]
	vmov.u16	r0, d16[1]
	strb	r0, [sp, #5]
	vmov.u16	r0, d16[0]
	strb	r0, [sp, #4]
	vldmia	sp, {d16, d17}
	vmov	r0, r1, d16
	vmov	r2, r3, d17
	mov	sp, r7
	pop	{r7}
	bx	lr

	.globl	_test2
	.align	2
_test2:                                 @ @test2
@ BB#0:
	push	{r7}
	mov	r7, sp
	sub	sp, sp, #12
	bic	sp, sp, #7
	vld1.64	{d16, d17}, [r0:128]
	add	r0, r0, #16
	vld1.64	{d20, d21}, [r0:128]
	vmovn.i32	d18, q8
	vmov.u16	r0, d18[3]
	vmovn.i32	d16, q10
	strb	r0, [sp, #3]
	vmov.u16	r0, d18[2]
	strb	r0, [sp, #2]
	vmov.u16	r0, d18[1]
	strb	r0, [sp, #1]
	vmov.u16	r0, d18[0]
	strb	r0, [sp]
	vmov.u16	r0, d16[3]
	strb	r0, [sp, #7]
	vmov.u16	r0, d16[2]
	strb	r0, [sp, #6]
	vmov.u16	r0, d16[1]
	strb	r0, [sp, #5]
	vmov.u16	r0, d16[0]
	strb	r0, [sp, #4]
	ldm	sp, {r0, r1}
	mov	sp, r7
	pop	{r7}
	bx	lr

Now, however, we generate the much more straightforward:
	.syntax unified
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_test1
	.align	2
_test1:                                 @ @test1
@ BB#0:
	add	r1, r0, #48
	add	r2, r0, #32
	vld1.64	{d20, d21}, [r0:128]
	vld1.64	{d16, d17}, [r1:128]
	add	r1, r0, #16
	vld1.64	{d18, d19}, [r2:128]
	vld1.64	{d22, d23}, [r1:128]
	vmovn.i32	d17, q8
	vmovn.i32	d16, q9
	vmovn.i32	d18, q10
	vmovn.i32	d19, q11
	vmovn.i16	d17, q8
	vmovn.i16	d16, q9
	vmov	r0, r1, d16
	vmov	r2, r3, d17
	bx	lr

	.globl	_test2
	.align	2
_test2:                                 @ @test2
@ BB#0:
	vld1.64	{d16, d17}, [r0:128]
	add	r0, r0, #16
	vld1.64	{d18, d19}, [r0:128]
	vmovn.i32	d16, q8
	vmovn.i32	d17, q9
	vmovn.i16	d16, q8
	vmov	r0, r1, d16
	bx	lr

llvm-svn: 179989
 2013-04-21 23:47:41 +00:00
Jim Grosbach d4db72db61 Tidy up comment grammar. 
llvm-svn: 179986
 2013-04-21 21:23:01 +00:00
Tim Northover a2b533906a Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE. 
llvm-svn: 179939
 2013-04-20 12:32:17 +00:00
Stephen Lin b8bd232a3d Add CodeGen support for functions that always return arguments via a new parameter attribute 'returned', which is taken advantage of in target-independent tail call opportunity detection and in ARM call lowering (when placed on an integral first parameter). 
llvm-svn: 179925
 2013-04-20 05:14:40 +00:00
Eli Bendersky e80691dc0a Simplify the code in FastISel::tryToFoldLoad, add an assertion and fix a comment. 
llvm-svn: 179908
 2013-04-19 23:26:18 +00:00