db18938355
If a brcond condition is promoted, make sure to zero extend it, even if not
...
expanded into BR_CC.
llvm-svn: 31932
2006-11-27 04:39:56 +00:00
6c38f0bb07
For PR950:
...
The long awaited CAST patch. This introduces 12 new instructions into LLVM
to replace the cast instruction. Corresponding changes throughout LLVM are
provided. This passes llvm-test, llvm/test, and SPEC CPUINT2000 with the
exception of 175.vpr which fails only on a slight floating point output
difference.
llvm-svn: 31931
2006-11-27 01:05:10 +00:00
d7f53cdaec
Global label not handled correctly.
...
llvm-svn: 31883
2006-11-20 20:29:06 +00:00
3676a994ca
Fix PR1011 and CodeGen/Generic/2006-11-20-DAGCombineCrash.ll
...
llvm-svn: 31878
2006-11-20 18:05:46 +00:00
539df43e4b
setOperand should not zap the operand list or add implicit operands to an
...
instruction. Doing so breaks the FP stackifier, the alpha branch selector
the sparc fpmover.
This fixes PR1012 and CodeGen/X86/fp-stack-compare.ll
llvm-svn: 31876
2006-11-20 17:57:22 +00:00
d9436b6837
For PR950:
...
First in a series of patches to convert SetCondInst into ICmpInst and
FCmpInst using only two opcodes and having the instructions contain their
predicate value. Nothing uses these classes yet. More patches to follow.
llvm-svn: 31867
2006-11-20 01:22:35 +00:00
ea017f66f7
Don't transform in another bad case: if the block is empty, it should be
...
simplified before we do this xform so that our cost model is accurate.
llvm-svn: 31864
2006-11-18 22:25:39 +00:00
56ec81ff73
Fix another case we *don't* want to do this xform.
...
llvm-svn: 31861
2006-11-18 21:56:39 +00:00
ace542fa6c
Implement operator<< for machine basic blocks to make it easier to dump them.
...
llvm-svn: 31857
2006-11-18 21:47:36 +00:00
7acdc17fe4
make the previous change more aggressive, moving any block with no fallthrough.
...
This speeds up yacr2 by 7% on a core2.
llvm-svn: 31856
2006-11-18 21:30:35 +00:00
47ce26158f
Minor code layout tweak: if we have something like this:
...
if (cond) goto BB2
BB1:
...
return;
BB2:
...
Move BB1 to the end of the function so that the code falls through in the
non-return case. This has the effect of moving assert (and other no-return
call) bodies and return blocks out of loops.
llvm-svn: 31855
2006-11-18 20:47:54 +00:00
da0add3fd0
Fixing the ENABLE_OPTIMIZED=1 DISABLE_ASSERTIONS=1 build.
...
llvm-svn: 31822
2006-11-17 13:07:55 +00:00
9d46fcd59c
More removal of std::cerr and DEBUG, replacing with DOUT instead.
...
llvm-svn: 31806
2006-11-17 02:09:07 +00:00
d108b9a60d
Replace std::cerr uses of the "DEBUG" macro with "DOUT" instead. Removes
...
a #include of iostream.
llvm-svn: 31800
2006-11-17 00:50:36 +00:00
8969ebca44
*** empty log message ***
...
llvm-svn: 31789
2006-11-16 20:11:33 +00:00
9fd73b8a7f
Match MachineCodeEmitter changes.
...
llvm-svn: 31787
2006-11-16 20:04:04 +00:00
d811cc6818
Don't recompute getNumOperands for each iteration.
...
llvm-svn: 31783
2006-11-16 07:35:18 +00:00
c7969fd1e7
Added a new method "CreateNewLiveInterval" which, given a list of
...
LiveRanges, creates a new LiveInterval from them. The LiveRanges should
have existed already in another LiveInterval, but removed.
llvm-svn: 31780
2006-11-16 02:41:50 +00:00
e0a70388c2
enable the branch folding pass for the JIT.
...
llvm-svn: 31777
2006-11-16 01:00:07 +00:00
f64da389f8
Fix an incorrectly inverted condition.
...
llvm-svn: 31773
2006-11-16 00:08:20 +00:00
0ffff1c629
Match live variable changes.
...
llvm-svn: 31762
2006-11-15 20:55:15 +00:00
ebb0357b4c
Minor updates.
...
llvm-svn: 31761
2006-11-15 20:54:29 +00:00
12ea213de9
A register def can be partially dead when the whole register has use(s) but a subreg does not.
...
llvm-svn: 31760
2006-11-15 20:54:11 +00:00
70ec52896e
Do away with kill / dead maps. Move kill / dead info onto MI's.
...
llvm-svn: 31759
2006-11-15 20:51:59 +00:00
2775aba51d
Simplify IntrinsicLowering and clarify that it is only for use by the
...
CBE and interpreter.
llvm-svn: 31755
2006-11-15 18:00:10 +00:00
30d08801ef
remove dead #include
...
llvm-svn: 31753
2006-11-15 17:51:15 +00:00
dbd3d294e6
Matches MachineInstr changes.
...
llvm-svn: 31712
2006-11-13 23:36:35 +00:00
77af6ac5e8
- Let MachineInstr ctors add implicit def and use operands. Other operands
...
will be inserted before these operands. If the opcode changes (by
setOpcode), the implicit operands are updated as well.
- Added IsKill, IsDead fields to MachineOperand in preparation for changes
that move kill / dead info to MachineInstr's.
llvm-svn: 31711
2006-11-13 23:34:06 +00:00
2230144a75
Make an assert comment match the tested assertion.
...
llvm-svn: 31686
2006-11-11 20:07:59 +00:00
979bbf48d5
Add methods to add implicit def use operands to a MI.
...
llvm-svn: 31675
2006-11-11 10:20:02 +00:00
a0a8003f59
disallow preinc of a frameindex. This is not profitable and causes 2-addr
...
pass to explode. This fixes a bunch of llc-beta failures on ppc last night.
llvm-svn: 31661
2006-11-11 01:00:15 +00:00
eabc15c1d8
reduce indentation by using early exits. No functionality change.
...
llvm-svn: 31660
2006-11-11 00:56:29 +00:00
ffad2166e1
move big chunks of code out-of-line, no functionality change.
...
llvm-svn: 31658
2006-11-11 00:39:41 +00:00
4eac5f59e6
Fix a dag combiner bug exposed by my recent instcombine patch. This fixes
...
CodeGen/Generic/2006-11-10-DAGCombineMiscompile.ll and PPC gsm/toast
llvm-svn: 31644
2006-11-10 21:37:15 +00:00
8c9c6d71ed
Add implicit def / use operands to MachineInstr.
...
llvm-svn: 31633
2006-11-10 08:43:01 +00:00
13440b025c
When forming a pre-indexed store, make sure ptr isn't the same or is a pred of value being stored. It would cause a cycle.
...
llvm-svn: 31631
2006-11-10 08:28:11 +00:00
d5e604dbb2
commentate
...
llvm-svn: 31627
2006-11-10 04:41:34 +00:00
6878378390
Don't attempt expensive pre-/post- indexed dag combine if target does not support them.
...
llvm-svn: 31598
2006-11-09 19:10:46 +00:00
d550248f2c
Add a mechanism to specify whether a target supports a particular indexed load / store.
...
llvm-svn: 31597
2006-11-09 18:56:43 +00:00
c034f14fbe
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
...
llvm-svn: 31596
2006-11-09 18:44:21 +00:00
b15000736c
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
...
llvm-svn: 31595
2006-11-09 17:55:04 +00:00
f1606b80f1
Allows debugging llc self hosted.
...
llvm-svn: 31594
2006-11-09 16:32:26 +00:00
97f89b11b3
Merging dwarf info to a single compile unit.
...
llvm-svn: 31593
2006-11-09 14:52:14 +00:00
b58e06bc9e
getPostIndexedAddressParts change: passes in load/store instead of its loaded / stored VT.
...
llvm-svn: 31584
2006-11-09 04:29:46 +00:00
1698c2999c
Remove M_2_ADDR_FLAG.
...
llvm-svn: 31583
2006-11-09 02:22:54 +00:00
85e54223cd
Match more post-indexed ops.
...
llvm-svn: 31569
2006-11-08 20:27:27 +00:00
61feeb90f9
Remove redundant <cmath>.
...
llvm-svn: 31561
2006-11-08 19:16:44 +00:00
62bbc9ef58
Now can re-enable debug label folding.
...
llvm-svn: 31549
2006-11-08 14:17:45 +00:00
0303cb9b33
- When performing pre-/post- indexed load/store transformation, do not worry
...
about whether the new base ptr would be live below the load/store. Let two
address pass split it back to non-indexed ops.
- Minor tweaks / fixes.
llvm-svn: 31544
2006-11-08 08:30:28 +00:00
6072435756
Fixed a minor bug preventing some pre-indexed load / store transformation.
...
llvm-svn: 31543
2006-11-08 06:56:05 +00:00
fdff938a7e
For PR950:
...
This patch converts the old SHR instruction into two instructions,
AShr (Arithmetic) and LShr (Logical). The Shr instructions now are not
dependent on the sign of their operands.
llvm-svn: 31542
2006-11-08 06:47:33 +00:00
d48f7dd250
Fix a obscure post-indexed load / store dag combine bug.
...
llvm-svn: 31537
2006-11-08 02:38:55 +00:00
bf3b57f221
optimize single MBB loops better. In particular, produce:
...
LBB1_57: #bb207.i
movl 72(%esp), %ecx
movb (%ecx,%eax), %cl
movl 80(%esp), %edx
movb %cl, 1(%edx,%eax)
incl %eax
cmpl $143, %eax
jne LBB1_57 #bb207.i
jmp LBB1_64 #cond_next255.i
intead of:
LBB1_57: #bb207.i
movl 72(%esp), %ecx
movb (%ecx,%eax), %cl
movl 80(%esp), %edx
movb %cl, 1(%edx,%eax)
incl %eax
cmpl $143, %eax
je LBB1_64 #cond_next255.i
jmp LBB1_57 #bb207.i
This eliminates a branch per iteration of the loop. This hurted PPC
particularly, because the extra branch meant another dispatch group for each
iteration of the loop.
llvm-svn: 31530
2006-11-08 01:03:21 +00:00
21d4d895ca
Accidently reran commit.
...
llvm-svn: 31516
2006-11-07 21:58:55 +00:00
a919ba9abd
Missed a label map, reverting till covered.
...
llvm-svn: 31514
2006-11-07 21:37:31 +00:00
21ce53b94e
Missed a label map, reverting till covered.
...
llvm-svn: 31512
2006-11-07 20:53:05 +00:00
6ea4fae838
1. Add a pass to fold debug label instructions so a debug info client can detect
...
empty ranges.
2. Reorg how MachineDebugInfo maintains changes to debug labels.
3. Have dwarf writer use debug label info to simplify scopes and source line
coorespondence.
4. Revert the merging of compile units until I can get the bugs ironed out.
llvm-svn: 31507
2006-11-07 19:33:46 +00:00
b18177bfab
Enable improved spilling costs by default. This speeds up viterbi on x86
...
by 40%, FreeBench/fourinarow by 20%, and many other programs 10-25%.
On PPC, this speeds up fourinarow by 18%, and probably other things as well.
llvm-svn: 31504
2006-11-07 18:04:58 +00:00
6a9342166b
Use correct value for float HUGH_VAL.
...
llvm-svn: 31500
2006-11-07 12:25:45 +00:00
60c6846d21
Add post-indexed load / store transformations.
...
llvm-svn: 31498
2006-11-07 09:03:05 +00:00
01d039cc44
Add a new llcbeta option. This speeds up viterbi from 12.34 to 8.76s on
...
X86. If happy, I'll enable this by default.
llvm-svn: 31493
2006-11-07 07:18:40 +00:00
78c84a0328
Unbreak X86/ELF Debugging. Somehow this line got lost in Jim's cleanup.
...
llvm-svn: 31492
2006-11-07 06:36:36 +00:00
94c231f453
Fix PR988 and CodeGen/Generic/2006-11-06-MemIntrinsicExpand.ll.
...
The low part goes in the first operand of expandop, not the second one.
llvm-svn: 31487
2006-11-07 04:11:44 +00:00
f24d15f969
Remove dead code; added a missing null ptr check.
...
llvm-svn: 31478
2006-11-06 21:33:46 +00:00
235aeef9e1
Tab interferes with uniqueness.
...
NOTE: There doesn't seem to be consistency for whether a leading tab
is present in a section heading.
llvm-svn: 31475
2006-11-06 16:23:59 +00:00
f39064c2de
D'oh - reversed logic.
...
llvm-svn: 31474
2006-11-06 13:20:29 +00:00
eb99bd736a
Add comment.
...
llvm-svn: 31473
2006-11-06 08:14:30 +00:00
7d6f3db3e2
Unbreak VC++ build.
...
llvm-svn: 31464
2006-11-05 19:31:28 +00:00
33157700d9
Added pre-indexed store support.
...
llvm-svn: 31459
2006-11-05 09:31:14 +00:00
1a1e23eff7
Added getIndexedStore.
...
llvm-svn: 31458
2006-11-05 09:30:09 +00:00
01c55a50b1
Live local variables are being dropped because the begin or end labels marking
...
their scope are being deleted. Workaround is to widen scope to full function.
llvm-svn: 31454
2006-11-04 10:48:07 +00:00
fd2c5dd806
Changes to use operand constraints to process two-address instructions.
...
llvm-svn: 31453
2006-11-04 09:44:31 +00:00
51733ed4a3
Fixed some spiller bugs exposed by the recent two-address code changes. Now
...
there may be other def(s) apart from the use&def two-address operand. We need
to check if the register reuse for a use&def operand may conflicts with another
def. Provide a mean to recover from the conflict if it is detected when the
defs are processed later.
llvm-svn: 31439
2006-11-04 00:21:55 +00:00
bb3ea2a437
this will work better
...
llvm-svn: 31419
2006-11-03 19:15:55 +00:00
a35f8c16c4
Fix the build on xcode < 2.4
...
llvm-svn: 31417
2006-11-03 19:13:59 +00:00
9456dd8b81
Fix comments.
...
llvm-svn: 31414
2006-11-03 07:31:32 +00:00
1dfd26a151
Rename
...
llvm-svn: 31413
2006-11-03 07:21:16 +00:00
52f958741a
Remove dead variable. Fix 80 column violations.
...
llvm-svn: 31412
2006-11-03 03:30:34 +00:00
357017f4a9
Added DAG combiner transformation to generate pre-indexed loads.
...
llvm-svn: 31410
2006-11-03 03:06:21 +00:00
c176f038b9
Added isPredecessor.
...
llvm-svn: 31409
2006-11-03 03:05:24 +00:00
299022d514
Proper check for two-addressness.
...
llvm-svn: 31408
2006-11-03 03:04:46 +00:00
cd7b92251d
silence warning
...
llvm-svn: 31397
2006-11-03 01:28:29 +00:00
cb67d99001
Make CodeGen libs -pedantic clean.
...
llvm-svn: 31387
2006-11-02 23:56:21 +00:00
15d166ba8f
1. Hash not quite right for DIEValues.
...
2. Not going to use Usage (no significant benefit.)
llvm-svn: 31384
2006-11-02 21:48:18 +00:00
9ec8a7555b
Remove unused variable.
...
llvm-svn: 31382
2006-11-02 20:55:40 +00:00
de46e48420
For PR786:
...
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.
llvm-svn: 31380
2006-11-02 20:25:50 +00:00
936d546eca
General clean up of teh dwarf writer.
...
1. Most significant is the folding of debug information entries. This
reduced self hosted -g SelectionDAGISel.s from 120M to 13M and pretty
close to matching .o file sizes with gcc.
2. Debug information entry printing for debugging the dwarf code.
3. Bring all the code closer to llvm standards.
4. Misc. fixes and doc clean ups.
llvm-svn: 31379
2006-11-02 20:12:39 +00:00
7eb55b395f
For PR950:
...
Replace the REM instruction with UREM, SREM and FREM.
llvm-svn: 31369
2006-11-02 01:53:59 +00:00
55402d4403
Allow the getRegForInlineAsmConstraint method to return a register class with
...
no fixes physreg. Treat this as permission to use any register in the register
class. When this happens and it is safe, allow the llvm register allcoator to
allocate the register instead of doing it at isel time. This eliminates a ton
of copies around common inline asms. For example:
int test2(int Y, int X) {
asm("foo %0, %1" : "=r"(X): "r"(X));
return X;
}
now compiles to:
_test2:
foo r3, r4
blr
instead of:
_test2:
mr r2, r4
foo r2, r2
mr r3, r2
blr
GCC produces:
_test2:
foo r4, r4
mr r3,r4
blr
llvm-svn: 31366
2006-11-02 01:41:49 +00:00
93cdd149f7
Rename
...
llvm-svn: 31364
2006-11-01 23:18:32 +00:00
d8697deca3
Two-address instructions no longer have to be A := A op C. Now any pair of dest / src operands can be tied together.
...
llvm-svn: 31363
2006-11-01 23:06:55 +00:00
1359196c4e
Clean up.
...
llvm-svn: 31359
2006-11-01 22:39:30 +00:00
47218fab42
CopyFromReg starts a live range so its use should not be considered a floater.
...
llvm-svn: 31356
2006-11-01 22:17:06 +00:00
7cee6ddcd8
give branch folding a simple heuristic to decide which block to split so that
...
it inserts an uncond branch where it is less likely to cause a problem. This
fixes some perf issues on ppc.
llvm-svn: 31354
2006-11-01 19:36:29 +00:00
91f120f4fa
Add a printSetLabel that takes two id's.
...
llvm-svn: 31347
2006-11-01 09:23:08 +00:00
415f365e5c
Print jumptable index.
...
llvm-svn: 31340
2006-11-01 04:48:30 +00:00
f505a5a063
make tail merging more aggressive. If two blocks share a common tail, but the
...
tail is not an entire block for either of them, pick one, split it, then
merge the common part.
llvm-svn: 31336
2006-11-01 01:16:12 +00:00
3ac71b31f0
enable branch folding with an option
...
llvm-svn: 31335
2006-11-01 00:38:31 +00:00
fe43befeda
Compile CodeGen/PowerPC/fp-branch.ll to:
...
_intcoord_cond_next55:
LBB1_3: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
blt cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
li r3, 1
blr
LBB1_2: ;cond_next62.exitStub
li r3, 0
blr
instead of:
_intcoord_cond_next55:
LBB1_3: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
bge cr0, LBB1_1 ;bb72.exitStub
LBB1_4: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
bnu cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
li r3, 1
blr
LBB1_2: ;cond_next62.exitStub
li r3, 0
blr
llvm-svn: 31330
2006-10-31 23:06:00 +00:00
427301fdae
look through isunordered to inline it into branch blocks.
...
llvm-svn: 31328
2006-10-31 22:37:42 +00:00
1fd360e13a
handle global address constant sdnodes
...
llvm-svn: 31323
2006-10-31 20:01:56 +00:00
6f043b90ea
TargetLowering::isOperandValidForConstraint
...
llvm-svn: 31319
2006-10-31 19:41:18 +00:00
8c6949e5b2
Change the prototype for TargetLowering::isOperandValidForConstraint
...
llvm-svn: 31318
2006-10-31 19:40:43 +00:00
aa4c0f9374
1. Clean up code due to changes in SwitchTo*Section(2)
...
2. Added partial debug support for mingw\cygwin targets (the same as
Linux\ELF). Please note, that currently mingw\cygwin uses 'stabs' format
for storing debug info by default, thus many (runtime) libraries has
this information included. These formats shouldn't be mixed in one binary
('stabs' & 'DWARF'), otherwise binutils tools will be confused.
llvm-svn: 31311
2006-10-31 08:31:24 +00:00
968f803928
Turn an assert into an error message. This is commonly triggered when
...
we don't support a specific constraint yet. When this happens, print the
unsupported constraint.
llvm-svn: 31310
2006-10-31 07:33:13 +00:00
e6d584765f
Fix a typo which can break jumptables.
...
llvm-svn: 31305
2006-10-31 02:31:00 +00:00
7eda51d4cf
Fix a problem introduced by a last-minute change (logic negation).
...
llvm-svn: 31302
2006-10-30 23:34:32 +00:00
b51b5c0b1f
Add debug support for X86/ELF targets (Linux). This allows llvm-gcc4
...
generated object modules to be debugged with gdb. Hopefully this helps
pre-release debugging.
llvm-svn: 31299
2006-10-30 22:32:30 +00:00
ad2f5b7d18
Switch abbreviations to use the folding set.a.
...
llvm-svn: 31296
2006-10-30 15:59:54 +00:00
43c19124bb
Simplify DwarfWriter header.
...
llvm-svn: 31295
2006-10-30 13:35:07 +00:00
84a28d4e76
Lower jumptable to BR_JT. The legalizer can lower it to a BRIND or let the target custom lower it.
...
llvm-svn: 31293
2006-10-30 08:00:44 +00:00
c3e695137d
Added a new SDNode type: BR_JT for jumptable branch.
...
llvm-svn: 31292
2006-10-30 07:59:36 +00:00
504eeda365
Make CanFallThrough more intelligent (so it can handle blocks with (e.g.) no
...
successors), and make island block movement more general.
This compiles CodeGen/X86/2006-04-27-ISelFoldingBug.ll to:
_loadAndRLEsource_no_exit_2E_1_label_2E_0:
subl $8, %esp
movl %esi, 4(%esp)
movl %ebx, (%esp)
movl 16(%esp), %eax
movl 12(%esp), %ecx
LBB1_3: #label.0
movl _last, %edx
movl %edx, %esi
incl %esi
movl %esi, _last
movl %ecx, %ebx
# TRUNCATE movb %bl, %bl
movl _block, %esi
movb %bl, 1(%esi,%edx)
cmpl %eax, _last
jge LBB1_2 #codeRepl5.exitStub
LBB1_4: #label.0
cmpl $257, %ecx
je LBB1_2 #codeRepl5.exitStub
LBB1_1: #label.0.no_exit.1_crit_edge.exitStub
movl $1, %eax
movl (%esp), %ebx
movl 4(%esp), %esi
addl $8, %esp
ret
LBB1_2: #codeRepl5.exitStub
xorl %eax, %eax
movl (%esp), %ebx
movl 4(%esp), %esi
addl $8, %esp
ret
instead of:
_loadAndRLEsource_no_exit_2E_1_label_2E_0:
subl $8, %esp
movl %esi, 4(%esp)
movl %ebx, (%esp)
movl 16(%esp), %eax
movl 12(%esp), %ecx
jmp LBB1_3 #label.0
LBB1_1: #label.0.no_exit.1_crit_edge.exitStub
movl $1, %eax
movl (%esp), %ebx
movl 4(%esp), %esi
addl $8, %esp
ret
LBB1_2: #codeRepl5.exitStub
xorl %eax, %eax
movl (%esp), %ebx
movl 4(%esp), %esi
addl $8, %esp
ret
LBB1_3: #label.0
movl _last, %edx
movl %edx, %esi
incl %esi
movl %esi, _last
movl %ecx, %ebx
# TRUNCATE movb %bl, %bl
movl _block, %esi
movb %bl, 1(%esi,%edx)
cmpl %eax, _last
jge LBB1_2 #codeRepl5.exitStub
LBB1_4: #label.0
cmpl $257, %ecx
jne LBB1_1 #label.0.no_exit.1_crit_edge.exitStub
jmp LBB1_2 #codeRepl5.exitStub
... which is much better layout :)
llvm-svn: 31282
2006-10-29 21:05:41 +00:00
e60ae823e8
fix Generic/2006-10-29-Crash.ll
...
llvm-svn: 31281
2006-10-29 21:01:20 +00:00
f31b9ef458
Fix a load folding issue that Evan noticed: there is no need to export values
...
used by comparisons in the main block.
llvm-svn: 31279
2006-10-29 18:23:37 +00:00
7ab6123c42
VLOAD is not the LoadSDNode opcode.
...
llvm-svn: 31276
2006-10-29 06:14:47 +00:00
dc146a9fb9
Remove spurious case. EXTLOAD is not one of the node opcodes.
...
llvm-svn: 31275
2006-10-29 02:26:30 +00:00
bba52191fa
split critical edges more carefully and intelligently. In particular, critical
...
edges whose destinations are not phi nodes don't bother us. Also, share
split edges, since the split edge can't have a phi. This significantly
reduces the complexity of generated code in some cases.
llvm-svn: 31274
2006-10-28 19:22:10 +00:00
c07657f59b
Teach branch folding to fold identical jump tables together and to delete
...
jump tables that are dead.
llvm-svn: 31273
2006-10-28 18:34:47 +00:00
cde339cf1e
const'ify jump table stuff
...
llvm-svn: 31269
2006-10-28 18:17:09 +00:00
28328f9a0a
add an assert
...
llvm-svn: 31267
2006-10-28 18:11:20 +00:00
28bfe389d1
don't print dead jump tables
...
llvm-svn: 31266
2006-10-28 18:10:06 +00:00
af8383806b
improve deletion of blocks that just contain branches by knowing that
...
the pred block doesn't fall through into them if it's a jumptable.
llvm-svn: 31263
2006-10-28 17:32:47 +00:00
eef273a16f
Load and stores have not been uniqued properly.
...
llvm-svn: 31261
2006-10-28 17:25:28 +00:00
3e6b1c6157
Split *all* critical edges before isel. This resolves issues with spill code
...
being inserted on unsplit critical edges, which introduces (sometimes large
amounts of) partially dead spill code.
This also fixes PR925 + CodeGen/Generic/switch-crit-edge-constant.ll
llvm-svn: 31260
2006-10-28 17:04:37 +00:00
b78eb6c8d1
Fix a serious bug that caused any x86 vector stuff to infinite loop
...
llvm-svn: 31254
2006-10-28 06:15:26 +00:00
bd0f088743
Clean up.
...
llvm-svn: 31243
2006-10-27 23:52:51 +00:00
84a035056e
Fix a bug in merged condition handling (CodeGen/Generic/2006-10-27-CondFolding.ll).
...
Add many fewer CFG edges and PHI node entries. If there is a switch which has
the same block as multiple destinations, only add that block once as a successor/phi
node (in the jumptable case)
llvm-svn: 31242
2006-10-27 23:50:33 +00:00
f576b42bb2
Switch over from SelectionNodeCSEMap to FoldingSet.
...
llvm-svn: 31240
2006-10-27 23:46:08 +00:00
b9392fb635
remove debug code
...
llvm-svn: 31233
2006-10-27 21:58:03 +00:00
f1b54fd7a5
Codegen cond&cond with two branches. This compiles (f.e.) PowerPC/and-branch.ll to:
...
cmpwi cr0, r4, 4
bgt cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_3: ;entry
cmplwi cr0, r3, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r3, r4, r3
rlwinm r2, r2, 30, 31, 31
or r2, r2, r3
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_1: ;cond_true
llvm-svn: 31232
2006-10-27 21:54:23 +00:00
ed0110b949
Turn conditions like x<Y|z==q into multiple blocks.
...
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-27 21:36:01 +00:00
96d6bf50ae
getPreIndexedLoad -> getIndexedLoad.
...
llvm-svn: 31209
2006-10-26 21:53:40 +00:00
7e80b0b31e
For PR950:
...
Make necessary changes to support DIV -> [SUF]Div. This changes llvm to
have three division instructions: signed, unsigned, floating point. The
bytecode and assembler are bacwards compatible, however.
llvm-svn: 31195
2006-10-26 06:15:43 +00:00
0d4479b77d
simplify code
...
llvm-svn: 31188
2006-10-25 22:21:37 +00:00
9feb308d51
turn off tail merging for now
...
llvm-svn: 31180
2006-10-25 18:08:50 +00:00
7a7835deb4
be more aggressive about matching identical instructions.
...
llvm-svn: 31179
2006-10-25 18:08:14 +00:00
71b99297aa
Move getPreferredAlignmentLog from AsmPrinter to TargetData
...
llvm-svn: 31171
2006-10-24 20:32:14 +00:00
61bcf9154d
visitSwitchCase knows how to insert conditional branches well. Change
...
visitBr to just call visitSwitchCase, eliminating duplicate logic.
llvm-svn: 31167
2006-10-24 18:07:37 +00:00
963ddad31a
Generalize CaseBlock a bit more:
...
Rename LHSBB/RHSBB to TrueBB/FalseBB. Allow the RHS value to be null,
in which case the LHS is treated as a bool.
llvm-svn: 31166
2006-10-24 17:57:59 +00:00
3f179d24c6
generalize 'CaseBlock'. It really allows any comparison to be inserted.
...
llvm-svn: 31161
2006-10-24 17:03:35 +00:00
1941bfa361
Don't do dead block elimination in fast mode.
...
llvm-svn: 31155
2006-10-24 16:11:49 +00:00
a916192267
LinearScanner hotspot.
...
llvm-svn: 31153
2006-10-24 14:35:25 +00:00
516cd40b5c
Tighter data structure for deleted debug labels.
...
llvm-svn: 31152
2006-10-24 11:50:43 +00:00
ceb51d8427
move single basic blocks that are neither fallen into nor fall out of into
...
a place more useful. In particular, if we can put them in a place where code
will be able to fall into it, do so. Otherwise, put it in a place it can fall
through into a successor. Otherwise, if preventing a fallthrough, move to the
end of the function, out of the way.
This deletes several hundred unconditional branches from spass.
llvm-svn: 31149
2006-10-24 01:12:32 +00:00
94866bef35
add moveBefore/moveAfter helper methods
...
llvm-svn: 31145
2006-10-24 00:02:26 +00:00
ebdb1d6724
Enable tail merging by default.
...
llvm-svn: 31140
2006-10-23 22:10:12 +00:00
4c931502cc
Minor tweak. Instead of generating:
...
movl 32(%esp), %eax
cmpl $1, %eax
je LBB1_1 #bb
LBB1_4: #entry
cmpl $2, %eax
je LBB1_2 #bb2
jmp LBB1_3 #UnifiedReturnBlock
LBB1_1: #bb
notice that we would miss the fall through and emit this instead:
movl 32(%esp), %eax
cmpl $2, %eax
je LBB1_2 #bb2
LBB1_4: #entry
cmpl $1, %eax
jne LBB1_3 #UnifiedReturnBlock
LBB1_1: #bb
llvm-svn: 31130
2006-10-23 18:38:22 +00:00
5e1a34032b
More complete solution to deleting blocks and debug info.
...
llvm-svn: 31129
2006-10-23 14:56:37 +00:00
76a7bc8c55
Fix phi node updating for switches lowered to linear sequences of branches.
...
llvm-svn: 31125
2006-10-22 23:00:53 +00:00
4c3ef4782d
disable this code for now, it's not yet safely updating phi nodes
...
llvm-svn: 31124
2006-10-22 22:47:10 +00:00
6d6fc26257
Implement PR964 and Regression/CodeGen/Generic/SwitchLowering.ll
...
llvm-svn: 31119
2006-10-22 21:36:53 +00:00
9f5a129543
don't break infinite loops
...
llvm-svn: 31102
2006-10-21 06:11:43 +00:00
28f17f45be
Use branch reversal to do stuff like this:
...
call L_strcmp$stub
testl %eax, %eax
- jne LBB26_208 #cond_true6020
- jmp LBB26_227 #bb7119
+ je LBB26_227 #bb7119
LBB26_208: #cond_true6020
movl $l31_str14, 4(%esp)
testl %eax, %eax
- jne LBB26_704 #cond_true13042
- jmp LBB26_713 #bb13151
+ je LBB26_713 #bb13151
LBB26_704: #cond_true13042
movl $_str52, 4(%esp)
cmpl 76(%ecx), %eax
- jge LBB26_1628 #cond_false63.i.i
- jmp LBB26_1769 #_Z8makeGridP13mrSurfaceListidiidd.exit.i
+ jl LBB26_1769 #_Z8makeGridP13mrSurfaceListidiidd.exit.i
LBB26_1628: #cond_false63.i.i
movl $0, 48964(%esp)
llvm-svn: 31100
2006-10-21 05:54:00 +00:00
3ca52185af
Transform code like:
...
jle FOO
jmp BAR
BAR:
into:
jle FOO
BAR:
... whoa!
llvm-svn: 31098
2006-10-21 05:43:30 +00:00
4fe01c42ca
Three changes:
...
1. Remove a bunch of ifdef'd code.
2. When a block just contains an uncond branch, change all blocks branching
to it to jump to the destination instead.
3. If branch analysis tells us some edges in the machinecfg are not actually
possible, remove them.
#2 triggers a suprisingly large number of times.
llvm-svn: 31094
2006-10-21 05:08:28 +00:00
60c9d4dc76
Add an experimental cross-jumping implementation.
...
This is currently disabled by default and limited in several ways, but does
have a positive effect.
llvm-svn: 31090
2006-10-21 00:47:49 +00:00
33f5af09e4
implement MachineOperand::isIdenticalTo
...
llvm-svn: 31088
2006-10-20 22:39:59 +00:00
c5ab6ce613
Make flag and chain edges visually distinguishable from value edges in DOT
...
output.
llvm-svn: 31067
2006-10-20 18:06:09 +00:00
e0fc4dfc22
For PR950:
...
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.
llvm-svn: 31063
2006-10-20 07:07:24 +00:00
be96e1cd09
Partially in response to PR926: insert the newly created machine basic
...
blocks into the basic block list when lowering the switch inst. into a
binary tree of if-then statements. This allows the "visitSwitchCase" func
to allow for fall-through behavior.
llvm-svn: 31057
2006-10-19 21:46:38 +00:00
55e4dcad36
Add option for controlling inclusion of global AA.
...
llvm-svn: 31040
2006-10-18 19:08:31 +00:00
a15b0ebb5e
Use global info for alias analysis.
...
llvm-svn: 31035
2006-10-18 12:29:57 +00:00
73da320e50
Teach the branch folder to update debug info if it removes blocks with line
...
# notes in it.
llvm-svn: 31026
2006-10-17 23:17:27 +00:00
34136d0cc1
add a method to remove a line # record.
...
llvm-svn: 31025
2006-10-17 23:16:42 +00:00
145f6b3ec8
Do not leak all of the SourceLineInfo objects. Do not bother mallocing each
...
one separately.
llvm-svn: 31022
2006-10-17 22:06:46 +00:00
78fd0f83ff
Trivial patch to speed up legalizing common i64 constants.
...
llvm-svn: 31020
2006-10-17 21:47:13 +00:00
327b88b102
Fix CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll
...
llvm-svn: 31019
2006-10-17 21:24:15 +00:00
2f4ddce75c
Fix printer for StoreSDNode.
...
llvm-svn: 31017
2006-10-17 21:18:26 +00:00
1839d76f69
Reflect MemOpAddrMode change; added a helper to create pre-indexed load.
...
llvm-svn: 31016
2006-10-17 21:14:32 +00:00
e7d2c24a7d
Make it simplier to dump DAGs while in DAGCombiner. Remove a nasty optimization.
...
llvm-svn: 31009
2006-10-17 19:33:52 +00:00
bca3e297fe
Enable deleting branches to successor blocks. With the previous patches,
...
branch folding can now compile stuff like this:
void foo(int W, int X, int Y, int Z) {
if (W & 1) {
for (; X;--X) bar();
} else if (W & 2) {
for (; Y;--Y) bar();
} else if (W & 4) {
for (; Z;--Z) bar();
} else if (W & 8) {
for (; W;--W) bar();
}
if (W) {
bar();
}
}
contrived testcase where loops exits all end up merging together. To have
the loop merges be:
...
cmplw cr0, r30, r27
bne cr0, LBB1_14 ;bb38
LBB1_16: ;cond_next48.loopexit
mr r27, r29
LBB1_20: ;cond_next48
cmplwi cr0, r27, 0
beq cr0, LBB1_22 ;UnifiedReturnBlock
...
instead of:
...
cmplw cr0, r30, r27
bne cr0, LBB1_14 ;bb38
LBB1_16: ;cond_next48.loopexit
mr r27, r29
b LBB1_20 ;cond_next48
LBB1_17: ;cond_next48.loopexit1
b LBB1_20 ;cond_next48
LBB1_18: ;cond_next48.loopexit2
b LBB1_20 ;cond_next48
LBB1_19: ;cond_next48.loopexit3
LBB1_20: ;cond_next48
cmplwi cr0, r27, 0
beq cr0, LBB1_22 ;UnifiedReturnBlock
...
This is CodeGen/PowerPC/branch-opt.ll
llvm-svn: 31006
2006-10-17 18:16:40 +00:00
d24b913a61
Clean up interface to getGlobalLinkName.
...
llvm-svn: 31001
2006-10-17 17:17:24 +00:00
56c9d2597e
Reenable this pass, fixing the bugs in it.
...
It now correctly deletes unreachable blocks and blocks that are empty.
llvm-svn: 31000
2006-10-17 17:13:52 +00:00
1e3a39cd08
Make sure operand does have size and element type operands.
...
llvm-svn: 30999
2006-10-17 17:06:35 +00:00
7126254a0e
Basic support for getGlobalLinkName.
...
llvm-svn: 30997
2006-10-17 13:41:07 +00:00
f3ae00a64a
Be careful when looking through a vbit_convert. Optimizing this:
...
(vector_shuffle
(vbitconvert (vbuildvector (copyfromreg v4f32), 1, v4f32), 4, f32),
(undef, undef, undef, undef), (0, 0, 0, 0), 4, f32)
to the
vbitconvert
is a very bad idea.
llvm-svn: 30989
2006-10-16 22:49:37 +00:00
dcb2b83886
Pass AliasAnalysis thru to DAGCombiner.
...
llvm-svn: 30984
2006-10-16 20:52:31 +00:00
9db3a08864
Global name regression.
...
llvm-svn: 30982
2006-10-16 19:38:41 +00:00
3bf4f3bd60
Tidy up after truncstore changes.
...
llvm-svn: 30961
2006-10-14 12:14:27 +00:00
47fbeda5ce
Debug tweak.
...
llvm-svn: 30959
2006-10-14 08:34:06 +00:00
6a1b2de8c4
Make sure that the node returned by SimplifySetCC is added to the worklist
...
so that it can be deleted if unused.
llvm-svn: 30955
2006-10-14 03:52:46 +00:00
0626bd2fbc
fold setcc of a setcc.
...
llvm-svn: 30953
2006-10-14 01:02:29 +00:00
bd9acad805
When SimplifySetCC was moved to the DAGCombiner, it was never removed from
...
SelectionDAG and it has since bitrotted. Remove the copy from SelectionDAG.
Next, remove the constant folding piece of DAGCombiner::SimplifySetCC into
a new FoldSetCC method which can be used by getNode() and SimplifySetCC.
This fixes obscure bugs.
llvm-svn: 30952
2006-10-14 00:41:01 +00:00
47db29a405
disable this pass for now, it's causing issues
...
llvm-svn: 30951
2006-10-14 00:30:06 +00:00
3218e0eed5
falling off the end of a function is ok with an unreachable instruction.
...
llvm-svn: 30950
2006-10-14 00:21:48 +00:00
dcf983ce41
Reduce the workload by not adding chain users to work list.
...
llvm-svn: 30948
2006-10-13 23:32:28 +00:00
45ffb1eb70
Fix a bug where we incorrectly turned '(X & 0) == 0' into '(X & 0) >> -1',
...
which is undefined. "0" isn't a power of 2.
llvm-svn: 30947
2006-10-13 22:46:18 +00:00
ab51cf2e78
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
...
llvm-svn: 30945
2006-10-13 21:14:26 +00:00
55ad08a59b
add the branch folding pass as a late cleanup pass for all targets. For now
...
it just deletes empty MBB's. Soon it will do more :)
llvm-svn: 30941
2006-10-13 20:45:56 +00:00
3e8e57c771
disable some objectionable code, maybe we can bring this pass to life
...
llvm-svn: 30939
2006-10-13 20:43:10 +00:00
ccee9baebe
Workaround for templates
...
llvm-svn: 30927
2006-10-13 13:02:19 +00:00
13d3373e72
Clean up dump.
...
llvm-svn: 30926
2006-10-13 13:01:34 +00:00
d0620d2773
Lower X%C into X/C+stuff. This allows the 'division by a constant' logic to
...
apply to rems as well as divs. This fixes PR945 and speeds up ReedSolomon
from 14.57s to 10.90s (which is now faster than gcc).
It compiles CodeGen/X86/rem.ll into:
_test1:
subl $4, %esp
movl %esi, (%esp)
movl $2155905153, %ecx
movl 8(%esp), %esi
movl %esi, %eax
imull %ecx
addl %esi, %edx
movl %edx, %eax
shrl $31, %eax
sarl $7, %edx
addl %eax, %edx
imull $255, %edx, %eax
subl %eax, %esi
movl %esi, %eax
movl (%esp), %esi
addl $4, %esp
ret
_test2:
movl 4(%esp), %eax
movl %eax, %ecx
sarl $31, %ecx
shrl $24, %ecx
addl %eax, %ecx
andl $4294967040, %ecx
subl %ecx, %eax
ret
_test3:
subl $4, %esp
movl %esi, (%esp)
movl $2155905153, %ecx
movl 8(%esp), %esi
movl %esi, %eax
mull %ecx
shrl $7, %edx
imull $255, %edx, %eax
subl %eax, %esi
movl %esi, %eax
movl (%esp), %esi
addl $4, %esp
ret
instead of div/idiv instructions.
llvm-svn: 30920
2006-10-12 20:58:32 +00:00
a731cb674a
Add RemoveDeadNode to remove a dead node and its (potentially) dead operands.
...
llvm-svn: 30916
2006-10-12 20:34:05 +00:00
2e33fb453b
add a minor dag combine noticed when looking at PR945
...
llvm-svn: 30915
2006-10-12 20:23:19 +00:00
c040e53372
restore my previous patch, now that the X86 backend bug has been fixed:
...
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20061009/038518.html
llvm-svn: 30906
2006-10-12 17:45:38 +00:00
df2ccc395e
D'oh - need to use the rigth kind of store.
...
llvm-svn: 30903
2006-10-12 15:22:24 +00:00
c935741b1d
Backing out Chris' last commit. It's breaking llvm-gcc bootstrapping.
...
It's turning:
movl -24(%ebp), %esp
subl $16, %esp
movl -24(%ebp), %ecx
into
movl -24(%ebp), %esp
subl $16, %esp
movl %esp, (%esp)
llvm-svn: 30902
2006-10-12 08:00:47 +00:00
86a012ab61
If we see a load from a stack slot into a physreg, consider it as providing
...
the stack slot. This fixes PR943.
llvm-svn: 30898
2006-10-12 02:34:07 +00:00
a13b9c7aa4
Alias analysis of TRUNCSTORE.
...
llvm-svn: 30889
2006-10-11 18:55:16 +00:00
6a4c6d3a7a
Typo
...
llvm-svn: 30884
2006-10-11 17:52:19 +00:00
0f7c328ae7
Handle aliasing of loadext.
...
llvm-svn: 30883
2006-10-11 17:47:52 +00:00
08edf332ed
Fix regression in combiner alias analysis.
...
llvm-svn: 30880
2006-10-11 13:47:09 +00:00
d35734bd1f
Naming consistency.
...
llvm-svn: 30878
2006-10-11 07:10:22 +00:00
a6bbf33cbf
Jimptables working again on alpha.
...
As a bonus, use the GOT node instead of the AlphaISD::GOT for internal stuff.
llvm-svn: 30873
2006-10-11 04:29:42 +00:00
6df349676e
add two helper methods.
...
llvm-svn: 30869
2006-10-11 03:58:02 +00:00
2da4671e05
FindModifiedNodeSlot needs to add LoadSDNode ivars to create proper SelectionDAGCSEMap ID.
...
llvm-svn: 30866
2006-10-11 01:47:58 +00:00
7994aec7b5
Also update getNodeLabel for LoadSDNode.
...
llvm-svn: 30861
2006-10-10 20:11:26 +00:00
fe858538c0
SDNode::dump should also print out extension type and VT.
...
llvm-svn: 30860
2006-10-10 20:05:10 +00:00
8438429c96
Fix another bug in extload promotion.
...
llvm-svn: 30857
2006-10-10 18:54:19 +00:00
dc6a3aab71
Fix a bug introduced by my LOAD/LOADX changes.
...
llvm-svn: 30853
2006-10-10 07:51:21 +00:00
e71fe34d75
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
...
llvm-svn: 30844
2006-10-09 20:57:25 +00:00
5ab6d8b3fc
Eliminate more token factors by taking advantage of transitivity:
...
if TF depends on A and B, and A depends on B, TF just needs to depend on
A. With Jim's alias-analysis stuff enabled, this compiles the testcase in
PR892 into:
__Z4test3Val:
subl $44, %esp
call L__Z3foov$stub
movl %edx, 28(%esp)
movl %eax, 32(%esp)
movl %eax, 24(%esp)
movl %edx, 36(%esp)
movl 52(%esp), %ecx
movl %ecx, 4(%esp)
movl %eax, 8(%esp)
movl %edx, 12(%esp)
movl 48(%esp), %eax
movl %eax, (%esp)
call L__Z3bar3ValS_$stub
addl $44, %esp
ret
instead of:
__Z4test3Val:
subl $44, %esp
call L__Z3foov$stub
movl %eax, 24(%esp)
movl %edx, 28(%esp)
movl 24(%esp), %eax
movl %eax, 32(%esp)
movl 28(%esp), %eax
movl %eax, 36(%esp)
movl 32(%esp), %eax
movl 36(%esp), %ecx
movl 52(%esp), %edx
movl %edx, 4(%esp)
movl %eax, 8(%esp)
movl %ecx, 12(%esp)
movl 48(%esp), %eax
movl %eax, (%esp)
call L__Z3bar3ValS_$stub
addl $44, %esp
ret
llvm-svn: 30821
2006-10-08 22:57:01 +00:00
0463e08005
Combiner alias analysis passes Multisource (release-asserts.)
...
llvm-svn: 30818
2006-10-07 23:37:56 +00:00
f9f90bc239
Fix a bug legalizing zero-extending i64 loads into 32-bit loads. The bottom
...
part was always forced to be sextload, even when we needed an zextload.
llvm-svn: 30782
2006-10-07 00:58:36 +00:00
a389a612bb
initialize ivar
...
llvm-svn: 30780
2006-10-06 22:52:08 +00:00
9043823cf4
If a target uses a GOT, put it in the jt data section, not the text
...
section. This will fix alpha when Andrew implements
AlphaTargetMachine::getTargetLowering().
llvm-svn: 30779
2006-10-06 22:50:56 +00:00
9d75324ddf
jump tables handle pic
...
llvm-svn: 30776
2006-10-06 22:32:29 +00:00
4e107aa0b6
print labels even if a MBB doesn't have a corresponding LLVM BB, just don't
...
print the LLVM BB label.
llvm-svn: 30775
2006-10-06 21:28:17 +00:00
f5839a0816
Fix a miscompilation of:
...
long long foo(long long X) {
return (long long)(signed char)(int)X;
}
Instead of:
_foo:
extsb r2, r4
srawi r3, r4, 31
mr r4, r2
blr
we now produce:
_foo:
extsb r4, r4
srawi r3, r4, 31
blr
This fixes a miscompilation in ConstantFolding.cpp.
llvm-svn: 30768
2006-10-06 17:34:12 +00:00
16ae43e901
MachineBasicBlock::splice was incorrectly updating parent pointers on
...
instructions.
llvm-svn: 30760
2006-10-06 01:12:44 +00:00
df9ac47e5e
Make use of getStore().
...
llvm-svn: 30759
2006-10-05 23:01:46 +00:00
af309d29b1
Add getStore() helper function to create ISD::STORE nodes.
...
llvm-svn: 30758
2006-10-05 22:57:11 +00:00
8b1a59a272
Don't crash if an MBB doesn't have an LLVM BB
...
llvm-svn: 30757
2006-10-05 21:40:14 +00:00
6549d22ef9
Alias analysis code clean ups.
...
llvm-svn: 30753
2006-10-05 15:07:25 +00:00
66c1625a37
Emit pic jumptables to the same section that the function is emitted to,
...
allowing label differences to work. This fixes CodeGen/X86/pic_jumptable.ll
llvm-svn: 30744
2006-10-05 03:13:28 +00:00
a6a570e02f
Pass the MachineFunction into EmitJumpTableInfo.
...
llvm-svn: 30742
2006-10-05 03:01:21 +00:00
dc82241182
move getSectionForFunction to AsmPrinter
...
llvm-svn: 30736
2006-10-05 02:42:47 +00:00
f80dfa83a0
Fix some typos that can cause a flag value to have more than one use.
...
llvm-svn: 30727
2006-10-04 22:23:53 +00:00
708d0db2d8
More extensive alias analysis.
...
llvm-svn: 30721
2006-10-04 16:53:27 +00:00
0d5a0eae57
More long term solution
...
llvm-svn: 30720
2006-10-04 10:40:15 +00:00
66b0b55816
Work around for some problems with templates.
...
llvm-svn: 30715
2006-10-04 01:43:13 +00:00
5d9fd977d3
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
...
extra operand to LOADX to specify the exact value extension type.
llvm-svn: 30714
2006-10-04 00:56:09 +00:00
fc416faaa0
Use $( $| $) to represent alternatives in asm blocks instead of {|}. This
...
is needed to support targets where {|} aren't special symbols.
llvm-svn: 30712
2006-10-03 23:27:09 +00:00
91d76cb27f
Fix an obvious typo.
...
llvm-svn: 30711
2006-10-03 23:08:27 +00:00
bd7286e606
Bugfixes
...
llvm-svn: 30709
2006-10-03 20:19:23 +00:00
de154b1737
Print the MBB ID # along with the bb tag in the -print-machine-instrs output.
...
llvm-svn: 30708
2006-10-03 20:17:24 +00:00
64fd9487bd
Provide a function that ensures MBB numbering is dense and inorder. This
...
can be used by MachineFunctionPasses who need this property.
llvm-svn: 30706
2006-10-03 19:18:57 +00:00
984f0ce06b
Fix for PR929. The PHI nodes were being gone through for each instruction
...
in a successor block for every block...resulting in some O(N^k) algorithm
which wasn't very good for performance. Calculating this information up
front and keeping it in a map made it much faster.
llvm-svn: 30697
2006-10-03 07:20:20 +00:00
e73a22514d
Debugging kruft
...
llvm-svn: 30688
2006-10-02 13:01:17 +00:00
1368c265da
Add ability to annotate (color) nodes in a viewGraph.
...
llvm-svn: 30686
2006-10-02 12:26:53 +00:00
eea983eb5d
simplify code
...
llvm-svn: 30659
2006-09-28 23:17:41 +00:00
bcf1b4120f
TargetRegisterClass specifies the desired spill alignment. However, it cannot be honored if stack alignment is smaller.
...
llvm-svn: 30648
2006-09-28 18:52:32 +00:00
5d409822d6
"Once more into the breach, dear friends, once more, or fill the wall up
...
with our English dead."
No! Really! Serious this time...It was how the vreg uses were being
adjusted that was causing hte Olden tests to fail. I corrected this and
the Olden and Regression tests all passed.
llvm-svn: 30644
2006-09-28 07:10:24 +00:00
a9caf95591
refactor critical edge breaking out into the SplitCritEdgesForPHIConstants method.
...
This is a baby step towards fixing PR925.
llvm-svn: 30643
2006-09-28 06:17:10 +00:00
764caf6129
re-re-revert this, back to the right revision. It currently breaks bisort/mst
...
in olden among others.
llvm-svn: 30637
2006-09-28 00:11:54 +00:00
d31f55c236
PEI now place callee save spills closest to the address pointed to by the
...
incoming stack. This allows X86 backend to use push / pop in epilogue /
prologue.
llvm-svn: 30636
2006-09-28 00:10:27 +00:00
9f7d0d1dc5
re-revert this patch, bisort and mst are still broken in Olden.
...
llvm-svn: 30634
2006-09-28 00:04:21 +00:00
1f29e6c5c5
Reapplying this patch. With the newest commits, the error in Olden/bisort
...
has disappeared.
llvm-svn: 30633
2006-09-27 22:37:35 +00:00
5f6c93701b
Temporarily revert this. This breaks Olden/bisort on PPC
...
llvm-svn: 30628
2006-09-27 16:59:16 +00:00
0a7f617a6c
PR878: Instead of calculating the vreg to PHI use count everytime we get
...
a function, do it up front in linear time (going through all of the
instructions once). We create a map out of them. Then it's no problem to
use the information in it during elimination...
llvm-svn: 30624
2006-09-27 09:04:15 +00:00
30b4708df2
Add support for ${:private} which prints "L" on darwin.
...
llvm-svn: 30620
2006-09-27 00:06:07 +00:00
a32814b033
Add support for ${:comment}, which expands to the current target's comment
...
character, and ${:uid} which expands to a unique ID for the MachineInstr.
More can be added if/when they are needed.
llvm-svn: 30619
2006-09-26 23:59:50 +00:00
5405c06737
Rename function. It's determining which callee-save registers to save.
...
llvm-svn: 30616
2006-09-26 22:29:31 +00:00
c19ef92403
Comments on JumpTableness
...
llvm-svn: 30615
2006-09-26 20:02:30 +00:00
60832693a7
Load chain check is not needed
...
llvm-svn: 30613
2006-09-26 17:44:58 +00:00
dde51671e5
Chain can be any operand
...
llvm-svn: 30611
2006-09-26 09:32:41 +00:00
5f3e0af9d0
Wrong size for load
...
llvm-svn: 30610
2006-09-26 08:14:06 +00:00
b4a864d533
Can't move a load node if it's chain is not used.
...
llvm-svn: 30609
2006-09-26 07:37:42 +00:00
9a1e91b107
print the preds of each MBB
...
llvm-svn: 30606
2006-09-26 03:41:59 +00:00
66af390631
Add support for targets that want to do something with the llvm.used list,
...
because they have an aggressive linker that does dead code stripping.
llvm-svn: 30604
2006-09-26 03:38:18 +00:00
7aa0638aa9
Accidental enable of bad code
...
llvm-svn: 30601
2006-09-25 21:11:32 +00:00
b5534e5c28
Fix chain dropping in load and drop unused stores in ret blocks.
...
llvm-svn: 30600
2006-09-25 19:32:58 +00:00
d07be232ba
Core antialiasing for load and store.
...
llvm-svn: 30597
2006-09-25 16:29:54 +00:00
783a4a9d86
Add support for other relocation bases to jump tables, as well as custom asm directives
...
llvm-svn: 30593
2006-09-24 19:45:58 +00:00
77c0757f8b
PIC jump table entries are always 32-bit. This fixes PIC jump table support on X86-64.
...
llvm-svn: 30590
2006-09-24 05:22:38 +00:00
449a0c7e33
Make it work for DAG combine of multi-value nodes.
...
llvm-svn: 30573
2006-09-21 19:04:05 +00:00
35f7eebb49
core corrections
...
llvm-svn: 30570
2006-09-21 17:35:47 +00:00
5d19d59017
Basic "in frame" alias analysis.
...
llvm-svn: 30568
2006-09-21 16:28:59 +00:00
082db3f9aa
fold (aext (and (trunc x), cst)) -> (and x, cst).
...
llvm-svn: 30561
2006-09-21 06:40:43 +00:00
fa9f92cf65
Check the right value type. This fixes 186.crafty on x86
...
llvm-svn: 30560
2006-09-21 06:17:39 +00:00
8d8a3bf9c9
Compile:
...
int %test(ulong *%tmp) {
%tmp = load ulong* %tmp ; <ulong> [#uses=1]
%tmp.mask = shr ulong %tmp, ubyte 50 ; <ulong> [#uses=1]
%tmp.mask = cast ulong %tmp.mask to ubyte
%tmp2 = and ubyte %tmp.mask, 3 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp2 to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
movl 4(%esp), %eax
movl 4(%eax), %eax
shrl $18, %eax
andl $3, %eax
ret
instead of:
_test:
movl 4(%esp), %eax
movl 4(%eax), %eax
shrl $18, %eax
# TRUNCATE movb %al, %al
andb $3, %al
movzbl %al, %eax
ret
llvm-svn: 30558
2006-09-21 06:14:31 +00:00
a31f0a622b
Generalize (zext (truncate x)) and (sext (truncate x)) folding to work when
...
the src/dst are not the same size. This catches things like "truncate
32-bit X to 8 bits, then zext to 16", which happens a bit on X86.
llvm-svn: 30557
2006-09-21 06:00:20 +00:00
c8cd62d381
Compile:
...
int test3(int a, int b) { return (a < 0) ? a : 0; }
to:
_test3:
srawi r2, r3, 31
and r3, r2, r3
blr
instead of:
_test3:
cmpwi cr0, r3, 1
li r2, 0
blt cr0, LBB2_2 ;entry
LBB2_1: ;entry
mr r3, r2
LBB2_2: ;entry
blr
This implements: PowerPC/select_lt0.ll:seli32_a_a
llvm-svn: 30517
2006-09-20 06:41:35 +00:00
8746e2cd57
Fold the full generality of (any_extend (truncate x))
...
llvm-svn: 30514
2006-09-20 06:29:17 +00:00
8b68decb27
Two things:
...
1. teach SimplifySetCC that '(srl (ctlz x), 5) == 0' is really x != 0.
2. Teach visitSELECT_CC to use SimplifySetCC instead of calling it and
ignoring the result. This allows us to compile:
bool %test(ulong %x) {
%tmp = setlt ulong %x, 4294967296
ret bool %tmp
}
to:
_test:
cntlzw r2, r3
cmplwi cr0, r3, 1
srwi r2, r2, 5
li r3, 0
beq cr0, LBB1_2 ;
LBB1_1: ;
mr r3, r2
LBB1_2: ;
blr
instead of:
_test:
addi r2, r3, -1
cntlzw r2, r2
cntlzw r3, r3
srwi r2, r2, 5
cmplwi cr0, r2, 0
srwi r2, r3, 5
li r3, 0
bne cr0, LBB1_2 ;
LBB1_1: ;
mr r3, r2
LBB1_2: ;
blr
This isn't wonderful, but it's an improvement.
llvm-svn: 30513
2006-09-20 06:19:26 +00:00
875ea0cdbd
Expand 64-bit shifts more optimally if we know that the high bit of the
...
shift amount is one or zero. For example, for:
long long foo1(long long X, int C) {
return X << (C|32);
}
long long foo2(long long X, int C) {
return X << (C&~32);
}
we get:
_foo1:
movb $31, %cl
movl 4(%esp), %edx
andb 12(%esp), %cl
shll %cl, %edx
xorl %eax, %eax
ret
_foo2:
movb $223, %cl
movl 4(%esp), %eax
movl 8(%esp), %edx
andb 12(%esp), %cl
shldl %cl, %eax, %edx
shll %cl, %eax
ret
instead of:
_foo1:
subl $4, %esp
movl %ebx, (%esp)
movb $32, %bl
movl 8(%esp), %eax
movl 12(%esp), %edx
movb %bl, %cl
orb 16(%esp), %cl
shldl %cl, %eax, %edx
shll %cl, %eax
xorl %ecx, %ecx
testb %bl, %bl
cmovne %eax, %edx
cmovne %ecx, %eax
movl (%esp), %ebx
addl $4, %esp
ret
_foo2:
subl $4, %esp
movl %ebx, (%esp)
movb $223, %cl
movl 8(%esp), %eax
movl 12(%esp), %edx
andb 16(%esp), %cl
shldl %cl, %eax, %edx
shll %cl, %eax
xorl %ecx, %ecx
xorb %bl, %bl
testb %bl, %bl
cmovne %eax, %edx
cmovne %ecx, %eax
movl (%esp), %ebx
addl $4, %esp
ret
llvm-svn: 30506
2006-09-20 03:38:48 +00:00
698000b0da
Fix UnitTests/2005-05-12-Int64ToFP.c with llc-beta. In particular, do not
...
allow it to go into an infinite loop, filling up the disk!
llvm-svn: 30494
2006-09-19 18:02:01 +00:00
5a42ebcff3
Fold extract_element(cst) to cst
...
llvm-svn: 30478
2006-09-19 05:02:39 +00:00
4c059f4962
Minor speedup for legalize by avoiding some malloc traffic
...
llvm-svn: 30477
2006-09-19 04:51:23 +00:00
1fc7c363e6
Fix a typo.
...
llvm-svn: 30474
2006-09-18 23:28:33 +00:00
4bfaf0bd2c
Allow i32 UDIV, SDIV, UREM, SREM to be expanded into libcalls.
...
llvm-svn: 30470
2006-09-18 21:49:04 +00:00
51ad73c98c
oops
...
llvm-svn: 30462
2006-09-18 18:00:18 +00:00
c50458fb90
absolute addresses must match pointer size
...
llvm-svn: 30461
2006-09-18 17:59:35 +00:00
d30bba331f
Sort out mangled names for globals
...
llvm-svn: 30460
2006-09-18 14:47:26 +00:00
e50f5d1fb1
Oh yeah, this is needed too
...
llvm-svn: 30407
2006-09-16 05:08:34 +00:00
1b63391fdf
simplify control flow, no functionality change
...
llvm-svn: 30403
2006-09-16 00:21:44 +00:00
fbadbda6ba
Allow custom expand of mul
...
llvm-svn: 30402
2006-09-16 00:09:24 +00:00
8fb3d445f5
Keep track of the start of MBB's in a separate map from instructions. This
...
is faster and is needed for future improvements.
llvm-svn: 30383
2006-09-15 03:57:23 +00:00
46d710e6ea
Fold (X & C1) | (Y & C2) -> (X|Y) & C3 when possible.
...
This implements CodeGen/X86/and-or-fold.ll
llvm-svn: 30379
2006-09-14 21:11:37 +00:00
97614c86ce
Split rotate matching code out to its own function. Make it stronger, by
...
matching things like ((x >> c1) & c2) | ((x << c3) & c4) to (rot x, c5) & c6
llvm-svn: 30376
2006-09-14 20:50:57 +00:00
616aa548b2
Use getOffset() instead.
...
llvm-svn: 30327
2006-09-14 07:41:12 +00:00
2ad050fb3e
Use MachineConstantPoolEntry getOffset() and getType() accessors.
...
llvm-svn: 30326
2006-09-14 07:35:00 +00:00
4f9299552b
A MachineConstantPool may have mixed Constant* and MachineConstantPoolValue* values.
...
llvm-svn: 30316
2006-09-14 05:50:57 +00:00
84cc1f7cb8
If LSR went through a lot of trouble to put constants (e.g. the addr of a global
...
in a specific BB, don't undo this!). This allows us to compile
CodeGen/X86/loop-hoist.ll into:
_foo:
xorl %eax, %eax
*** movl L_Arr$non_lazy_ptr, %ecx
movl 4(%esp), %edx
LBB1_1: #cond_true
movl %eax, (%ecx,%eax,4)
incl %eax
cmpl %edx, %eax
jne LBB1_1 #cond_true
LBB1_2: #return
ret
instead of:
_foo:
xorl %eax, %eax
movl 4(%esp), %ecx
LBB1_1: #cond_true
*** movl L_Arr$non_lazy_ptr, %edx
movl %eax, (%edx,%eax,4)
incl %eax
cmpl %ecx, %eax
jne LBB1_1 #cond_true
LBB1_2: #return
ret
This was noticed in 464.h264ref. This doesn't usually affect PPC,
but strikes X86 all the time.
llvm-svn: 30290
2006-09-13 06:02:42 +00:00
72b503bcad
Compile X << 1 (where X is a long-long) to:
...
addl %ecx, %ecx
adcl %eax, %eax
instead of:
movl %ecx, %edx
addl %edx, %edx
shrl $31, %ecx
addl %eax, %eax
orl %ecx, %eax
and to:
addc r5, r5, r5
adde r4, r4, r4
instead of:
slwi r2,r9,1
srwi r0,r11,31
slwi r3,r11,1
or r2,r0,r2
on PPC.
llvm-svn: 30284
2006-09-13 03:50:39 +00:00
45fe3bc72c
Added support for machine specific constantpool values. These are useful for
...
representing expressions that can only be resolved at link time, etc.
llvm-svn: 30278
2006-09-12 21:00:35 +00:00
a0d95a8da9
Behold, more work on relocations. Things are looking pretty good now.
...
llvm-svn: 30240
2006-09-10 23:03:44 +00:00
2e0dfb0b16
This code was trying too hard. By eliminating redundant edges in the CFG
...
due to switch cases going to the same place, it make #pred != #phi entries,
breaking live interval analysis.
This fixes 458.sjeng on x86 with llc.
llvm-svn: 30236
2006-09-10 06:36:57 +00:00
Chris Lattner