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Author SHA1 Message Date
Sebastian Neubauer 833b3b0d3a [AMDGPU] Add v3f16/v3i16 support to SDag 
Fix lowering and instruction selection for v3x16 types
and enable InstCombine to emit them.

This patch only implements it for the selection dag.
GlobalISel tests in GlobalISel/llvm.amdgcn.image.load.1d.d16.ll and
GlobalISel/llvm.amdgcn.image.store.2d.d16.ll still don't work.

Differential Revision: https://reviews.llvm.org/D84420
 2020-09-16 17:20:27 +02:00
Jay Foad 590964c835 [AMDGPU] More accurate gfx10 latencies 
Differential Revision: https://reviews.llvm.org/D81012
 2020-06-04 10:29:32 +01:00
Matt Arsenault 9c928649a0 AMDGPU: Fix interaction of tfe and d16 
This using the wrong result register, and dropping the result entirely
for v2f16. This would fail to select on the scalar case. I believe it
was also mishandling packed/unpacked subtargets.
 2020-01-22 09:26:17 -05:00