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5 Commits

Author SHA1 Message Date
Tom Stellard ca69a53bae Revert "R600: Non vector only instruction can be scheduled on trans unit" 
This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6.

llvm-svn: 187526
 2013-07-31 20:43:27 +00:00
Vincent Lejeune df18804e26 R600: Non vector only instruction can be scheduled on trans unit 
llvm-svn: 187514
 2013-07-31 19:31:56 +00:00
Aaron Watry 00aeb119db R600/SI: Expand and of v2i32/v4i32 for SI 
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 184837
 2013-06-25 13:55:23 +00:00
Vincent Lejeune f97af796a9 R600: Prettier asmPrint of Alu 
llvm-svn: 180956
 2013-05-02 21:52:30 +00:00
Tom Stellard 5a6b0d828b R600: Reorganize lit tests and document how they should be organized 
llvm-svn: 179828
 2013-04-19 02:10:53 +00:00