0344cdfe39
R600: Add 64-bit float load/store support
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* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions
Tom Stellard:
- Mark vec2 operations as expand. The addition of a vec2 register
class made them all legal.
Patch by: Dmitry Cherkassov
Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
llvm-svn: 187582
2013-08-01 15:23:42 +00:00
ca69a53bae
Revert "R600: Non vector only instruction can be scheduled on trans unit"
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This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6.
llvm-svn: 187526
2013-07-31 20:43:27 +00:00
df18804e26
R600: Non vector only instruction can be scheduled on trans unit
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llvm-svn: 187514
2013-07-31 19:31:56 +00:00
4b5b849753
R600: Schedule copy from phys register at beginning of block
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It allows regalloc pass to remove them by trivially assigning associated reg
llvm-svn: 183336
2013-06-05 20:27:35 +00:00
f83df1f1cb
R600: use capital letter for PV channel
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llvm-svn: 183107
2013-06-03 15:44:35 +00:00
3d5118ca40
R600: Use bottom up scheduling algorithm
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llvm-svn: 182129
2013-05-17 16:50:56 +00:00
f97af796a9
R600: Prettier asmPrint of Alu
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llvm-svn: 180956
2013-05-02 21:52:30 +00:00
5a6b0d828b
R600: Reorganize lit tests and document how they should be organized
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llvm-svn: 179828
2013-04-19 02:10:53 +00:00
75aadc2813
Add R600 backend
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A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX
llvm-svn: 169915
2012-12-11 21:25:42 +00:00
fc3db614c0
Revert "test/CodeGen/R600: Add some basic tests v6"
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This reverts commit 11d3457afcda7848448dd7f11b2ede6552ffb9ea.
llvm-svn: 160300
2012-07-16 18:19:43 +00:00
6693fbe3eb
test/CodeGen/R600: Add some basic tests v6
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llvm-svn: 160273
2012-07-16 14:17:19 +00:00
Tom Stellard