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4 Commits

Author SHA1 Message Date
Andrew Trick 8523b16ff5 Instruction scheduling itinerary for Intel Atom. 
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

llvm-svn: 149558
 2012-02-01 23:20:51 +00:00
Jakob Stoklund Olesen e20fec7732 Fix one more batch of X86 tests to be register allocation dependent. 
llvm-svn: 128919
 2011-04-05 20:20:30 +00:00
Bill Wendling a136521a17 MorphNodeTo doesn't preserve the memory operands. Because we're morphing a node 
into the same node, but with different non-memory operands, we need to replace
the memory operands after it's finished morphing.

llvm-svn: 106643
 2010-06-23 18:16:24 +00:00
Arnold Schwaighofer 30ece5b807 Mark the return address stack slot as mutable when moving the return address 
during a tail call. A parameter might overwrite this stack slot during the tail
call. 

The sequence during a tail call is:
1.) load return address to temp reg
2.) move parameters (might involve storing to return address stack slot)
3.) store return address to new location from temp reg

If the stack location is marked immutable CodeGen can colocate load (1) with the
store (3).

This fixes bug 6225.

llvm-svn: 96783
 2010-02-22 16:18:09 +00:00